0001 // SPDX-License-Identifier: GPL-2.0+ OR MIT
0002 //
0003 // Device Tree Source for UniPhier Pro5 SoC
0004 //
0005 // Copyright (C) 2015-2016 Socionext Inc.
0006 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
0007
0008 / {
0009 compatible = "socionext,uniphier-pro5";
0010 #address-cells = <1>;
0011 #size-cells = <1>;
0012
0013 cpus {
0014 #address-cells = <1>;
0015 #size-cells = <0>;
0016
0017 cpu@0 {
0018 device_type = "cpu";
0019 compatible = "arm,cortex-a9";
0020 reg = <0>;
0021 clocks = <&sys_clk 32>;
0022 enable-method = "psci";
0023 next-level-cache = <&l2>;
0024 operating-points-v2 = <&cpu_opp>;
0025 };
0026
0027 cpu@1 {
0028 device_type = "cpu";
0029 compatible = "arm,cortex-a9";
0030 reg = <1>;
0031 clocks = <&sys_clk 32>;
0032 enable-method = "psci";
0033 next-level-cache = <&l2>;
0034 operating-points-v2 = <&cpu_opp>;
0035 };
0036 };
0037
0038 cpu_opp: opp-table {
0039 compatible = "operating-points-v2";
0040 opp-shared;
0041
0042 opp-100000000 {
0043 opp-hz = /bits/ 64 <100000000>;
0044 clock-latency-ns = <300>;
0045 };
0046 opp-116667000 {
0047 opp-hz = /bits/ 64 <116667000>;
0048 clock-latency-ns = <300>;
0049 };
0050 opp-150000000 {
0051 opp-hz = /bits/ 64 <150000000>;
0052 clock-latency-ns = <300>;
0053 };
0054 opp-175000000 {
0055 opp-hz = /bits/ 64 <175000000>;
0056 clock-latency-ns = <300>;
0057 };
0058 opp-200000000 {
0059 opp-hz = /bits/ 64 <200000000>;
0060 clock-latency-ns = <300>;
0061 };
0062 opp-233334000 {
0063 opp-hz = /bits/ 64 <233334000>;
0064 clock-latency-ns = <300>;
0065 };
0066 opp-300000000 {
0067 opp-hz = /bits/ 64 <300000000>;
0068 clock-latency-ns = <300>;
0069 };
0070 opp-350000000 {
0071 opp-hz = /bits/ 64 <350000000>;
0072 clock-latency-ns = <300>;
0073 };
0074 opp-400000000 {
0075 opp-hz = /bits/ 64 <400000000>;
0076 clock-latency-ns = <300>;
0077 };
0078 opp-466667000 {
0079 opp-hz = /bits/ 64 <466667000>;
0080 clock-latency-ns = <300>;
0081 };
0082 opp-600000000 {
0083 opp-hz = /bits/ 64 <600000000>;
0084 clock-latency-ns = <300>;
0085 };
0086 opp-700000000 {
0087 opp-hz = /bits/ 64 <700000000>;
0088 clock-latency-ns = <300>;
0089 };
0090 opp-800000000 {
0091 opp-hz = /bits/ 64 <800000000>;
0092 clock-latency-ns = <300>;
0093 };
0094 opp-933334000 {
0095 opp-hz = /bits/ 64 <933334000>;
0096 clock-latency-ns = <300>;
0097 };
0098 opp-1200000000 {
0099 opp-hz = /bits/ 64 <1200000000>;
0100 clock-latency-ns = <300>;
0101 };
0102 opp-1400000000 {
0103 opp-hz = /bits/ 64 <1400000000>;
0104 clock-latency-ns = <300>;
0105 };
0106 };
0107
0108 psci {
0109 compatible = "arm,psci-0.2";
0110 method = "smc";
0111 };
0112
0113 clocks {
0114 refclk: ref {
0115 compatible = "fixed-clock";
0116 #clock-cells = <0>;
0117 clock-frequency = <20000000>;
0118 };
0119
0120 arm_timer_clk: arm-timer {
0121 #clock-cells = <0>;
0122 compatible = "fixed-clock";
0123 clock-frequency = <50000000>;
0124 };
0125 };
0126
0127 soc {
0128 compatible = "simple-bus";
0129 #address-cells = <1>;
0130 #size-cells = <1>;
0131 ranges;
0132 interrupt-parent = <&intc>;
0133
0134 l2: cache-controller@500c0000 {
0135 compatible = "socionext,uniphier-system-cache";
0136 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
0137 <0x506c0000 0x400>;
0138 interrupts = <0 190 4>, <0 191 4>;
0139 cache-unified;
0140 cache-size = <(2 * 1024 * 1024)>;
0141 cache-sets = <512>;
0142 cache-line-size = <128>;
0143 cache-level = <2>;
0144 next-level-cache = <&l3>;
0145 };
0146
0147 l3: cache-controller@500c8000 {
0148 compatible = "socionext,uniphier-system-cache";
0149 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
0150 <0x506c8000 0x400>;
0151 interrupts = <0 174 4>, <0 175 4>;
0152 cache-unified;
0153 cache-size = <(2 * 1024 * 1024)>;
0154 cache-sets = <512>;
0155 cache-line-size = <256>;
0156 cache-level = <3>;
0157 };
0158
0159 spi0: spi@54006000 {
0160 compatible = "socionext,uniphier-scssi";
0161 status = "disabled";
0162 reg = <0x54006000 0x100>;
0163 #address-cells = <1>;
0164 #size-cells = <0>;
0165 interrupts = <0 39 4>;
0166 pinctrl-names = "default";
0167 pinctrl-0 = <&pinctrl_spi0>;
0168 clocks = <&peri_clk 11>;
0169 resets = <&peri_rst 11>;
0170 };
0171
0172 spi1: spi@54006100 {
0173 compatible = "socionext,uniphier-scssi";
0174 status = "disabled";
0175 reg = <0x54006100 0x100>;
0176 #address-cells = <1>;
0177 #size-cells = <0>;
0178 interrupts = <0 216 4>;
0179 pinctrl-names = "default";
0180 pinctrl-0 = <&pinctrl_spi1>;
0181 clocks = <&peri_clk 11>; /* common with spi0 */
0182 resets = <&peri_rst 12>;
0183 };
0184
0185 serial0: serial@54006800 {
0186 compatible = "socionext,uniphier-uart";
0187 status = "disabled";
0188 reg = <0x54006800 0x40>;
0189 interrupts = <0 33 4>;
0190 pinctrl-names = "default";
0191 pinctrl-0 = <&pinctrl_uart0>;
0192 clocks = <&peri_clk 0>;
0193 resets = <&peri_rst 0>;
0194 };
0195
0196 serial1: serial@54006900 {
0197 compatible = "socionext,uniphier-uart";
0198 status = "disabled";
0199 reg = <0x54006900 0x40>;
0200 interrupts = <0 35 4>;
0201 pinctrl-names = "default";
0202 pinctrl-0 = <&pinctrl_uart1>;
0203 clocks = <&peri_clk 1>;
0204 resets = <&peri_rst 1>;
0205 };
0206
0207 serial2: serial@54006a00 {
0208 compatible = "socionext,uniphier-uart";
0209 status = "disabled";
0210 reg = <0x54006a00 0x40>;
0211 interrupts = <0 37 4>;
0212 pinctrl-names = "default";
0213 pinctrl-0 = <&pinctrl_uart2>;
0214 clocks = <&peri_clk 2>;
0215 resets = <&peri_rst 2>;
0216 };
0217
0218 serial3: serial@54006b00 {
0219 compatible = "socionext,uniphier-uart";
0220 status = "disabled";
0221 reg = <0x54006b00 0x40>;
0222 interrupts = <0 177 4>;
0223 pinctrl-names = "default";
0224 pinctrl-0 = <&pinctrl_uart3>;
0225 clocks = <&peri_clk 3>;
0226 resets = <&peri_rst 3>;
0227 };
0228
0229 gpio: gpio@55000000 {
0230 compatible = "socionext,uniphier-gpio";
0231 reg = <0x55000000 0x200>;
0232 interrupt-parent = <&aidet>;
0233 interrupt-controller;
0234 #interrupt-cells = <2>;
0235 gpio-controller;
0236 #gpio-cells = <2>;
0237 gpio-ranges = <&pinctrl 0 0 0>;
0238 gpio-ranges-group-names = "gpio_range";
0239 ngpios = <248>;
0240 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
0241 };
0242
0243 i2c0: i2c@58780000 {
0244 compatible = "socionext,uniphier-fi2c";
0245 status = "disabled";
0246 reg = <0x58780000 0x80>;
0247 #address-cells = <1>;
0248 #size-cells = <0>;
0249 interrupts = <0 41 4>;
0250 pinctrl-names = "default";
0251 pinctrl-0 = <&pinctrl_i2c0>;
0252 clocks = <&peri_clk 4>;
0253 resets = <&peri_rst 4>;
0254 clock-frequency = <100000>;
0255 };
0256
0257 i2c1: i2c@58781000 {
0258 compatible = "socionext,uniphier-fi2c";
0259 status = "disabled";
0260 reg = <0x58781000 0x80>;
0261 #address-cells = <1>;
0262 #size-cells = <0>;
0263 interrupts = <0 42 4>;
0264 pinctrl-names = "default";
0265 pinctrl-0 = <&pinctrl_i2c1>;
0266 clocks = <&peri_clk 5>;
0267 resets = <&peri_rst 5>;
0268 clock-frequency = <100000>;
0269 };
0270
0271 i2c2: i2c@58782000 {
0272 compatible = "socionext,uniphier-fi2c";
0273 status = "disabled";
0274 reg = <0x58782000 0x80>;
0275 #address-cells = <1>;
0276 #size-cells = <0>;
0277 interrupts = <0 43 4>;
0278 pinctrl-names = "default";
0279 pinctrl-0 = <&pinctrl_i2c2>;
0280 clocks = <&peri_clk 6>;
0281 resets = <&peri_rst 6>;
0282 clock-frequency = <100000>;
0283 };
0284
0285 i2c3: i2c@58783000 {
0286 compatible = "socionext,uniphier-fi2c";
0287 status = "disabled";
0288 reg = <0x58783000 0x80>;
0289 #address-cells = <1>;
0290 #size-cells = <0>;
0291 interrupts = <0 44 4>;
0292 pinctrl-names = "default";
0293 pinctrl-0 = <&pinctrl_i2c3>;
0294 clocks = <&peri_clk 7>;
0295 resets = <&peri_rst 7>;
0296 clock-frequency = <100000>;
0297 };
0298
0299 /* i2c4 does not exist */
0300
0301 /* chip-internal connection for DMD */
0302 i2c5: i2c@58785000 {
0303 compatible = "socionext,uniphier-fi2c";
0304 reg = <0x58785000 0x80>;
0305 #address-cells = <1>;
0306 #size-cells = <0>;
0307 interrupts = <0 25 4>;
0308 clocks = <&peri_clk 9>;
0309 resets = <&peri_rst 9>;
0310 clock-frequency = <400000>;
0311 };
0312
0313 /* chip-internal connection for HDMI */
0314 i2c6: i2c@58786000 {
0315 compatible = "socionext,uniphier-fi2c";
0316 reg = <0x58786000 0x80>;
0317 #address-cells = <1>;
0318 #size-cells = <0>;
0319 interrupts = <0 26 4>;
0320 clocks = <&peri_clk 10>;
0321 resets = <&peri_rst 10>;
0322 clock-frequency = <400000>;
0323 };
0324
0325 system_bus: system-bus@58c00000 {
0326 compatible = "socionext,uniphier-system-bus";
0327 status = "disabled";
0328 reg = <0x58c00000 0x400>;
0329 #address-cells = <2>;
0330 #size-cells = <1>;
0331 pinctrl-names = "default";
0332 pinctrl-0 = <&pinctrl_system_bus>;
0333 };
0334
0335 smpctrl@59801000 {
0336 compatible = "socionext,uniphier-smpctrl";
0337 reg = <0x59801000 0x400>;
0338 };
0339
0340 sdctrl@59810000 {
0341 compatible = "socionext,uniphier-pro5-sdctrl",
0342 "simple-mfd", "syscon";
0343 reg = <0x59810000 0x400>;
0344
0345 sd_clk: clock {
0346 compatible = "socionext,uniphier-pro5-sd-clock";
0347 #clock-cells = <1>;
0348 };
0349
0350 sd_rst: reset {
0351 compatible = "socionext,uniphier-pro5-sd-reset";
0352 #reset-cells = <1>;
0353 };
0354 };
0355
0356 perictrl@59820000 {
0357 compatible = "socionext,uniphier-pro5-perictrl",
0358 "simple-mfd", "syscon";
0359 reg = <0x59820000 0x200>;
0360
0361 peri_clk: clock {
0362 compatible = "socionext,uniphier-pro5-peri-clock";
0363 #clock-cells = <1>;
0364 };
0365
0366 peri_rst: reset {
0367 compatible = "socionext,uniphier-pro5-peri-reset";
0368 #reset-cells = <1>;
0369 };
0370 };
0371
0372 soc-glue@5f800000 {
0373 compatible = "socionext,uniphier-pro5-soc-glue",
0374 "simple-mfd", "syscon";
0375 reg = <0x5f800000 0x2000>;
0376
0377 pinctrl: pinctrl {
0378 compatible = "socionext,uniphier-pro5-pinctrl";
0379 };
0380 };
0381
0382 soc-glue@5f900000 {
0383 compatible = "socionext,uniphier-pro5-soc-glue-debug",
0384 "simple-mfd";
0385 #address-cells = <1>;
0386 #size-cells = <1>;
0387 ranges = <0 0x5f900000 0x2000>;
0388
0389 efuse@100 {
0390 compatible = "socionext,uniphier-efuse";
0391 reg = <0x100 0x28>;
0392 };
0393
0394 efuse@130 {
0395 compatible = "socionext,uniphier-efuse";
0396 reg = <0x130 0x8>;
0397 };
0398
0399 efuse@200 {
0400 compatible = "socionext,uniphier-efuse";
0401 reg = <0x200 0x28>;
0402 };
0403
0404 efuse@300 {
0405 compatible = "socionext,uniphier-efuse";
0406 reg = <0x300 0x14>;
0407 };
0408
0409 efuse@400 {
0410 compatible = "socionext,uniphier-efuse";
0411 reg = <0x400 0x8>;
0412 };
0413 };
0414
0415 xdmac: dma-controller@5fc10000 {
0416 compatible = "socionext,uniphier-xdmac";
0417 reg = <0x5fc10000 0x5300>;
0418 interrupts = <0 188 4>;
0419 dma-channels = <16>;
0420 #dma-cells = <2>;
0421 };
0422
0423 aidet: interrupt-controller@5fc20000 {
0424 compatible = "socionext,uniphier-pro5-aidet";
0425 reg = <0x5fc20000 0x200>;
0426 interrupt-controller;
0427 #interrupt-cells = <2>;
0428 };
0429
0430 timer@60000200 {
0431 compatible = "arm,cortex-a9-global-timer";
0432 reg = <0x60000200 0x20>;
0433 interrupts = <1 11 0x304>;
0434 clocks = <&arm_timer_clk>;
0435 };
0436
0437 timer@60000600 {
0438 compatible = "arm,cortex-a9-twd-timer";
0439 reg = <0x60000600 0x20>;
0440 interrupts = <1 13 0x304>;
0441 clocks = <&arm_timer_clk>;
0442 };
0443
0444 intc: interrupt-controller@60001000 {
0445 compatible = "arm,cortex-a9-gic";
0446 reg = <0x60001000 0x1000>,
0447 <0x60000100 0x100>;
0448 #interrupt-cells = <3>;
0449 interrupt-controller;
0450 };
0451
0452 sysctrl@61840000 {
0453 compatible = "socionext,uniphier-pro5-sysctrl",
0454 "simple-mfd", "syscon";
0455 reg = <0x61840000 0x10000>;
0456
0457 sys_clk: clock {
0458 compatible = "socionext,uniphier-pro5-clock";
0459 #clock-cells = <1>;
0460 };
0461
0462 sys_rst: reset {
0463 compatible = "socionext,uniphier-pro5-reset";
0464 #reset-cells = <1>;
0465 };
0466 };
0467
0468 usb0: usb@65a00000 {
0469 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
0470 status = "disabled";
0471 reg = <0x65a00000 0xcd00>;
0472 interrupt-names = "host";
0473 interrupts = <0 134 4>;
0474 pinctrl-names = "default";
0475 pinctrl-0 = <&pinctrl_usb0>;
0476 clock-names = "ref", "bus_early", "suspend";
0477 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
0478 resets = <&usb0_rst 15>;
0479 phys = <&usb0_hsphy0>, <&usb0_ssphy0>;
0480 dr_mode = "host";
0481 };
0482
0483 usb-glue@65b00000 {
0484 compatible = "socionext,uniphier-pro5-dwc3-glue",
0485 "simple-mfd";
0486 #address-cells = <1>;
0487 #size-cells = <1>;
0488 ranges = <0 0x65b00000 0x400>;
0489
0490 usb0_rst: reset@0 {
0491 compatible = "socionext,uniphier-pro5-usb3-reset";
0492 reg = <0x0 0x4>;
0493 #reset-cells = <1>;
0494 clock-names = "gio", "link";
0495 clocks = <&sys_clk 12>, <&sys_clk 14>;
0496 reset-names = "gio", "link";
0497 resets = <&sys_rst 12>, <&sys_rst 14>;
0498 };
0499
0500 usb0_vbus0: regulator@100 {
0501 compatible = "socionext,uniphier-pro5-usb3-regulator";
0502 reg = <0x100 0x10>;
0503 clock-names = "gio", "link";
0504 clocks = <&sys_clk 12>, <&sys_clk 14>;
0505 reset-names = "gio", "link";
0506 resets = <&sys_rst 12>, <&sys_rst 14>;
0507 };
0508
0509 usb0_hsphy0: hs-phy@280 {
0510 compatible = "socionext,uniphier-pro5-usb3-hsphy";
0511 reg = <0x280 0x10>;
0512 #phy-cells = <0>;
0513 clock-names = "gio", "link";
0514 clocks = <&sys_clk 12>, <&sys_clk 14>;
0515 reset-names = "gio", "link";
0516 resets = <&sys_rst 12>, <&sys_rst 14>;
0517 vbus-supply = <&usb0_vbus0>;
0518 };
0519
0520 usb0_ssphy0: ss-phy@380 {
0521 compatible = "socionext,uniphier-pro5-usb3-ssphy";
0522 reg = <0x380 0x10>;
0523 #phy-cells = <0>;
0524 clock-names = "gio", "link";
0525 clocks = <&sys_clk 12>, <&sys_clk 14>;
0526 reset-names = "gio", "link";
0527 resets = <&sys_rst 12>, <&sys_rst 14>;
0528 vbus-supply = <&usb0_vbus0>;
0529 };
0530 };
0531
0532 usb1: usb@65c00000 {
0533 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
0534 status = "disabled";
0535 reg = <0x65c00000 0xcd00>;
0536 interrupt-names = "host";
0537 interrupts = <0 137 4>;
0538 pinctrl-names = "default";
0539 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
0540 clock-names = "ref", "bus_early", "suspend";
0541 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
0542 resets = <&usb1_rst 15>;
0543 phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>;
0544 dr_mode = "host";
0545 };
0546
0547 usb-glue@65d00000 {
0548 compatible = "socionext,uniphier-pro5-dwc3-glue",
0549 "simple-mfd";
0550 #address-cells = <1>;
0551 #size-cells = <1>;
0552 ranges = <0 0x65d00000 0x400>;
0553
0554 usb1_rst: reset@0 {
0555 compatible = "socionext,uniphier-pro5-usb3-reset";
0556 reg = <0x0 0x4>;
0557 #reset-cells = <1>;
0558 clock-names = "gio", "link";
0559 clocks = <&sys_clk 12>, <&sys_clk 15>;
0560 reset-names = "gio", "link";
0561 resets = <&sys_rst 12>, <&sys_rst 15>;
0562 };
0563
0564 usb1_vbus0: regulator@100 {
0565 compatible = "socionext,uniphier-pro5-usb3-regulator";
0566 reg = <0x100 0x10>;
0567 clock-names = "gio", "link";
0568 clocks = <&sys_clk 12>, <&sys_clk 15>;
0569 reset-names = "gio", "link";
0570 resets = <&sys_rst 12>, <&sys_rst 15>;
0571 };
0572
0573 usb1_vbus1: regulator@110 {
0574 compatible = "socionext,uniphier-pro5-usb3-regulator";
0575 reg = <0x110 0x10>;
0576 clock-names = "gio", "link";
0577 clocks = <&sys_clk 12>, <&sys_clk 15>;
0578 reset-names = "gio", "link";
0579 resets = <&sys_rst 12>, <&sys_rst 15>;
0580 };
0581
0582 usb1_hsphy0: hs-phy@280 {
0583 compatible = "socionext,uniphier-pro5-usb3-hsphy";
0584 reg = <0x280 0x10>;
0585 #phy-cells = <0>;
0586 clock-names = "gio", "link";
0587 clocks = <&sys_clk 12>, <&sys_clk 15>;
0588 reset-names = "gio", "link";
0589 resets = <&sys_rst 12>, <&sys_rst 15>;
0590 vbus-supply = <&usb1_vbus0>;
0591 };
0592
0593 usb1_hsphy1: hs-phy@290 {
0594 compatible = "socionext,uniphier-pro5-usb3-hsphy";
0595 reg = <0x290 0x10>;
0596 #phy-cells = <0>;
0597 clock-names = "gio", "link";
0598 clocks = <&sys_clk 12>, <&sys_clk 15>;
0599 reset-names = "gio", "link";
0600 resets = <&sys_rst 12>, <&sys_rst 15>;
0601 vbus-supply = <&usb1_vbus1>;
0602 };
0603
0604 usb1_ssphy0: ss-phy@380 {
0605 compatible = "socionext,uniphier-pro5-usb3-ssphy";
0606 reg = <0x380 0x10>;
0607 #phy-cells = <0>;
0608 clock-names = "gio", "link";
0609 clocks = <&sys_clk 12>, <&sys_clk 15>;
0610 reset-names = "gio", "link";
0611 resets = <&sys_rst 12>, <&sys_rst 15>;
0612 vbus-supply = <&usb1_vbus0>;
0613 };
0614 };
0615
0616 pcie_ep: pcie-ep@66000000 {
0617 compatible = "socionext,uniphier-pro5-pcie-ep",
0618 "snps,dw-pcie-ep";
0619 status = "disabled";
0620 reg-names = "dbi", "dbi2", "link", "addr_space";
0621 reg = <0x66000000 0x1000>, <0x66001000 0x1000>,
0622 <0x66010000 0x10000>, <0x67000000 0x400000>;
0623 pinctrl-names = "default";
0624 pinctrl-0 = <&pinctrl_pcie>;
0625 clock-names = "gio", "link";
0626 clocks = <&sys_clk 12>, <&sys_clk 24>;
0627 reset-names = "gio", "link";
0628 resets = <&sys_rst 12>, <&sys_rst 24>;
0629 num-ib-windows = <16>;
0630 num-ob-windows = <16>;
0631 num-lanes = <4>;
0632 phy-names = "pcie-phy";
0633 phys = <&pcie_phy>;
0634 };
0635
0636 pcie_phy: phy@66038000 {
0637 compatible = "socionext,uniphier-pro5-pcie-phy";
0638 reg = <0x66038000 0x4000>;
0639 #phy-cells = <0>;
0640 clock-names = "gio", "link";
0641 clocks = <&sys_clk 12>, <&sys_clk 24>;
0642 reset-names = "gio", "link";
0643 resets = <&sys_rst 12>, <&sys_rst 24>;
0644 };
0645
0646 nand: nand-controller@68000000 {
0647 compatible = "socionext,uniphier-denali-nand-v5b";
0648 status = "disabled";
0649 reg-names = "nand_data", "denali_reg";
0650 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
0651 #address-cells = <1>;
0652 #size-cells = <0>;
0653 interrupts = <0 65 4>;
0654 pinctrl-names = "default";
0655 pinctrl-0 = <&pinctrl_nand>;
0656 clock-names = "nand", "nand_x", "ecc";
0657 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
0658 reset-names = "nand", "reg";
0659 resets = <&sys_rst 2>, <&sys_rst 2>;
0660 };
0661
0662 emmc: mmc@68400000 {
0663 compatible = "socionext,uniphier-sd-v3.1";
0664 status = "disabled";
0665 reg = <0x68400000 0x800>;
0666 interrupts = <0 78 4>;
0667 pinctrl-names = "default";
0668 pinctrl-0 = <&pinctrl_emmc>;
0669 clocks = <&sd_clk 1>;
0670 reset-names = "host", "hw";
0671 resets = <&sd_rst 1>, <&sd_rst 6>;
0672 bus-width = <8>;
0673 cap-mmc-highspeed;
0674 cap-mmc-hw-reset;
0675 non-removable;
0676 };
0677
0678 sd: mmc@68800000 {
0679 compatible = "socionext,uniphier-sd-v3.1";
0680 status = "disabled";
0681 reg = <0x68800000 0x800>;
0682 interrupts = <0 76 4>;
0683 pinctrl-names = "default", "uhs";
0684 pinctrl-0 = <&pinctrl_sd>;
0685 pinctrl-1 = <&pinctrl_sd_uhs>;
0686 clocks = <&sd_clk 0>;
0687 reset-names = "host";
0688 resets = <&sd_rst 0>;
0689 bus-width = <4>;
0690 cap-sd-highspeed;
0691 sd-uhs-sdr12;
0692 sd-uhs-sdr25;
0693 sd-uhs-sdr50;
0694 };
0695 };
0696 };
0697
0698 #include "uniphier-pinctrl.dtsi"
