0001 // SPDX-License-Identifier: GPL-2.0+ OR MIT
0002 //
0003 // Device Tree Source for UniPhier Pro4 SoC
0004 //
0005 // Copyright (C) 2015-2016 Socionext Inc.
0006 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
0007
0008 #include <dt-bindings/gpio/uniphier-gpio.h>
0009
0010 / {
0011 compatible = "socionext,uniphier-pro4";
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014
0015 cpus {
0016 #address-cells = <1>;
0017 #size-cells = <0>;
0018
0019 cpu@0 {
0020 device_type = "cpu";
0021 compatible = "arm,cortex-a9";
0022 reg = <0>;
0023 enable-method = "psci";
0024 next-level-cache = <&l2>;
0025 };
0026
0027 cpu@1 {
0028 device_type = "cpu";
0029 compatible = "arm,cortex-a9";
0030 reg = <1>;
0031 enable-method = "psci";
0032 next-level-cache = <&l2>;
0033 };
0034 };
0035
0036 psci {
0037 compatible = "arm,psci-0.2";
0038 method = "smc";
0039 };
0040
0041 clocks {
0042 refclk: ref {
0043 compatible = "fixed-clock";
0044 #clock-cells = <0>;
0045 clock-frequency = <25000000>;
0046 };
0047
0048 arm_timer_clk: arm-timer {
0049 #clock-cells = <0>;
0050 compatible = "fixed-clock";
0051 clock-frequency = <50000000>;
0052 };
0053 };
0054
0055 soc {
0056 compatible = "simple-bus";
0057 #address-cells = <1>;
0058 #size-cells = <1>;
0059 ranges;
0060 interrupt-parent = <&intc>;
0061
0062 l2: cache-controller@500c0000 {
0063 compatible = "socionext,uniphier-system-cache";
0064 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
0065 <0x506c0000 0x400>;
0066 interrupts = <0 174 4>, <0 175 4>;
0067 cache-unified;
0068 cache-size = <(768 * 1024)>;
0069 cache-sets = <256>;
0070 cache-line-size = <128>;
0071 cache-level = <2>;
0072 };
0073
0074 spi0: spi@54006000 {
0075 compatible = "socionext,uniphier-scssi";
0076 status = "disabled";
0077 reg = <0x54006000 0x100>;
0078 #address-cells = <1>;
0079 #size-cells = <0>;
0080 interrupts = <0 39 4>;
0081 pinctrl-names = "default";
0082 pinctrl-0 = <&pinctrl_spi0>;
0083 clocks = <&peri_clk 11>;
0084 resets = <&peri_rst 11>;
0085 };
0086
0087 serial0: serial@54006800 {
0088 compatible = "socionext,uniphier-uart";
0089 status = "disabled";
0090 reg = <0x54006800 0x40>;
0091 interrupts = <0 33 4>;
0092 pinctrl-names = "default";
0093 pinctrl-0 = <&pinctrl_uart0>;
0094 clocks = <&peri_clk 0>;
0095 resets = <&peri_rst 0>;
0096 };
0097
0098 serial1: serial@54006900 {
0099 compatible = "socionext,uniphier-uart";
0100 status = "disabled";
0101 reg = <0x54006900 0x40>;
0102 interrupts = <0 35 4>;
0103 pinctrl-names = "default";
0104 pinctrl-0 = <&pinctrl_uart1>;
0105 clocks = <&peri_clk 1>;
0106 resets = <&peri_rst 1>;
0107 };
0108
0109 serial2: serial@54006a00 {
0110 compatible = "socionext,uniphier-uart";
0111 status = "disabled";
0112 reg = <0x54006a00 0x40>;
0113 interrupts = <0 37 4>;
0114 pinctrl-names = "default";
0115 pinctrl-0 = <&pinctrl_uart2>;
0116 clocks = <&peri_clk 2>;
0117 resets = <&peri_rst 2>;
0118 };
0119
0120 serial3: serial@54006b00 {
0121 compatible = "socionext,uniphier-uart";
0122 status = "disabled";
0123 reg = <0x54006b00 0x40>;
0124 interrupts = <0 177 4>;
0125 pinctrl-names = "default";
0126 pinctrl-0 = <&pinctrl_uart3>;
0127 clocks = <&peri_clk 3>;
0128 resets = <&peri_rst 3>;
0129 };
0130
0131 gpio: gpio@55000000 {
0132 compatible = "socionext,uniphier-gpio";
0133 reg = <0x55000000 0x200>;
0134 interrupt-parent = <&aidet>;
0135 interrupt-controller;
0136 #interrupt-cells = <2>;
0137 gpio-controller;
0138 #gpio-cells = <2>;
0139 gpio-ranges = <&pinctrl 0 0 0>;
0140 gpio-ranges-group-names = "gpio_range";
0141 ngpios = <248>;
0142 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
0143 };
0144
0145 i2c0: i2c@58780000 {
0146 compatible = "socionext,uniphier-fi2c";
0147 status = "disabled";
0148 reg = <0x58780000 0x80>;
0149 #address-cells = <1>;
0150 #size-cells = <0>;
0151 interrupts = <0 41 4>;
0152 pinctrl-names = "default";
0153 pinctrl-0 = <&pinctrl_i2c0>;
0154 clocks = <&peri_clk 4>;
0155 resets = <&peri_rst 4>;
0156 clock-frequency = <100000>;
0157 };
0158
0159 i2c1: i2c@58781000 {
0160 compatible = "socionext,uniphier-fi2c";
0161 status = "disabled";
0162 reg = <0x58781000 0x80>;
0163 #address-cells = <1>;
0164 #size-cells = <0>;
0165 interrupts = <0 42 4>;
0166 pinctrl-names = "default";
0167 pinctrl-0 = <&pinctrl_i2c1>;
0168 clocks = <&peri_clk 5>;
0169 resets = <&peri_rst 5>;
0170 clock-frequency = <100000>;
0171 };
0172
0173 i2c2: i2c@58782000 {
0174 compatible = "socionext,uniphier-fi2c";
0175 status = "disabled";
0176 reg = <0x58782000 0x80>;
0177 #address-cells = <1>;
0178 #size-cells = <0>;
0179 interrupts = <0 43 4>;
0180 pinctrl-names = "default";
0181 pinctrl-0 = <&pinctrl_i2c2>;
0182 clocks = <&peri_clk 6>;
0183 resets = <&peri_rst 6>;
0184 clock-frequency = <100000>;
0185 };
0186
0187 i2c3: i2c@58783000 {
0188 compatible = "socionext,uniphier-fi2c";
0189 status = "disabled";
0190 reg = <0x58783000 0x80>;
0191 #address-cells = <1>;
0192 #size-cells = <0>;
0193 interrupts = <0 44 4>;
0194 pinctrl-names = "default";
0195 pinctrl-0 = <&pinctrl_i2c3>;
0196 clocks = <&peri_clk 7>;
0197 resets = <&peri_rst 7>;
0198 clock-frequency = <100000>;
0199 };
0200
0201 /* i2c4 does not exist */
0202
0203 /* chip-internal connection for DMD */
0204 i2c5: i2c@58785000 {
0205 compatible = "socionext,uniphier-fi2c";
0206 reg = <0x58785000 0x80>;
0207 #address-cells = <1>;
0208 #size-cells = <0>;
0209 interrupts = <0 25 4>;
0210 clocks = <&peri_clk 9>;
0211 resets = <&peri_rst 9>;
0212 clock-frequency = <400000>;
0213 };
0214
0215 /* chip-internal connection for HDMI */
0216 i2c6: i2c@58786000 {
0217 compatible = "socionext,uniphier-fi2c";
0218 reg = <0x58786000 0x80>;
0219 #address-cells = <1>;
0220 #size-cells = <0>;
0221 interrupts = <0 26 4>;
0222 clocks = <&peri_clk 10>;
0223 resets = <&peri_rst 10>;
0224 clock-frequency = <400000>;
0225 };
0226
0227 system_bus: system-bus@58c00000 {
0228 compatible = "socionext,uniphier-system-bus";
0229 status = "disabled";
0230 reg = <0x58c00000 0x400>;
0231 #address-cells = <2>;
0232 #size-cells = <1>;
0233 pinctrl-names = "default";
0234 pinctrl-0 = <&pinctrl_system_bus>;
0235 };
0236
0237 smpctrl@59801000 {
0238 compatible = "socionext,uniphier-smpctrl";
0239 reg = <0x59801000 0x400>;
0240 };
0241
0242 mioctrl@59810000 {
0243 compatible = "socionext,uniphier-pro4-mioctrl",
0244 "simple-mfd", "syscon";
0245 reg = <0x59810000 0x800>;
0246
0247 mio_clk: clock {
0248 compatible = "socionext,uniphier-pro4-mio-clock";
0249 #clock-cells = <1>;
0250 };
0251
0252 mio_rst: reset {
0253 compatible = "socionext,uniphier-pro4-mio-reset";
0254 #reset-cells = <1>;
0255 };
0256 };
0257
0258 perictrl@59820000 {
0259 compatible = "socionext,uniphier-pro4-perictrl",
0260 "simple-mfd", "syscon";
0261 reg = <0x59820000 0x200>;
0262
0263 peri_clk: clock {
0264 compatible = "socionext,uniphier-pro4-peri-clock";
0265 #clock-cells = <1>;
0266 };
0267
0268 peri_rst: reset {
0269 compatible = "socionext,uniphier-pro4-peri-reset";
0270 #reset-cells = <1>;
0271 };
0272 };
0273
0274 dmac: dma-controller@5a000000 {
0275 compatible = "socionext,uniphier-mio-dmac";
0276 reg = <0x5a000000 0x1000>;
0277 interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
0278 <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
0279 clocks = <&mio_clk 7>;
0280 resets = <&mio_rst 7>;
0281 #dma-cells = <1>;
0282 };
0283
0284 sd: mmc@5a400000 {
0285 compatible = "socionext,uniphier-sd-v2.91";
0286 status = "disabled";
0287 reg = <0x5a400000 0x200>;
0288 interrupts = <0 76 4>;
0289 pinctrl-names = "default", "uhs";
0290 pinctrl-0 = <&pinctrl_sd>;
0291 pinctrl-1 = <&pinctrl_sd_uhs>;
0292 clocks = <&mio_clk 0>;
0293 reset-names = "host", "bridge";
0294 resets = <&mio_rst 0>, <&mio_rst 3>;
0295 dma-names = "rx-tx";
0296 dmas = <&dmac 4>;
0297 bus-width = <4>;
0298 cap-sd-highspeed;
0299 sd-uhs-sdr12;
0300 sd-uhs-sdr25;
0301 sd-uhs-sdr50;
0302 };
0303
0304 emmc: mmc@5a500000 {
0305 compatible = "socionext,uniphier-sd-v2.91";
0306 status = "disabled";
0307 reg = <0x5a500000 0x200>;
0308 interrupts = <0 78 4>;
0309 pinctrl-names = "default";
0310 pinctrl-0 = <&pinctrl_emmc>;
0311 clocks = <&mio_clk 1>;
0312 reset-names = "host", "bridge", "hw";
0313 resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
0314 dma-names = "rx-tx";
0315 dmas = <&dmac 5>;
0316 bus-width = <8>;
0317 cap-mmc-highspeed;
0318 cap-mmc-hw-reset;
0319 non-removable;
0320 };
0321
0322 sd1: mmc@5a600000 {
0323 compatible = "socionext,uniphier-sd-v2.91";
0324 status = "disabled";
0325 reg = <0x5a600000 0x200>;
0326 interrupts = <0 85 4>;
0327 pinctrl-names = "default";
0328 pinctrl-0 = <&pinctrl_sd1>;
0329 clocks = <&mio_clk 2>;
0330 reset-names = "host", "bridge";
0331 resets = <&mio_rst 2>, <&mio_rst 5>;
0332 dma-names = "rx-tx";
0333 dmas = <&dmac 6>;
0334 bus-width = <4>;
0335 cap-sd-highspeed;
0336 };
0337
0338 usb2: usb@5a800100 {
0339 compatible = "socionext,uniphier-ehci", "generic-ehci";
0340 status = "disabled";
0341 reg = <0x5a800100 0x100>;
0342 interrupts = <0 80 4>;
0343 pinctrl-names = "default";
0344 pinctrl-0 = <&pinctrl_usb2>;
0345 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
0346 <&mio_clk 12>;
0347 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
0348 <&mio_rst 12>;
0349 phy-names = "usb";
0350 phys = <&usb_phy0>;
0351 has-transaction-translator;
0352 };
0353
0354 usb3: usb@5a810100 {
0355 compatible = "socionext,uniphier-ehci", "generic-ehci";
0356 status = "disabled";
0357 reg = <0x5a810100 0x100>;
0358 interrupts = <0 81 4>;
0359 pinctrl-names = "default";
0360 pinctrl-0 = <&pinctrl_usb3>;
0361 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
0362 <&mio_clk 13>;
0363 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
0364 <&mio_rst 13>;
0365 phy-names = "usb";
0366 phys = <&usb_phy1>;
0367 has-transaction-translator;
0368 };
0369
0370 soc_glue: soc-glue@5f800000 {
0371 compatible = "socionext,uniphier-pro4-soc-glue",
0372 "simple-mfd", "syscon";
0373 reg = <0x5f800000 0x2000>;
0374
0375 pinctrl: pinctrl {
0376 compatible = "socionext,uniphier-pro4-pinctrl";
0377 };
0378
0379 usb-phy {
0380 compatible = "socionext,uniphier-pro4-usb2-phy";
0381 #address-cells = <1>;
0382 #size-cells = <0>;
0383
0384 usb_phy0: phy@0 {
0385 reg = <0>;
0386 #phy-cells = <0>;
0387 };
0388
0389 usb_phy1: phy@1 {
0390 reg = <1>;
0391 #phy-cells = <0>;
0392 };
0393
0394 usb_phy2: phy@2 {
0395 reg = <2>;
0396 #phy-cells = <0>;
0397 vbus-supply = <&usb0_vbus>;
0398 };
0399
0400 usb_phy3: phy@3 {
0401 reg = <3>;
0402 #phy-cells = <0>;
0403 vbus-supply = <&usb1_vbus>;
0404 };
0405 };
0406 };
0407
0408 soc-glue@5f900000 {
0409 compatible = "socionext,uniphier-pro4-soc-glue-debug",
0410 "simple-mfd";
0411 #address-cells = <1>;
0412 #size-cells = <1>;
0413 ranges = <0 0x5f900000 0x2000>;
0414
0415 efuse@100 {
0416 compatible = "socionext,uniphier-efuse";
0417 reg = <0x100 0x28>;
0418 };
0419
0420 efuse@130 {
0421 compatible = "socionext,uniphier-efuse";
0422 reg = <0x130 0x8>;
0423 };
0424
0425 efuse@200 {
0426 compatible = "socionext,uniphier-efuse";
0427 reg = <0x200 0x14>;
0428 };
0429 };
0430
0431 xdmac: dma-controller@5fc10000 {
0432 compatible = "socionext,uniphier-xdmac";
0433 reg = <0x5fc10000 0x5300>;
0434 interrupts = <0 188 4>;
0435 dma-channels = <16>;
0436 #dma-cells = <2>;
0437 };
0438
0439 aidet: interrupt-controller@5fc20000 {
0440 compatible = "socionext,uniphier-pro4-aidet";
0441 reg = <0x5fc20000 0x200>;
0442 interrupt-controller;
0443 #interrupt-cells = <2>;
0444 };
0445
0446 timer@60000200 {
0447 compatible = "arm,cortex-a9-global-timer";
0448 reg = <0x60000200 0x20>;
0449 interrupts = <1 11 0x304>;
0450 clocks = <&arm_timer_clk>;
0451 };
0452
0453 timer@60000600 {
0454 compatible = "arm,cortex-a9-twd-timer";
0455 reg = <0x60000600 0x20>;
0456 interrupts = <1 13 0x304>;
0457 clocks = <&arm_timer_clk>;
0458 };
0459
0460 intc: interrupt-controller@60001000 {
0461 compatible = "arm,cortex-a9-gic";
0462 reg = <0x60001000 0x1000>,
0463 <0x60000100 0x100>;
0464 #interrupt-cells = <3>;
0465 interrupt-controller;
0466 };
0467
0468 sysctrl@61840000 {
0469 compatible = "socionext,uniphier-pro4-sysctrl",
0470 "simple-mfd", "syscon";
0471 reg = <0x61840000 0x10000>;
0472
0473 sys_clk: clock {
0474 compatible = "socionext,uniphier-pro4-clock";
0475 #clock-cells = <1>;
0476 };
0477
0478 sys_rst: reset {
0479 compatible = "socionext,uniphier-pro4-reset";
0480 #reset-cells = <1>;
0481 };
0482 };
0483
0484 eth: ethernet@65000000 {
0485 compatible = "socionext,uniphier-pro4-ave4";
0486 status = "disabled";
0487 reg = <0x65000000 0x8500>;
0488 interrupts = <0 66 4>;
0489 pinctrl-names = "default";
0490 pinctrl-0 = <&pinctrl_ether_rgmii>;
0491 clock-names = "gio", "ether", "ether-gb", "ether-phy";
0492 clocks = <&sys_clk 12>, <&sys_clk 6>, <&sys_clk 7>,
0493 <&sys_clk 10>;
0494 reset-names = "gio", "ether";
0495 resets = <&sys_rst 12>, <&sys_rst 6>;
0496 phy-mode = "rgmii";
0497 local-mac-address = [00 00 00 00 00 00];
0498 socionext,syscon-phy-mode = <&soc_glue 0>;
0499
0500 mdio: mdio {
0501 #address-cells = <1>;
0502 #size-cells = <0>;
0503 };
0504 };
0505
0506 usb0: usb@65a00000 {
0507 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
0508 status = "disabled";
0509 reg = <0x65a00000 0xcd00>;
0510 interrupt-names = "host", "peripheral";
0511 interrupts = <0 134 4>, <0 135 4>;
0512 pinctrl-names = "default";
0513 pinctrl-0 = <&pinctrl_usb0>;
0514 clock-names = "ref", "bus_early", "suspend";
0515 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
0516 resets = <&usb0_rst 4>;
0517 phys = <&usb_phy2>, <&usb0_ssphy>;
0518 dr_mode = "host";
0519 };
0520
0521 usb-glue@65b00000 {
0522 compatible = "socionext,uniphier-pro4-dwc3-glue",
0523 "simple-mfd";
0524 #address-cells = <1>;
0525 #size-cells = <1>;
0526 ranges = <0 0x65b00000 0x100>;
0527
0528 usb0_vbus: regulator@0 {
0529 compatible = "socionext,uniphier-pro4-usb3-regulator";
0530 reg = <0 0x10>;
0531 clock-names = "gio", "link";
0532 clocks = <&sys_clk 12>, <&sys_clk 14>;
0533 reset-names = "gio", "link";
0534 resets = <&sys_rst 12>, <&sys_rst 14>;
0535 };
0536
0537 usb0_ssphy: ss-phy@10 {
0538 compatible = "socionext,uniphier-pro4-usb3-ssphy";
0539 reg = <0x10 0x10>;
0540 #phy-cells = <0>;
0541 clock-names = "gio", "link";
0542 clocks = <&sys_clk 12>, <&sys_clk 14>;
0543 reset-names = "gio", "link";
0544 resets = <&sys_rst 12>, <&sys_rst 14>;
0545 vbus-supply = <&usb0_vbus>;
0546 };
0547
0548 usb0_rst: reset@40 {
0549 compatible = "socionext,uniphier-pro4-usb3-reset";
0550 reg = <0x40 0x4>;
0551 #reset-cells = <1>;
0552 clock-names = "gio", "link";
0553 clocks = <&sys_clk 12>, <&sys_clk 14>;
0554 reset-names = "gio", "link";
0555 resets = <&sys_rst 12>, <&sys_rst 14>;
0556 };
0557 };
0558
0559 usb1: usb@65c00000 {
0560 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
0561 status = "disabled";
0562 reg = <0x65c00000 0xcd00>;
0563 interrupt-names = "host", "peripheral";
0564 interrupts = <0 137 4>, <0 138 4>;
0565 pinctrl-names = "default";
0566 pinctrl-0 = <&pinctrl_usb1>;
0567 clock-names = "ref", "bus_early", "suspend";
0568 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
0569 resets = <&usb1_rst 4>;
0570 phys = <&usb_phy3>;
0571 dr_mode = "host";
0572 };
0573
0574 usb-glue@65d00000 {
0575 compatible = "socionext,uniphier-pro4-dwc3-glue",
0576 "simple-mfd";
0577 #address-cells = <1>;
0578 #size-cells = <1>;
0579 ranges = <0 0x65d00000 0x100>;
0580
0581 usb1_vbus: regulator@0 {
0582 compatible = "socionext,uniphier-pro4-usb3-regulator";
0583 reg = <0 0x10>;
0584 clock-names = "gio", "link";
0585 clocks = <&sys_clk 12>, <&sys_clk 15>;
0586 reset-names = "gio", "link";
0587 resets = <&sys_rst 12>, <&sys_rst 15>;
0588 };
0589
0590 usb1_rst: reset@40 {
0591 compatible = "socionext,uniphier-pro4-usb3-reset";
0592 reg = <0x40 0x4>;
0593 #reset-cells = <1>;
0594 clock-names = "gio", "link";
0595 clocks = <&sys_clk 12>, <&sys_clk 15>;
0596 reset-names = "gio", "link";
0597 resets = <&sys_rst 12>, <&sys_rst 15>;
0598 };
0599 };
0600
0601 nand: nand-controller@68000000 {
0602 compatible = "socionext,uniphier-denali-nand-v5a";
0603 status = "disabled";
0604 reg-names = "nand_data", "denali_reg";
0605 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
0606 #address-cells = <1>;
0607 #size-cells = <0>;
0608 interrupts = <0 65 4>;
0609 pinctrl-names = "default";
0610 pinctrl-0 = <&pinctrl_nand>;
0611 clock-names = "nand", "nand_x", "ecc";
0612 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
0613 reset-names = "nand", "reg";
0614 resets = <&sys_rst 2>, <&sys_rst 2>;
0615 };
0616 };
0617 };
0618
0619 #include "uniphier-pinctrl.dtsi"
