0001 // SPDX-License-Identifier: GPL-2.0+ OR MIT
0002 //
0003 // Device Tree Source for UniPhier LD4 SoC
0004 //
0005 // Copyright (C) 2015-2016 Socionext Inc.
0006 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
0007
0008 #include <dt-bindings/gpio/uniphier-gpio.h>
0009
0010 / {
0011 compatible = "socionext,uniphier-ld4";
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014
0015 cpus {
0016 #address-cells = <1>;
0017 #size-cells = <0>;
0018
0019 cpu@0 {
0020 device_type = "cpu";
0021 compatible = "arm,cortex-a9";
0022 reg = <0>;
0023 enable-method = "psci";
0024 next-level-cache = <&l2>;
0025 };
0026 };
0027
0028 psci {
0029 compatible = "arm,psci-0.2";
0030 method = "smc";
0031 };
0032
0033 clocks {
0034 refclk: ref {
0035 compatible = "fixed-clock";
0036 #clock-cells = <0>;
0037 clock-frequency = <24576000>;
0038 };
0039
0040 arm_timer_clk: arm-timer {
0041 #clock-cells = <0>;
0042 compatible = "fixed-clock";
0043 clock-frequency = <50000000>;
0044 };
0045 };
0046
0047 soc {
0048 compatible = "simple-bus";
0049 #address-cells = <1>;
0050 #size-cells = <1>;
0051 ranges;
0052 interrupt-parent = <&intc>;
0053
0054 l2: cache-controller@500c0000 {
0055 compatible = "socionext,uniphier-system-cache";
0056 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
0057 <0x506c0000 0x400>;
0058 interrupts = <0 174 4>, <0 175 4>;
0059 cache-unified;
0060 cache-size = <(512 * 1024)>;
0061 cache-sets = <256>;
0062 cache-line-size = <128>;
0063 cache-level = <2>;
0064 };
0065
0066 spi: spi@54006000 {
0067 compatible = "socionext,uniphier-scssi";
0068 status = "disabled";
0069 reg = <0x54006000 0x100>;
0070 #address-cells = <1>;
0071 #size-cells = <0>;
0072 interrupts = <0 39 4>;
0073 pinctrl-names = "default";
0074 pinctrl-0 = <&pinctrl_spi0>;
0075 clocks = <&peri_clk 11>;
0076 resets = <&peri_rst 11>;
0077 };
0078
0079 serial0: serial@54006800 {
0080 compatible = "socionext,uniphier-uart";
0081 status = "disabled";
0082 reg = <0x54006800 0x40>;
0083 interrupts = <0 33 4>;
0084 pinctrl-names = "default";
0085 pinctrl-0 = <&pinctrl_uart0>;
0086 clocks = <&peri_clk 0>;
0087 resets = <&peri_rst 0>;
0088 };
0089
0090 serial1: serial@54006900 {
0091 compatible = "socionext,uniphier-uart";
0092 status = "disabled";
0093 reg = <0x54006900 0x40>;
0094 interrupts = <0 35 4>;
0095 pinctrl-names = "default";
0096 pinctrl-0 = <&pinctrl_uart1>;
0097 clocks = <&peri_clk 1>;
0098 resets = <&peri_rst 1>;
0099 };
0100
0101 serial2: serial@54006a00 {
0102 compatible = "socionext,uniphier-uart";
0103 status = "disabled";
0104 reg = <0x54006a00 0x40>;
0105 interrupts = <0 37 4>;
0106 pinctrl-names = "default";
0107 pinctrl-0 = <&pinctrl_uart2>;
0108 clocks = <&peri_clk 2>;
0109 resets = <&peri_rst 2>;
0110 };
0111
0112 serial3: serial@54006b00 {
0113 compatible = "socionext,uniphier-uart";
0114 status = "disabled";
0115 reg = <0x54006b00 0x40>;
0116 interrupts = <0 29 4>;
0117 pinctrl-names = "default";
0118 pinctrl-0 = <&pinctrl_uart3>;
0119 clocks = <&peri_clk 3>;
0120 resets = <&peri_rst 3>;
0121 };
0122
0123 gpio: gpio@55000000 {
0124 compatible = "socionext,uniphier-gpio";
0125 reg = <0x55000000 0x200>;
0126 interrupt-parent = <&aidet>;
0127 interrupt-controller;
0128 #interrupt-cells = <2>;
0129 gpio-controller;
0130 #gpio-cells = <2>;
0131 gpio-ranges = <&pinctrl 0 0 0>;
0132 gpio-ranges-group-names = "gpio_range";
0133 ngpios = <136>;
0134 socionext,interrupt-ranges = <0 48 13>, <14 62 2>;
0135 };
0136
0137 i2c0: i2c@58400000 {
0138 compatible = "socionext,uniphier-i2c";
0139 status = "disabled";
0140 reg = <0x58400000 0x40>;
0141 #address-cells = <1>;
0142 #size-cells = <0>;
0143 interrupts = <0 41 1>;
0144 pinctrl-names = "default";
0145 pinctrl-0 = <&pinctrl_i2c0>;
0146 clocks = <&peri_clk 4>;
0147 resets = <&peri_rst 4>;
0148 clock-frequency = <100000>;
0149 };
0150
0151 i2c1: i2c@58480000 {
0152 compatible = "socionext,uniphier-i2c";
0153 status = "disabled";
0154 reg = <0x58480000 0x40>;
0155 #address-cells = <1>;
0156 #size-cells = <0>;
0157 interrupts = <0 42 1>;
0158 pinctrl-names = "default";
0159 pinctrl-0 = <&pinctrl_i2c1>;
0160 clocks = <&peri_clk 5>;
0161 resets = <&peri_rst 5>;
0162 clock-frequency = <100000>;
0163 };
0164
0165 /* chip-internal connection for DMD */
0166 i2c2: i2c@58500000 {
0167 compatible = "socionext,uniphier-i2c";
0168 reg = <0x58500000 0x40>;
0169 #address-cells = <1>;
0170 #size-cells = <0>;
0171 interrupts = <0 43 1>;
0172 pinctrl-names = "default";
0173 pinctrl-0 = <&pinctrl_i2c2>;
0174 clocks = <&peri_clk 6>;
0175 resets = <&peri_rst 6>;
0176 clock-frequency = <400000>;
0177 };
0178
0179 i2c3: i2c@58580000 {
0180 compatible = "socionext,uniphier-i2c";
0181 status = "disabled";
0182 reg = <0x58580000 0x40>;
0183 #address-cells = <1>;
0184 #size-cells = <0>;
0185 interrupts = <0 44 1>;
0186 pinctrl-names = "default";
0187 pinctrl-0 = <&pinctrl_i2c3>;
0188 clocks = <&peri_clk 7>;
0189 resets = <&peri_rst 7>;
0190 clock-frequency = <100000>;
0191 };
0192
0193 system_bus: system-bus@58c00000 {
0194 compatible = "socionext,uniphier-system-bus";
0195 status = "disabled";
0196 reg = <0x58c00000 0x400>;
0197 #address-cells = <2>;
0198 #size-cells = <1>;
0199 pinctrl-names = "default";
0200 pinctrl-0 = <&pinctrl_system_bus>;
0201 };
0202
0203 smpctrl@59801000 {
0204 compatible = "socionext,uniphier-smpctrl";
0205 reg = <0x59801000 0x400>;
0206 };
0207
0208 mioctrl@59810000 {
0209 compatible = "socionext,uniphier-ld4-mioctrl",
0210 "simple-mfd", "syscon";
0211 reg = <0x59810000 0x800>;
0212
0213 mio_clk: clock {
0214 compatible = "socionext,uniphier-ld4-mio-clock";
0215 #clock-cells = <1>;
0216 };
0217
0218 mio_rst: reset {
0219 compatible = "socionext,uniphier-ld4-mio-reset";
0220 #reset-cells = <1>;
0221 };
0222 };
0223
0224 perictrl@59820000 {
0225 compatible = "socionext,uniphier-ld4-perictrl",
0226 "simple-mfd", "syscon";
0227 reg = <0x59820000 0x200>;
0228
0229 peri_clk: clock {
0230 compatible = "socionext,uniphier-ld4-peri-clock";
0231 #clock-cells = <1>;
0232 };
0233
0234 peri_rst: reset {
0235 compatible = "socionext,uniphier-ld4-peri-reset";
0236 #reset-cells = <1>;
0237 };
0238 };
0239
0240 dmac: dma-controller@5a000000 {
0241 compatible = "socionext,uniphier-mio-dmac";
0242 reg = <0x5a000000 0x1000>;
0243 interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
0244 <0 71 4>, <0 72 4>, <0 73 4>;
0245 clocks = <&mio_clk 7>;
0246 resets = <&mio_rst 7>;
0247 #dma-cells = <1>;
0248 };
0249
0250 sd: mmc@5a400000 {
0251 compatible = "socionext,uniphier-sd-v2.91";
0252 status = "disabled";
0253 reg = <0x5a400000 0x200>;
0254 interrupts = <0 76 4>;
0255 pinctrl-names = "default", "uhs";
0256 pinctrl-0 = <&pinctrl_sd>;
0257 pinctrl-1 = <&pinctrl_sd_uhs>;
0258 clocks = <&mio_clk 0>;
0259 reset-names = "host", "bridge";
0260 resets = <&mio_rst 0>, <&mio_rst 3>;
0261 dma-names = "rx-tx";
0262 dmas = <&dmac 4>;
0263 bus-width = <4>;
0264 cap-sd-highspeed;
0265 sd-uhs-sdr12;
0266 sd-uhs-sdr25;
0267 sd-uhs-sdr50;
0268 };
0269
0270 emmc: mmc@5a500000 {
0271 compatible = "socionext,uniphier-sd-v2.91";
0272 status = "disabled";
0273 reg = <0x5a500000 0x200>;
0274 interrupts = <0 78 4>;
0275 pinctrl-names = "default";
0276 pinctrl-0 = <&pinctrl_emmc>;
0277 clocks = <&mio_clk 1>;
0278 reset-names = "host", "bridge", "hw";
0279 resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
0280 dma-names = "rx-tx";
0281 dmas = <&dmac 6>;
0282 bus-width = <8>;
0283 cap-mmc-highspeed;
0284 cap-mmc-hw-reset;
0285 non-removable;
0286 };
0287
0288 usb0: usb@5a800100 {
0289 compatible = "socionext,uniphier-ehci", "generic-ehci";
0290 status = "disabled";
0291 reg = <0x5a800100 0x100>;
0292 interrupts = <0 80 4>;
0293 pinctrl-names = "default";
0294 pinctrl-0 = <&pinctrl_usb0>;
0295 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
0296 <&mio_clk 12>;
0297 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
0298 <&mio_rst 12>;
0299 has-transaction-translator;
0300 };
0301
0302 usb1: usb@5a810100 {
0303 compatible = "socionext,uniphier-ehci", "generic-ehci";
0304 status = "disabled";
0305 reg = <0x5a810100 0x100>;
0306 interrupts = <0 81 4>;
0307 pinctrl-names = "default";
0308 pinctrl-0 = <&pinctrl_usb1>;
0309 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
0310 <&mio_clk 13>;
0311 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
0312 <&mio_rst 13>;
0313 has-transaction-translator;
0314 };
0315
0316 usb2: usb@5a820100 {
0317 compatible = "socionext,uniphier-ehci", "generic-ehci";
0318 status = "disabled";
0319 reg = <0x5a820100 0x100>;
0320 interrupts = <0 82 4>;
0321 pinctrl-names = "default";
0322 pinctrl-0 = <&pinctrl_usb2>;
0323 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
0324 <&mio_clk 14>;
0325 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
0326 <&mio_rst 14>;
0327 has-transaction-translator;
0328 };
0329
0330 soc-glue@5f800000 {
0331 compatible = "socionext,uniphier-ld4-soc-glue",
0332 "simple-mfd", "syscon";
0333 reg = <0x5f800000 0x2000>;
0334
0335 pinctrl: pinctrl {
0336 compatible = "socionext,uniphier-ld4-pinctrl";
0337 };
0338 };
0339
0340 soc-glue@5f900000 {
0341 compatible = "socionext,uniphier-ld4-soc-glue-debug",
0342 "simple-mfd";
0343 #address-cells = <1>;
0344 #size-cells = <1>;
0345 ranges = <0 0x5f900000 0x2000>;
0346
0347 efuse@100 {
0348 compatible = "socionext,uniphier-efuse";
0349 reg = <0x100 0x28>;
0350 };
0351
0352 efuse@130 {
0353 compatible = "socionext,uniphier-efuse";
0354 reg = <0x130 0x8>;
0355 };
0356 };
0357
0358 timer@60000200 {
0359 compatible = "arm,cortex-a9-global-timer";
0360 reg = <0x60000200 0x20>;
0361 interrupts = <1 11 0x104>;
0362 clocks = <&arm_timer_clk>;
0363 };
0364
0365 timer@60000600 {
0366 compatible = "arm,cortex-a9-twd-timer";
0367 reg = <0x60000600 0x20>;
0368 interrupts = <1 13 0x104>;
0369 clocks = <&arm_timer_clk>;
0370 };
0371
0372 intc: interrupt-controller@60001000 {
0373 compatible = "arm,cortex-a9-gic";
0374 reg = <0x60001000 0x1000>,
0375 <0x60000100 0x100>;
0376 #interrupt-cells = <3>;
0377 interrupt-controller;
0378 };
0379
0380 aidet: interrupt-controller@61830000 {
0381 compatible = "socionext,uniphier-ld4-aidet";
0382 reg = <0x61830000 0x200>;
0383 interrupt-controller;
0384 #interrupt-cells = <2>;
0385 };
0386
0387 sysctrl@61840000 {
0388 compatible = "socionext,uniphier-ld4-sysctrl",
0389 "simple-mfd", "syscon";
0390 reg = <0x61840000 0x10000>;
0391
0392 sys_clk: clock {
0393 compatible = "socionext,uniphier-ld4-clock";
0394 #clock-cells = <1>;
0395 };
0396
0397 sys_rst: reset {
0398 compatible = "socionext,uniphier-ld4-reset";
0399 #reset-cells = <1>;
0400 };
0401 };
0402
0403 nand: nand-controller@68000000 {
0404 compatible = "socionext,uniphier-denali-nand-v5a";
0405 status = "disabled";
0406 reg-names = "nand_data", "denali_reg";
0407 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
0408 #address-cells = <1>;
0409 #size-cells = <0>;
0410 interrupts = <0 65 4>;
0411 pinctrl-names = "default";
0412 pinctrl-0 = <&pinctrl_nand>;
0413 clock-names = "nand", "nand_x", "ecc";
0414 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
0415 reset-names = "nand", "reg";
0416 resets = <&sys_rst 2>, <&sys_rst 2>;
0417 };
0418 };
0419 };
0420
0421 #include "uniphier-pinctrl.dtsi"
