0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <dt-bindings/clock/tegra30-car.h>
0003 #include <dt-bindings/gpio/tegra-gpio.h>
0004 #include <dt-bindings/memory/tegra30-mc.h>
0005 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
0006 #include <dt-bindings/interrupt-controller/arm-gic.h>
0007 #include <dt-bindings/soc/tegra-pmc.h>
0008 #include <dt-bindings/thermal/thermal.h>
0009
0010 #include "tegra30-peripherals-opp.dtsi"
0011
0012 / {
0013 compatible = "nvidia,tegra30";
0014 interrupt-parent = <&lic>;
0015 #address-cells = <1>;
0016 #size-cells = <1>;
0017
0018 memory@80000000 {
0019 device_type = "memory";
0020 reg = <0x80000000 0x0>;
0021 };
0022
0023 pcie@3000 {
0024 compatible = "nvidia,tegra30-pcie";
0025 device_type = "pci";
0026 reg = <0x00003000 0x00000800>, /* PADS registers */
0027 <0x00003800 0x00000200>, /* AFI registers */
0028 <0x10000000 0x10000000>; /* configuration space */
0029 reg-names = "pads", "afi", "cs";
0030 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
0031 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
0032 interrupt-names = "intr", "msi";
0033
0034 #interrupt-cells = <1>;
0035 interrupt-map-mask = <0 0 0 0>;
0036 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
0037
0038 bus-range = <0x00 0xff>;
0039 #address-cells = <3>;
0040 #size-cells = <2>;
0041
0042 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
0043 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
0044 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
0045 <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */
0046 <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */
0047 <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
0048
0049 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
0050 <&tegra_car TEGRA30_CLK_AFI>,
0051 <&tegra_car TEGRA30_CLK_PLL_E>,
0052 <&tegra_car TEGRA30_CLK_CML0>;
0053 clock-names = "pex", "afi", "pll_e", "cml";
0054 resets = <&tegra_car 70>,
0055 <&tegra_car 72>,
0056 <&tegra_car 74>;
0057 reset-names = "pex", "afi", "pcie_x";
0058 power-domains = <&pd_core>;
0059 operating-points-v2 = <&pcie_dvfs_opp_table>;
0060 status = "disabled";
0061
0062 pci@1,0 {
0063 device_type = "pci";
0064 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
0065 reg = <0x000800 0 0 0 0>;
0066 bus-range = <0x00 0xff>;
0067 status = "disabled";
0068
0069 #address-cells = <3>;
0070 #size-cells = <2>;
0071 ranges;
0072
0073 nvidia,num-lanes = <2>;
0074 };
0075
0076 pci@2,0 {
0077 device_type = "pci";
0078 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
0079 reg = <0x001000 0 0 0 0>;
0080 bus-range = <0x00 0xff>;
0081 status = "disabled";
0082
0083 #address-cells = <3>;
0084 #size-cells = <2>;
0085 ranges;
0086
0087 nvidia,num-lanes = <2>;
0088 };
0089
0090 pci@3,0 {
0091 device_type = "pci";
0092 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
0093 reg = <0x001800 0 0 0 0>;
0094 bus-range = <0x00 0xff>;
0095 status = "disabled";
0096
0097 #address-cells = <3>;
0098 #size-cells = <2>;
0099 ranges;
0100
0101 nvidia,num-lanes = <2>;
0102 };
0103 };
0104
0105 sram@40000000 {
0106 compatible = "mmio-sram";
0107 reg = <0x40000000 0x40000>;
0108 #address-cells = <1>;
0109 #size-cells = <1>;
0110 ranges = <0 0x40000000 0x40000>;
0111
0112 vde_pool: sram@400 {
0113 reg = <0x400 0x3fc00>;
0114 pool;
0115 };
0116 };
0117
0118 host1x@50000000 {
0119 compatible = "nvidia,tegra30-host1x";
0120 reg = <0x50000000 0x00024000>;
0121 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
0122 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
0123 interrupt-names = "syncpt", "host1x";
0124 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
0125 clock-names = "host1x";
0126 resets = <&tegra_car 28>, <&mc TEGRA30_MC_RESET_HC>;
0127 reset-names = "host1x", "mc";
0128 iommus = <&mc TEGRA_SWGROUP_HC>;
0129 power-domains = <&pd_heg>;
0130 operating-points-v2 = <&host1x_dvfs_opp_table>;
0131
0132 #address-cells = <1>;
0133 #size-cells = <1>;
0134
0135 ranges = <0x54000000 0x54000000 0x04000000>;
0136
0137 mpe@54040000 {
0138 compatible = "nvidia,tegra30-mpe";
0139 reg = <0x54040000 0x00040000>;
0140 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
0141 clocks = <&tegra_car TEGRA30_CLK_MPE>;
0142 resets = <&tegra_car 60>;
0143 reset-names = "mpe";
0144 power-domains = <&pd_mpe>;
0145 operating-points-v2 = <&mpe_dvfs_opp_table>;
0146
0147 iommus = <&mc TEGRA_SWGROUP_MPE>;
0148
0149 status = "disabled";
0150 };
0151
0152 vi@54080000 {
0153 compatible = "nvidia,tegra30-vi";
0154 reg = <0x54080000 0x00040000>;
0155 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0156 clocks = <&tegra_car TEGRA30_CLK_VI>;
0157 resets = <&tegra_car 20>;
0158 reset-names = "vi";
0159 power-domains = <&pd_venc>;
0160 operating-points-v2 = <&vi_dvfs_opp_table>;
0161
0162 iommus = <&mc TEGRA_SWGROUP_VI>;
0163
0164 status = "disabled";
0165 };
0166
0167 epp@540c0000 {
0168 compatible = "nvidia,tegra30-epp";
0169 reg = <0x540c0000 0x00040000>;
0170 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
0171 clocks = <&tegra_car TEGRA30_CLK_EPP>;
0172 resets = <&tegra_car 19>;
0173 reset-names = "epp";
0174 power-domains = <&pd_heg>;
0175 operating-points-v2 = <&epp_dvfs_opp_table>;
0176
0177 iommus = <&mc TEGRA_SWGROUP_EPP>;
0178
0179 status = "disabled";
0180 };
0181
0182 isp@54100000 {
0183 compatible = "nvidia,tegra30-isp";
0184 reg = <0x54100000 0x00040000>;
0185 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0186 clocks = <&tegra_car TEGRA30_CLK_ISP>;
0187 resets = <&tegra_car 23>;
0188 reset-names = "isp";
0189 power-domains = <&pd_venc>;
0190
0191 iommus = <&mc TEGRA_SWGROUP_ISP>;
0192
0193 status = "disabled";
0194 };
0195
0196 gr2d@54140000 {
0197 compatible = "nvidia,tegra30-gr2d";
0198 reg = <0x54140000 0x00040000>;
0199 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0200 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
0201 resets = <&tegra_car 21>, <&mc TEGRA30_MC_RESET_2D>;
0202 reset-names = "2d", "mc";
0203 power-domains = <&pd_heg>;
0204 operating-points-v2 = <&gr2d_dvfs_opp_table>;
0205
0206 iommus = <&mc TEGRA_SWGROUP_G2>;
0207 };
0208
0209 gr3d@54180000 {
0210 compatible = "nvidia,tegra30-gr3d";
0211 reg = <0x54180000 0x00040000>;
0212 clocks = <&tegra_car TEGRA30_CLK_GR3D>,
0213 <&tegra_car TEGRA30_CLK_GR3D2>;
0214 clock-names = "3d", "3d2";
0215 resets = <&tegra_car 24>,
0216 <&tegra_car 98>,
0217 <&mc TEGRA30_MC_RESET_3D>,
0218 <&mc TEGRA30_MC_RESET_3D2>;
0219 reset-names = "3d", "3d2", "mc", "mc2";
0220 power-domains = <&pd_3d0>, <&pd_3d1>;
0221 power-domain-names = "3d0", "3d1";
0222 operating-points-v2 = <&gr3d_dvfs_opp_table>;
0223
0224 iommus = <&mc TEGRA_SWGROUP_NV>,
0225 <&mc TEGRA_SWGROUP_NV2>;
0226 };
0227
0228 dc@54200000 {
0229 compatible = "nvidia,tegra30-dc";
0230 reg = <0x54200000 0x00040000>;
0231 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0232 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
0233 <&tegra_car TEGRA30_CLK_PLL_P>;
0234 clock-names = "dc", "parent";
0235 resets = <&tegra_car 27>;
0236 reset-names = "dc";
0237 power-domains = <&pd_core>;
0238 operating-points-v2 = <&disp1_dvfs_opp_table>;
0239
0240 iommus = <&mc TEGRA_SWGROUP_DC>;
0241
0242 nvidia,head = <0>;
0243
0244 interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>,
0245 <&mc TEGRA30_MC_DISPLAY0B &emc>,
0246 <&mc TEGRA30_MC_DISPLAY1B &emc>,
0247 <&mc TEGRA30_MC_DISPLAY0C &emc>,
0248 <&mc TEGRA30_MC_DISPLAYHC &emc>;
0249 interconnect-names = "wina",
0250 "winb",
0251 "winb-vfilter",
0252 "winc",
0253 "cursor";
0254
0255 rgb {
0256 status = "disabled";
0257 };
0258 };
0259
0260 dc@54240000 {
0261 compatible = "nvidia,tegra30-dc";
0262 reg = <0x54240000 0x00040000>;
0263 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0264 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
0265 <&tegra_car TEGRA30_CLK_PLL_P>;
0266 clock-names = "dc", "parent";
0267 resets = <&tegra_car 26>;
0268 reset-names = "dc";
0269 power-domains = <&pd_core>;
0270 operating-points-v2 = <&disp2_dvfs_opp_table>;
0271
0272 iommus = <&mc TEGRA_SWGROUP_DCB>;
0273
0274 nvidia,head = <1>;
0275
0276 interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>,
0277 <&mc TEGRA30_MC_DISPLAY0BB &emc>,
0278 <&mc TEGRA30_MC_DISPLAY1BB &emc>,
0279 <&mc TEGRA30_MC_DISPLAY0CB &emc>,
0280 <&mc TEGRA30_MC_DISPLAYHCB &emc>;
0281 interconnect-names = "wina",
0282 "winb",
0283 "winb-vfilter",
0284 "winc",
0285 "cursor";
0286
0287 rgb {
0288 status = "disabled";
0289 };
0290 };
0291
0292 hdmi@54280000 {
0293 compatible = "nvidia,tegra30-hdmi";
0294 reg = <0x54280000 0x00040000>;
0295 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0296 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
0297 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
0298 clock-names = "hdmi", "parent";
0299 resets = <&tegra_car 51>;
0300 reset-names = "hdmi";
0301 power-domains = <&pd_core>;
0302 operating-points-v2 = <&hdmi_dvfs_opp_table>;
0303 status = "disabled";
0304 };
0305
0306 tvo@542c0000 {
0307 compatible = "nvidia,tegra30-tvo";
0308 reg = <0x542c0000 0x00040000>;
0309 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0310 clocks = <&tegra_car TEGRA30_CLK_TVO>;
0311 power-domains = <&pd_core>;
0312 operating-points-v2 = <&tvo_dvfs_opp_table>;
0313 status = "disabled";
0314 };
0315
0316 dsi@54300000 {
0317 compatible = "nvidia,tegra30-dsi";
0318 reg = <0x54300000 0x00040000>;
0319 clocks = <&tegra_car TEGRA30_CLK_DSIA>,
0320 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
0321 clock-names = "dsi", "parent";
0322 resets = <&tegra_car 48>;
0323 reset-names = "dsi";
0324 power-domains = <&pd_core>;
0325 operating-points-v2 = <&dsia_dvfs_opp_table>;
0326 status = "disabled";
0327 };
0328
0329 dsi@54400000 {
0330 compatible = "nvidia,tegra30-dsi";
0331 reg = <0x54400000 0x00040000>;
0332 clocks = <&tegra_car TEGRA30_CLK_DSIB>,
0333 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
0334 clock-names = "dsi", "parent";
0335 resets = <&tegra_car 84>;
0336 reset-names = "dsi";
0337 power-domains = <&pd_core>;
0338 operating-points-v2 = <&dsib_dvfs_opp_table>;
0339 status = "disabled";
0340 };
0341 };
0342
0343 timer@50040600 {
0344 compatible = "arm,cortex-a9-twd-timer";
0345 reg = <0x50040600 0x20>;
0346 interrupt-parent = <&intc>;
0347 interrupts = <GIC_PPI 13
0348 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
0349 clocks = <&tegra_car TEGRA30_CLK_TWD>;
0350 };
0351
0352 intc: interrupt-controller@50041000 {
0353 compatible = "arm,cortex-a9-gic";
0354 reg = <0x50041000 0x1000>,
0355 <0x50040100 0x0100>;
0356 interrupt-controller;
0357 #interrupt-cells = <3>;
0358 interrupt-parent = <&intc>;
0359 };
0360
0361 cache-controller@50043000 {
0362 compatible = "arm,pl310-cache";
0363 reg = <0x50043000 0x1000>;
0364 arm,data-latency = <6 6 2>;
0365 arm,tag-latency = <5 5 2>;
0366 cache-unified;
0367 cache-level = <2>;
0368 };
0369
0370 lic: interrupt-controller@60004000 {
0371 compatible = "nvidia,tegra30-ictlr";
0372 reg = <0x60004000 0x100>,
0373 <0x60004100 0x50>,
0374 <0x60004200 0x50>,
0375 <0x60004300 0x50>,
0376 <0x60004400 0x50>;
0377 interrupt-controller;
0378 #interrupt-cells = <3>;
0379 interrupt-parent = <&intc>;
0380 };
0381
0382 timer@60005000 {
0383 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
0384 reg = <0x60005000 0x400>;
0385 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0386 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0387 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
0388 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
0389 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
0390 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
0391 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
0392 };
0393
0394 tegra_car: clock@60006000 {
0395 compatible = "nvidia,tegra30-car";
0396 reg = <0x60006000 0x1000>;
0397 #clock-cells = <1>;
0398 #reset-cells = <1>;
0399
0400 sclk {
0401 compatible = "nvidia,tegra30-sclk";
0402 clocks = <&tegra_car TEGRA30_CLK_SCLK>;
0403 power-domains = <&pd_core>;
0404 operating-points-v2 = <&sclk_dvfs_opp_table>;
0405 };
0406
0407 pll-c {
0408 compatible = "nvidia,tegra30-pllc";
0409 clocks = <&tegra_car TEGRA30_CLK_PLL_C>;
0410 power-domains = <&pd_core>;
0411 operating-points-v2 = <&pll_c_dvfs_opp_table>;
0412 };
0413
0414 pll-e {
0415 compatible = "nvidia,tegra30-plle";
0416 clocks = <&tegra_car TEGRA30_CLK_PLL_E>;
0417 power-domains = <&pd_core>;
0418 operating-points-v2 = <&pll_e_dvfs_opp_table>;
0419 };
0420
0421 pll-m {
0422 compatible = "nvidia,tegra30-pllm";
0423 clocks = <&tegra_car TEGRA30_CLK_PLL_M>;
0424 power-domains = <&pd_core>;
0425 operating-points-v2 = <&pll_m_dvfs_opp_table>;
0426 };
0427 };
0428
0429 flow-controller@60007000 {
0430 compatible = "nvidia,tegra30-flowctrl";
0431 reg = <0x60007000 0x1000>;
0432 };
0433
0434 apbdma: dma@6000a000 {
0435 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
0436 reg = <0x6000a000 0x1400>;
0437 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0438 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
0439 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
0440 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
0441 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
0442 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
0443 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
0444 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
0445 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
0446 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
0447 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
0448 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
0449 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
0450 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
0451 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
0452 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
0453 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
0454 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
0455 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
0456 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
0457 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
0458 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
0459 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
0460 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
0461 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
0462 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
0463 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
0464 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
0465 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
0466 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
0467 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
0468 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0469 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
0470 resets = <&tegra_car 34>;
0471 reset-names = "dma";
0472 #dma-cells = <1>;
0473 };
0474
0475 ahb: ahb@6000c000 {
0476 compatible = "nvidia,tegra30-ahb";
0477 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
0478 };
0479
0480 actmon: actmon@6000c800 {
0481 compatible = "nvidia,tegra30-actmon";
0482 reg = <0x6000c800 0x400>;
0483 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0484 clocks = <&tegra_car TEGRA30_CLK_ACTMON>,
0485 <&tegra_car TEGRA30_CLK_EMC>;
0486 clock-names = "actmon", "emc";
0487 resets = <&tegra_car TEGRA30_CLK_ACTMON>;
0488 reset-names = "actmon";
0489 operating-points-v2 = <&emc_bw_dfs_opp_table>;
0490 interconnects = <&mc TEGRA30_MC_MPCORER &emc>;
0491 interconnect-names = "cpu-read";
0492 #cooling-cells = <2>;
0493 };
0494
0495 gpio: gpio@6000d000 {
0496 compatible = "nvidia,tegra30-gpio";
0497 reg = <0x6000d000 0x1000>;
0498 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
0499 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
0500 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
0501 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
0502 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
0503 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0504 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
0505 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
0506 #gpio-cells = <2>;
0507 gpio-controller;
0508 #interrupt-cells = <2>;
0509 interrupt-controller;
0510 gpio-ranges = <&pinmux 0 0 248>;
0511 };
0512
0513 vde@6001a000 {
0514 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
0515 reg = <0x6001a000 0x1000>, /* Syntax Engine */
0516 <0x6001b000 0x1000>, /* Video Bitstream Engine */
0517 <0x6001c000 0x100>, /* Macroblock Engine */
0518 <0x6001c200 0x100>, /* Post-processing Engine */
0519 <0x6001c400 0x100>, /* Motion Compensation Engine */
0520 <0x6001c600 0x100>, /* Transform Engine */
0521 <0x6001c800 0x100>, /* Pixel prediction block */
0522 <0x6001ca00 0x100>, /* Video DMA */
0523 <0x6001d800 0x400>; /* Video frame controls */
0524 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
0525 "tfe", "ppb", "vdma", "frameid";
0526 iram = <&vde_pool>; /* IRAM region */
0527 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
0528 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
0529 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
0530 interrupt-names = "sync-token", "bsev", "sxe";
0531 clocks = <&tegra_car TEGRA30_CLK_VDE>;
0532 reset-names = "vde", "mc";
0533 resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>;
0534 iommus = <&mc TEGRA_SWGROUP_VDE>;
0535 power-domains = <&pd_vde>;
0536 operating-points-v2 = <&vde_dvfs_opp_table>;
0537 };
0538
0539 apbmisc@70000800 {
0540 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
0541 reg = <0x70000800 0x64>, /* Chip revision */
0542 <0x70000008 0x04>; /* Strapping options */
0543 };
0544
0545 pinmux: pinmux@70000868 {
0546 compatible = "nvidia,tegra30-pinmux";
0547 reg = <0x70000868 0x0d4>, /* Pad control registers */
0548 <0x70003000 0x3e4>; /* Mux registers */
0549 };
0550
0551 /*
0552 * There are two serial driver i.e. 8250 based simple serial
0553 * driver and APB DMA based serial driver for higher baudrate
0554 * and performace. To enable the 8250 based driver, the compatible
0555 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
0556 * the APB DMA based serial driver, the compatible is
0557 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
0558 */
0559 uarta: serial@70006000 {
0560 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
0561 reg = <0x70006000 0x40>;
0562 reg-shift = <2>;
0563 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0564 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
0565 resets = <&tegra_car 6>;
0566 reset-names = "serial";
0567 dmas = <&apbdma 8>, <&apbdma 8>;
0568 dma-names = "rx", "tx";
0569 status = "disabled";
0570 };
0571
0572 uartb: serial@70006040 {
0573 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
0574 reg = <0x70006040 0x40>;
0575 reg-shift = <2>;
0576 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0577 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
0578 resets = <&tegra_car 7>;
0579 reset-names = "serial";
0580 dmas = <&apbdma 9>, <&apbdma 9>;
0581 dma-names = "rx", "tx";
0582 status = "disabled";
0583 };
0584
0585 uartc: serial@70006200 {
0586 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
0587 reg = <0x70006200 0x100>;
0588 reg-shift = <2>;
0589 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0590 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
0591 resets = <&tegra_car 55>;
0592 reset-names = "serial";
0593 dmas = <&apbdma 10>, <&apbdma 10>;
0594 dma-names = "rx", "tx";
0595 status = "disabled";
0596 };
0597
0598 uartd: serial@70006300 {
0599 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
0600 reg = <0x70006300 0x100>;
0601 reg-shift = <2>;
0602 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0603 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
0604 resets = <&tegra_car 65>;
0605 reset-names = "serial";
0606 dmas = <&apbdma 19>, <&apbdma 19>;
0607 dma-names = "rx", "tx";
0608 status = "disabled";
0609 };
0610
0611 uarte: serial@70006400 {
0612 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
0613 reg = <0x70006400 0x100>;
0614 reg-shift = <2>;
0615 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0616 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
0617 resets = <&tegra_car 66>;
0618 reset-names = "serial";
0619 dmas = <&apbdma 20>, <&apbdma 20>;
0620 dma-names = "rx", "tx";
0621 status = "disabled";
0622 };
0623
0624 gmi@70009000 {
0625 compatible = "nvidia,tegra30-gmi";
0626 reg = <0x70009000 0x1000>;
0627 #address-cells = <2>;
0628 #size-cells = <1>;
0629 ranges = <0 0 0x48000000 0x7ffffff>;
0630 clocks = <&tegra_car TEGRA30_CLK_NOR>;
0631 clock-names = "gmi";
0632 resets = <&tegra_car 42>;
0633 reset-names = "gmi";
0634 power-domains = <&pd_core>;
0635 operating-points-v2 = <&nor_dvfs_opp_table>;
0636 status = "disabled";
0637 };
0638
0639 pwm: pwm@7000a000 {
0640 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
0641 reg = <0x7000a000 0x100>;
0642 #pwm-cells = <2>;
0643 clocks = <&tegra_car TEGRA30_CLK_PWM>;
0644 resets = <&tegra_car 17>;
0645 reset-names = "pwm";
0646 power-domains = <&pd_core>;
0647 operating-points-v2 = <&pwm_dvfs_opp_table>;
0648 status = "disabled";
0649 };
0650
0651 rtc@7000e000 {
0652 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
0653 reg = <0x7000e000 0x100>;
0654 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0655 clocks = <&tegra_car TEGRA30_CLK_RTC>;
0656 };
0657
0658 i2c@7000c000 {
0659 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
0660 reg = <0x7000c000 0x100>;
0661 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0662 #address-cells = <1>;
0663 #size-cells = <0>;
0664 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
0665 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
0666 clock-names = "div-clk", "fast-clk";
0667 resets = <&tegra_car 12>;
0668 reset-names = "i2c";
0669 dmas = <&apbdma 21>, <&apbdma 21>;
0670 dma-names = "rx", "tx";
0671 status = "disabled";
0672 };
0673
0674 i2c@7000c400 {
0675 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
0676 reg = <0x7000c400 0x100>;
0677 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0678 #address-cells = <1>;
0679 #size-cells = <0>;
0680 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
0681 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
0682 clock-names = "div-clk", "fast-clk";
0683 resets = <&tegra_car 54>;
0684 reset-names = "i2c";
0685 dmas = <&apbdma 22>, <&apbdma 22>;
0686 dma-names = "rx", "tx";
0687 status = "disabled";
0688 };
0689
0690 i2c@7000c500 {
0691 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
0692 reg = <0x7000c500 0x100>;
0693 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0694 #address-cells = <1>;
0695 #size-cells = <0>;
0696 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
0697 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
0698 clock-names = "div-clk", "fast-clk";
0699 resets = <&tegra_car 67>;
0700 reset-names = "i2c";
0701 dmas = <&apbdma 23>, <&apbdma 23>;
0702 dma-names = "rx", "tx";
0703 status = "disabled";
0704 };
0705
0706 i2c@7000c700 {
0707 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
0708 reg = <0x7000c700 0x100>;
0709 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
0710 #address-cells = <1>;
0711 #size-cells = <0>;
0712 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
0713 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
0714 resets = <&tegra_car 103>;
0715 reset-names = "i2c";
0716 clock-names = "div-clk", "fast-clk";
0717 dmas = <&apbdma 26>, <&apbdma 26>;
0718 dma-names = "rx", "tx";
0719 status = "disabled";
0720 };
0721
0722 i2c@7000d000 {
0723 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
0724 reg = <0x7000d000 0x100>;
0725 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
0726 #address-cells = <1>;
0727 #size-cells = <0>;
0728 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
0729 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
0730 clock-names = "div-clk", "fast-clk";
0731 resets = <&tegra_car 47>;
0732 reset-names = "i2c";
0733 dmas = <&apbdma 24>, <&apbdma 24>;
0734 dma-names = "rx", "tx";
0735 status = "disabled";
0736 };
0737
0738 spi@7000d400 {
0739 compatible = "nvidia,tegra30-slink";
0740 reg = <0x7000d400 0x200>;
0741 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
0742 #address-cells = <1>;
0743 #size-cells = <0>;
0744 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
0745 resets = <&tegra_car 41>;
0746 reset-names = "spi";
0747 dmas = <&apbdma 15>, <&apbdma 15>;
0748 dma-names = "rx", "tx";
0749 power-domains = <&pd_core>;
0750 operating-points-v2 = <&sbc1_dvfs_opp_table>;
0751 status = "disabled";
0752 };
0753
0754 spi@7000d600 {
0755 compatible = "nvidia,tegra30-slink";
0756 reg = <0x7000d600 0x200>;
0757 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0758 #address-cells = <1>;
0759 #size-cells = <0>;
0760 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
0761 resets = <&tegra_car 44>;
0762 reset-names = "spi";
0763 dmas = <&apbdma 16>, <&apbdma 16>;
0764 dma-names = "rx", "tx";
0765 power-domains = <&pd_core>;
0766 operating-points-v2 = <&sbc2_dvfs_opp_table>;
0767 status = "disabled";
0768 };
0769
0770 spi@7000d800 {
0771 compatible = "nvidia,tegra30-slink";
0772 reg = <0x7000d800 0x200>;
0773 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0774 #address-cells = <1>;
0775 #size-cells = <0>;
0776 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
0777 resets = <&tegra_car 46>;
0778 reset-names = "spi";
0779 dmas = <&apbdma 17>, <&apbdma 17>;
0780 dma-names = "rx", "tx";
0781 power-domains = <&pd_core>;
0782 operating-points-v2 = <&sbc3_dvfs_opp_table>;
0783 status = "disabled";
0784 };
0785
0786 spi@7000da00 {
0787 compatible = "nvidia,tegra30-slink";
0788 reg = <0x7000da00 0x200>;
0789 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
0790 #address-cells = <1>;
0791 #size-cells = <0>;
0792 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
0793 resets = <&tegra_car 68>;
0794 reset-names = "spi";
0795 dmas = <&apbdma 18>, <&apbdma 18>;
0796 dma-names = "rx", "tx";
0797 power-domains = <&pd_core>;
0798 operating-points-v2 = <&sbc4_dvfs_opp_table>;
0799 status = "disabled";
0800 };
0801
0802 spi@7000dc00 {
0803 compatible = "nvidia,tegra30-slink";
0804 reg = <0x7000dc00 0x200>;
0805 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0806 #address-cells = <1>;
0807 #size-cells = <0>;
0808 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
0809 resets = <&tegra_car 104>;
0810 reset-names = "spi";
0811 dmas = <&apbdma 27>, <&apbdma 27>;
0812 dma-names = "rx", "tx";
0813 power-domains = <&pd_core>;
0814 operating-points-v2 = <&sbc5_dvfs_opp_table>;
0815 status = "disabled";
0816 };
0817
0818 spi@7000de00 {
0819 compatible = "nvidia,tegra30-slink";
0820 reg = <0x7000de00 0x200>;
0821 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0822 #address-cells = <1>;
0823 #size-cells = <0>;
0824 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
0825 resets = <&tegra_car 106>;
0826 reset-names = "spi";
0827 dmas = <&apbdma 28>, <&apbdma 28>;
0828 dma-names = "rx", "tx";
0829 power-domains = <&pd_core>;
0830 operating-points-v2 = <&sbc6_dvfs_opp_table>;
0831 status = "disabled";
0832 };
0833
0834 kbc@7000e200 {
0835 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
0836 reg = <0x7000e200 0x100>;
0837 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
0838 clocks = <&tegra_car TEGRA30_CLK_KBC>;
0839 resets = <&tegra_car 36>;
0840 reset-names = "kbc";
0841 status = "disabled";
0842 };
0843
0844 tegra_pmc: pmc@7000e400 {
0845 compatible = "nvidia,tegra30-pmc";
0846 reg = <0x7000e400 0x400>;
0847 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
0848 clock-names = "pclk", "clk32k_in";
0849 #clock-cells = <1>;
0850
0851 pd_core: core-domain {
0852 #power-domain-cells = <0>;
0853 operating-points-v2 = <&core_opp_table>;
0854 };
0855
0856 powergates {
0857 pd_3d0: td {
0858 clocks = <&tegra_car TEGRA30_CLK_GR3D>;
0859 resets = <&mc TEGRA30_MC_RESET_3D>,
0860 <&tegra_car TEGRA30_CLK_GR3D>;
0861 power-domains = <&pd_core>;
0862 #power-domain-cells = <0>;
0863 };
0864
0865 pd_3d1: td2 {
0866 clocks = <&tegra_car TEGRA30_CLK_GR3D2>;
0867 resets = <&mc TEGRA30_MC_RESET_3D2>,
0868 <&tegra_car TEGRA30_CLK_GR3D2>;
0869 power-domains = <&pd_core>;
0870 #power-domain-cells = <0>;
0871 };
0872
0873 pd_venc: venc {
0874 clocks = <&tegra_car TEGRA30_CLK_ISP>,
0875 <&tegra_car TEGRA30_CLK_VI>,
0876 <&tegra_car TEGRA30_CLK_CSI>;
0877 resets = <&mc TEGRA30_MC_RESET_ISP>,
0878 <&mc TEGRA30_MC_RESET_VI>,
0879 <&tegra_car TEGRA30_CLK_ISP>,
0880 <&tegra_car 20 /* VI */>,
0881 <&tegra_car TEGRA30_CLK_CSI>;
0882 power-domains = <&pd_core>;
0883 #power-domain-cells = <0>;
0884 };
0885
0886 pd_vde: vdec {
0887 clocks = <&tegra_car TEGRA30_CLK_VDE>;
0888 resets = <&mc TEGRA30_MC_RESET_VDE>,
0889 <&tegra_car TEGRA30_CLK_VDE>;
0890 power-domains = <&pd_core>;
0891 #power-domain-cells = <0>;
0892 };
0893
0894 pd_mpe: mpe {
0895 clocks = <&tegra_car TEGRA30_CLK_MPE>;
0896 resets = <&mc TEGRA30_MC_RESET_MPE>,
0897 <&tegra_car TEGRA30_CLK_MPE>;
0898 power-domains = <&pd_core>;
0899 #power-domain-cells = <0>;
0900 };
0901
0902 pd_heg: heg {
0903 clocks = <&tegra_car TEGRA30_CLK_GR2D>,
0904 <&tegra_car TEGRA30_CLK_EPP>,
0905 <&tegra_car TEGRA30_CLK_HOST1X>;
0906 resets = <&mc TEGRA30_MC_RESET_2D>,
0907 <&mc TEGRA30_MC_RESET_EPP>,
0908 <&mc TEGRA30_MC_RESET_HC>,
0909 <&tegra_car TEGRA30_CLK_GR2D>,
0910 <&tegra_car TEGRA30_CLK_EPP>,
0911 <&tegra_car TEGRA30_CLK_HOST1X>;
0912 power-domains = <&pd_core>;
0913 #power-domain-cells = <0>;
0914 };
0915 };
0916 };
0917
0918 mc: memory-controller@7000f000 {
0919 compatible = "nvidia,tegra30-mc";
0920 reg = <0x7000f000 0x400>;
0921 clocks = <&tegra_car TEGRA30_CLK_MC>;
0922 clock-names = "mc";
0923
0924 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0925
0926 #iommu-cells = <1>;
0927 #reset-cells = <1>;
0928 #interconnect-cells = <1>;
0929 };
0930
0931 emc: memory-controller@7000f400 {
0932 compatible = "nvidia,tegra30-emc";
0933 reg = <0x7000f400 0x400>;
0934 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
0935 clocks = <&tegra_car TEGRA30_CLK_EMC>;
0936 power-domains = <&pd_core>;
0937
0938 nvidia,memory-controller = <&mc>;
0939 operating-points-v2 = <&emc_icc_dvfs_opp_table>;
0940
0941 #interconnect-cells = <0>;
0942 };
0943
0944 fuse@7000f800 {
0945 compatible = "nvidia,tegra30-efuse";
0946 reg = <0x7000f800 0x400>;
0947 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
0948 clock-names = "fuse";
0949 resets = <&tegra_car 39>;
0950 reset-names = "fuse";
0951 power-domains = <&pd_core>;
0952 operating-points-v2 = <&fuse_burn_dvfs_opp_table>;
0953 };
0954
0955 tsensor: tsensor@70014000 {
0956 compatible = "nvidia,tegra30-tsensor";
0957 reg = <0x70014000 0x500>;
0958 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
0959 clocks = <&tegra_car TEGRA30_CLK_TSENSOR>;
0960 resets = <&tegra_car TEGRA30_CLK_TSENSOR>;
0961
0962 assigned-clocks = <&tegra_car TEGRA30_CLK_TSENSOR>;
0963 assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>;
0964 assigned-clock-rates = <500000>;
0965
0966 #thermal-sensor-cells = <1>;
0967 };
0968
0969 hda@70030000 {
0970 compatible = "nvidia,tegra30-hda";
0971 reg = <0x70030000 0x10000>;
0972 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
0973 clocks = <&tegra_car TEGRA30_CLK_HDA>,
0974 <&tegra_car TEGRA30_CLK_HDA2HDMI>,
0975 <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
0976 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
0977 resets = <&tegra_car 125>, /* hda */
0978 <&tegra_car 128>, /* hda2hdmi */
0979 <&tegra_car 111>; /* hda2codec_2x */
0980 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
0981 status = "disabled";
0982 };
0983
0984 ahub@70080000 {
0985 compatible = "nvidia,tegra30-ahub";
0986 reg = <0x70080000 0x200>,
0987 <0x70080200 0x100>;
0988 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0989 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
0990 <&tegra_car TEGRA30_CLK_APBIF>;
0991 clock-names = "d_audio", "apbif";
0992 resets = <&tegra_car 106>, /* d_audio */
0993 <&tegra_car 107>, /* apbif */
0994 <&tegra_car 30>, /* i2s0 */
0995 <&tegra_car 11>, /* i2s1 */
0996 <&tegra_car 18>, /* i2s2 */
0997 <&tegra_car 101>, /* i2s3 */
0998 <&tegra_car 102>, /* i2s4 */
0999 <&tegra_car 108>, /* dam0 */
1000 <&tegra_car 109>, /* dam1 */
1001 <&tegra_car 110>, /* dam2 */
1002 <&tegra_car 10>; /* spdif */
1003 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
1004 "i2s3", "i2s4", "dam0", "dam1", "dam2",
1005 "spdif";
1006 dmas = <&apbdma 1>, <&apbdma 1>,
1007 <&apbdma 2>, <&apbdma 2>,
1008 <&apbdma 3>, <&apbdma 3>,
1009 <&apbdma 4>, <&apbdma 4>;
1010 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
1011 "rx3", "tx3";
1012 ranges;
1013 #address-cells = <1>;
1014 #size-cells = <1>;
1015
1016 tegra_i2s0: i2s@70080300 {
1017 compatible = "nvidia,tegra30-i2s";
1018 reg = <0x70080300 0x100>;
1019 nvidia,ahub-cif-ids = <4 4>;
1020 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
1021 resets = <&tegra_car 30>;
1022 reset-names = "i2s";
1023 status = "disabled";
1024 };
1025
1026 tegra_i2s1: i2s@70080400 {
1027 compatible = "nvidia,tegra30-i2s";
1028 reg = <0x70080400 0x100>;
1029 nvidia,ahub-cif-ids = <5 5>;
1030 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
1031 resets = <&tegra_car 11>;
1032 reset-names = "i2s";
1033 status = "disabled";
1034 };
1035
1036 tegra_i2s2: i2s@70080500 {
1037 compatible = "nvidia,tegra30-i2s";
1038 reg = <0x70080500 0x100>;
1039 nvidia,ahub-cif-ids = <6 6>;
1040 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
1041 resets = <&tegra_car 18>;
1042 reset-names = "i2s";
1043 status = "disabled";
1044 };
1045
1046 tegra_i2s3: i2s@70080600 {
1047 compatible = "nvidia,tegra30-i2s";
1048 reg = <0x70080600 0x100>;
1049 nvidia,ahub-cif-ids = <7 7>;
1050 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
1051 resets = <&tegra_car 101>;
1052 reset-names = "i2s";
1053 status = "disabled";
1054 };
1055
1056 tegra_i2s4: i2s@70080700 {
1057 compatible = "nvidia,tegra30-i2s";
1058 reg = <0x70080700 0x100>;
1059 nvidia,ahub-cif-ids = <8 8>;
1060 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
1061 resets = <&tegra_car 102>;
1062 reset-names = "i2s";
1063 status = "disabled";
1064 };
1065 };
1066
1067 mmc@78000000 {
1068 compatible = "nvidia,tegra30-sdhci";
1069 reg = <0x78000000 0x200>;
1070 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1071 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
1072 clock-names = "sdhci";
1073 resets = <&tegra_car 14>;
1074 reset-names = "sdhci";
1075 power-domains = <&pd_core>;
1076 operating-points-v2 = <&sdmmc1_dvfs_opp_table>;
1077 status = "disabled";
1078 };
1079
1080 mmc@78000200 {
1081 compatible = "nvidia,tegra30-sdhci";
1082 reg = <0x78000200 0x200>;
1083 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1084 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
1085 clock-names = "sdhci";
1086 resets = <&tegra_car 9>;
1087 reset-names = "sdhci";
1088 status = "disabled";
1089 };
1090
1091 mmc@78000400 {
1092 compatible = "nvidia,tegra30-sdhci";
1093 reg = <0x78000400 0x200>;
1094 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1095 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
1096 clock-names = "sdhci";
1097 resets = <&tegra_car 69>;
1098 reset-names = "sdhci";
1099 power-domains = <&pd_core>;
1100 operating-points-v2 = <&sdmmc3_dvfs_opp_table>;
1101 status = "disabled";
1102 };
1103
1104 mmc@78000600 {
1105 compatible = "nvidia,tegra30-sdhci";
1106 reg = <0x78000600 0x200>;
1107 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1108 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
1109 clock-names = "sdhci";
1110 resets = <&tegra_car 15>;
1111 reset-names = "sdhci";
1112 status = "disabled";
1113 };
1114
1115 usb@7d000000 {
1116 compatible = "nvidia,tegra30-ehci";
1117 reg = <0x7d000000 0x4000>;
1118 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1119 phy_type = "utmi";
1120 clocks = <&tegra_car TEGRA30_CLK_USBD>;
1121 resets = <&tegra_car 22>;
1122 reset-names = "usb";
1123 nvidia,needs-double-reset;
1124 nvidia,phy = <&phy1>;
1125 power-domains = <&pd_core>;
1126 operating-points-v2 = <&usbd_dvfs_opp_table>;
1127 status = "disabled";
1128 };
1129
1130 phy1: usb-phy@7d000000 {
1131 compatible = "nvidia,tegra30-usb-phy";
1132 reg = <0x7d000000 0x4000>,
1133 <0x7d000000 0x4000>;
1134 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1135 phy_type = "utmi";
1136 clocks = <&tegra_car TEGRA30_CLK_USBD>,
1137 <&tegra_car TEGRA30_CLK_PLL_U>,
1138 <&tegra_car TEGRA30_CLK_USBD>;
1139 clock-names = "reg", "pll_u", "utmi-pads";
1140 resets = <&tegra_car 22>, <&tegra_car 22>;
1141 reset-names = "usb", "utmi-pads";
1142 #phy-cells = <0>;
1143 nvidia,hssync-start-delay = <9>;
1144 nvidia,idle-wait-delay = <17>;
1145 nvidia,elastic-limit = <16>;
1146 nvidia,term-range-adj = <6>;
1147 nvidia,xcvr-setup = <51>;
1148 nvidia,xcvr-setup-use-fuses;
1149 nvidia,xcvr-lsfslew = <1>;
1150 nvidia,xcvr-lsrslew = <1>;
1151 nvidia,xcvr-hsslew = <32>;
1152 nvidia,hssquelch-level = <2>;
1153 nvidia,hsdiscon-level = <5>;
1154 nvidia,has-utmi-pad-registers;
1155 nvidia,pmc = <&tegra_pmc 0>;
1156 status = "disabled";
1157 };
1158
1159 usb@7d004000 {
1160 compatible = "nvidia,tegra30-ehci";
1161 reg = <0x7d004000 0x4000>;
1162 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1163 phy_type = "utmi";
1164 clocks = <&tegra_car TEGRA30_CLK_USB2>;
1165 resets = <&tegra_car 58>;
1166 reset-names = "usb";
1167 nvidia,phy = <&phy2>;
1168 power-domains = <&pd_core>;
1169 operating-points-v2 = <&usb2_dvfs_opp_table>;
1170 status = "disabled";
1171 };
1172
1173 phy2: usb-phy@7d004000 {
1174 compatible = "nvidia,tegra30-usb-phy";
1175 reg = <0x7d004000 0x4000>,
1176 <0x7d000000 0x4000>;
1177 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1178 phy_type = "utmi";
1179 clocks = <&tegra_car TEGRA30_CLK_USB2>,
1180 <&tegra_car TEGRA30_CLK_PLL_U>,
1181 <&tegra_car TEGRA30_CLK_USBD>;
1182 clock-names = "reg", "pll_u", "utmi-pads";
1183 resets = <&tegra_car 58>, <&tegra_car 22>;
1184 reset-names = "usb", "utmi-pads";
1185 #phy-cells = <0>;
1186 nvidia,hssync-start-delay = <9>;
1187 nvidia,idle-wait-delay = <17>;
1188 nvidia,elastic-limit = <16>;
1189 nvidia,term-range-adj = <6>;
1190 nvidia,xcvr-setup = <51>;
1191 nvidia,xcvr-setup-use-fuses;
1192 nvidia,xcvr-lsfslew = <2>;
1193 nvidia,xcvr-lsrslew = <2>;
1194 nvidia,xcvr-hsslew = <32>;
1195 nvidia,hssquelch-level = <2>;
1196 nvidia,hsdiscon-level = <5>;
1197 nvidia,pmc = <&tegra_pmc 2>;
1198 status = "disabled";
1199 };
1200
1201 usb@7d008000 {
1202 compatible = "nvidia,tegra30-ehci";
1203 reg = <0x7d008000 0x4000>;
1204 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1205 phy_type = "utmi";
1206 clocks = <&tegra_car TEGRA30_CLK_USB3>;
1207 resets = <&tegra_car 59>;
1208 reset-names = "usb";
1209 nvidia,phy = <&phy3>;
1210 power-domains = <&pd_core>;
1211 operating-points-v2 = <&usb3_dvfs_opp_table>;
1212 status = "disabled";
1213 };
1214
1215 phy3: usb-phy@7d008000 {
1216 compatible = "nvidia,tegra30-usb-phy";
1217 reg = <0x7d008000 0x4000>,
1218 <0x7d000000 0x4000>;
1219 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1220 phy_type = "utmi";
1221 clocks = <&tegra_car TEGRA30_CLK_USB3>,
1222 <&tegra_car TEGRA30_CLK_PLL_U>,
1223 <&tegra_car TEGRA30_CLK_USBD>;
1224 clock-names = "reg", "pll_u", "utmi-pads";
1225 resets = <&tegra_car 59>, <&tegra_car 22>;
1226 reset-names = "usb", "utmi-pads";
1227 #phy-cells = <0>;
1228 nvidia,hssync-start-delay = <0>;
1229 nvidia,idle-wait-delay = <17>;
1230 nvidia,elastic-limit = <16>;
1231 nvidia,term-range-adj = <6>;
1232 nvidia,xcvr-setup = <51>;
1233 nvidia,xcvr-setup-use-fuses;
1234 nvidia,xcvr-lsfslew = <2>;
1235 nvidia,xcvr-lsrslew = <2>;
1236 nvidia,xcvr-hsslew = <32>;
1237 nvidia,hssquelch-level = <2>;
1238 nvidia,hsdiscon-level = <5>;
1239 nvidia,pmc = <&tegra_pmc 1>;
1240 status = "disabled";
1241 };
1242
1243 cpus {
1244 #address-cells = <1>;
1245 #size-cells = <0>;
1246
1247 cpu0: cpu@0 {
1248 device_type = "cpu";
1249 compatible = "arm,cortex-a9";
1250 reg = <0>;
1251 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1252 #cooling-cells = <2>;
1253 };
1254
1255 cpu1: cpu@1 {
1256 device_type = "cpu";
1257 compatible = "arm,cortex-a9";
1258 reg = <1>;
1259 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1260 #cooling-cells = <2>;
1261 };
1262
1263 cpu2: cpu@2 {
1264 device_type = "cpu";
1265 compatible = "arm,cortex-a9";
1266 reg = <2>;
1267 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1268 #cooling-cells = <2>;
1269 };
1270
1271 cpu3: cpu@3 {
1272 device_type = "cpu";
1273 compatible = "arm,cortex-a9";
1274 reg = <3>;
1275 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1276 #cooling-cells = <2>;
1277 };
1278 };
1279
1280 pmu {
1281 compatible = "arm,cortex-a9-pmu";
1282 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1283 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1284 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1285 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1286 interrupt-affinity = <&{/cpus/cpu@0}>,
1287 <&{/cpus/cpu@1}>,
1288 <&{/cpus/cpu@2}>,
1289 <&{/cpus/cpu@3}>;
1290 };
1291
1292 thermal-zones {
1293 tsensor0-thermal {
1294 polling-delay-passive = <1000>; /* milliseconds */
1295 polling-delay = <5000>; /* milliseconds */
1296
1297 thermal-sensors = <&tsensor 0>;
1298
1299 trips {
1300 level1_trip: dvfs-alert {
1301 /* throttle at 80C until temperature drops to 79.8C */
1302 temperature = <80000>;
1303 hysteresis = <200>;
1304 type = "passive";
1305 };
1306
1307 level2_trip: cpu-div2-throttle {
1308 /* hardware CPU x2 freq throttle at 85C */
1309 temperature = <85000>;
1310 hysteresis = <200>;
1311 type = "hot";
1312 };
1313
1314 level3_trip: soc-critical {
1315 /* hardware shut down at 90C */
1316 temperature = <90000>;
1317 hysteresis = <2000>;
1318 type = "critical";
1319 };
1320 };
1321
1322 cooling-maps {
1323 map0 {
1324 trip = <&level1_trip>;
1325 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1326 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1327 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1328 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1329 <&actmon THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1330 };
1331 };
1332 };
1333
1334 tsensor1-thermal {
1335 status = "disabled";
1336
1337 polling-delay-passive = <1000>; /* milliseconds */
1338 polling-delay = <0>; /* milliseconds */
1339
1340 thermal-sensors = <&tsensor 1>;
1341
1342 trips {
1343 dvfs-alert {
1344 temperature = <80000>;
1345 hysteresis = <200>;
1346 type = "passive";
1347 };
1348 };
1349 };
1350 };
1351 };
