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0001 // SPDX-License-Identifier: GPL-2.0
0002 #include "tegra30.dtsi"
0003
0004 /*
0005 * Toradex Colibri T30 Module Device Tree
0006 * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E, V1.1F; IT: V1.1A, V1.1B
0007 */
0008 / {
0009 memory@80000000 {
0010 reg = <0x80000000 0x40000000>;
0011 };
0012
0013 host1x@50000000 {
0014 hdmi@54280000 {
0015 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
0016 nvidia,hpd-gpio =
0017 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
0018 pll-supply = <®_1v8_avdd_hdmi_pll>;
0019 vdd-supply = <®_3v3_avdd_hdmi>;
0020 };
0021 };
0022
0023 pinmux@70000868 {
0024 pinctrl-names = "default";
0025 pinctrl-0 = <&state_default>;
0026
0027 state_default: pinmux {
0028 /* Analogue Audio (On-module) */
0029 clk1-out-pw4 {
0030 nvidia,pins = "clk1_out_pw4";
0031 nvidia,function = "extperiph1";
0032 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0033 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0034 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0035 };
0036 dap3-fs-pp0 {
0037 nvidia,pins = "dap3_fs_pp0",
0038 "dap3_sclk_pp3",
0039 "dap3_din_pp1",
0040 "dap3_dout_pp2";
0041 nvidia,function = "i2s2";
0042 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0043 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0044 };
0045
0046 /* Colibri Address/Data Bus (GMI) */
0047 gmi-ad0-pg0 {
0048 nvidia,pins = "gmi_ad0_pg0",
0049 "gmi_ad2_pg2",
0050 "gmi_ad3_pg3",
0051 "gmi_ad4_pg4",
0052 "gmi_ad5_pg5",
0053 "gmi_ad6_pg6",
0054 "gmi_ad7_pg7",
0055 "gmi_ad8_ph0",
0056 "gmi_ad9_ph1",
0057 "gmi_ad10_ph2",
0058 "gmi_ad11_ph3",
0059 "gmi_ad12_ph4",
0060 "gmi_ad13_ph5",
0061 "gmi_ad14_ph6",
0062 "gmi_ad15_ph7",
0063 "gmi_adv_n_pk0",
0064 "gmi_clk_pk1",
0065 "gmi_cs4_n_pk2",
0066 "gmi_cs2_n_pk3",
0067 "gmi_iordy_pi5",
0068 "gmi_oe_n_pi1",
0069 "gmi_wait_pi7",
0070 "gmi_wr_n_pi0",
0071 "dap1_fs_pn0",
0072 "dap1_din_pn1",
0073 "dap1_dout_pn2",
0074 "dap1_sclk_pn3",
0075 "dap2_fs_pa2",
0076 "dap2_sclk_pa3",
0077 "dap2_din_pa4",
0078 "dap2_dout_pa5",
0079 "spi1_sck_px5",
0080 "spi1_mosi_px4",
0081 "spi1_cs0_n_px6",
0082 "spi2_cs0_n_px3",
0083 "spi2_miso_px1",
0084 "spi2_mosi_px0",
0085 "spi2_sck_px2",
0086 "uart2_cts_n_pj5",
0087 "uart2_rts_n_pj6";
0088 nvidia,function = "gmi";
0089 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0090 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0091 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0092 };
0093 /* Further pins may be used as GPIOs */
0094 dap4-din-pp5 {
0095 nvidia,pins = "dap4_din_pp5",
0096 "dap4_dout_pp6",
0097 "dap4_fs_pp4",
0098 "dap4_sclk_pp7",
0099 "pbb7",
0100 "sdmmc1_clk_pz0",
0101 "sdmmc1_cmd_pz1",
0102 "sdmmc1_dat0_py7",
0103 "sdmmc1_dat1_py6",
0104 "sdmmc1_dat3_py4",
0105 "uart3_cts_n_pa1",
0106 "uart3_txd_pw6",
0107 "uart3_rxd_pw7";
0108 nvidia,function = "rsvd2";
0109 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0110 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0111 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0112 };
0113 lcd-d18-pm2 {
0114 nvidia,pins = "lcd_d18_pm2",
0115 "lcd_d19_pm3",
0116 "lcd_d20_pm4",
0117 "lcd_d21_pm5",
0118 "lcd_d22_pm6",
0119 "lcd_d23_pm7",
0120 "lcd_dc0_pn6",
0121 "pex_l2_clkreq_n_pcc7";
0122 nvidia,function = "rsvd3";
0123 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0124 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0125 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0126 };
0127 lcd-cs0-n-pn4 {
0128 nvidia,pins = "lcd_cs0_n_pn4",
0129 "lcd_sdin_pz2",
0130 "pu0",
0131 "pu1",
0132 "pu2",
0133 "pu3",
0134 "pu4",
0135 "pu5",
0136 "pu6",
0137 "spi1_miso_px7",
0138 "uart3_rts_n_pc0";
0139 nvidia,function = "rsvd4";
0140 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0141 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0142 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0143 };
0144 lcd-pwr0-pb2 {
0145 nvidia,pins = "lcd_pwr0_pb2",
0146 "lcd_sck_pz4",
0147 "lcd_sdout_pn5",
0148 "lcd_wr_n_pz3";
0149 nvidia,function = "hdcp";
0150 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0151 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0152 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0153 };
0154 pbb4 {
0155 nvidia,pins = "pbb4",
0156 "pbb5",
0157 "pbb6";
0158 nvidia,function = "displayb";
0159 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0160 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0161 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0162 };
0163 /* Multiplexed RDnWR and therefore disabled */
0164 lcd-cs1-n-pw0 {
0165 nvidia,pins = "lcd_cs1_n_pw0";
0166 nvidia,function = "rsvd4";
0167 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0168 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0169 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0170 };
0171 /* Multiplexed GMI_CLK and therefore disabled */
0172 owr {
0173 nvidia,pins = "owr";
0174 nvidia,function = "rsvd3";
0175 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0176 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0177 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0178 };
0179 /* Tri-stating GMI_WR_N on nPWE SODIMM pin 99 */
0180 sdmmc3-dat4-pd1 {
0181 nvidia,pins = "sdmmc3_dat4_pd1";
0182 nvidia,function = "sdmmc3";
0183 nvidia,pull = <TEGRA_PIN_PULL_UP>;
0184 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0185 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0186 };
0187 /* Not tri-stating GMI_WR_N on RDnWR SODIMM pin 93 */
0188 sdmmc3-dat5-pd0 {
0189 nvidia,pins = "sdmmc3_dat5_pd0";
0190 nvidia,function = "sdmmc3";
0191 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0192 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0193 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0194 };
0195
0196 /* Colibri BL_ON */
0197 pv2 {
0198 nvidia,pins = "pv2";
0199 nvidia,function = "rsvd4";
0200 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0201 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0202 };
0203
0204 /* Colibri Backlight PWM<A> */
0205 sdmmc3-dat3-pb4 {
0206 nvidia,pins = "sdmmc3_dat3_pb4";
0207 nvidia,function = "pwm0";
0208 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0209 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0210 };
0211
0212 /* Colibri CAN_INT */
0213 kb-row8-ps0 {
0214 nvidia,pins = "kb_row8_ps0";
0215 nvidia,function = "kbc";
0216 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0217 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0218 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0219 };
0220
0221 /* Colibri DDC */
0222 ddc-scl-pv4 {
0223 nvidia,pins = "ddc_scl_pv4",
0224 "ddc_sda_pv5";
0225 nvidia,function = "i2c4";
0226 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0227 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0228 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0229 };
0230
0231 /* Colibri EXT_IO* */
0232 gen2-i2c-scl-pt5 {
0233 nvidia,pins = "gen2_i2c_scl_pt5",
0234 "gen2_i2c_sda_pt6";
0235 nvidia,function = "rsvd4";
0236 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
0237 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0238 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0239 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0240 };
0241 spdif-in-pk6 {
0242 nvidia,pins = "spdif_in_pk6";
0243 nvidia,function = "hda";
0244 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0245 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0246 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0247 };
0248
0249 /* Colibri GPIO */
0250 clk2-out-pw5 {
0251 nvidia,pins = "clk2_out_pw5",
0252 "pcc2",
0253 "pv3",
0254 "sdmmc1_dat2_py5";
0255 nvidia,function = "rsvd2";
0256 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0257 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0258 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0259 };
0260 lcd-pwr1-pc1 {
0261 nvidia,pins = "lcd_pwr1_pc1",
0262 "pex_l1_clkreq_n_pdd6",
0263 "pex_l1_rst_n_pdd5";
0264 nvidia,function = "rsvd3";
0265 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0266 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0267 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0268 };
0269 pv1 {
0270 nvidia,pins = "pv1",
0271 "sdmmc3_dat0_pb7",
0272 "sdmmc3_dat1_pb6";
0273 nvidia,function = "rsvd1";
0274 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0275 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0276 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0277 };
0278
0279 /* Colibri HOTPLUG_DETECT (HDMI) */
0280 hdmi-int-pn7 {
0281 nvidia,pins = "hdmi_int_pn7";
0282 nvidia,function = "hdmi";
0283 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0284 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0285 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0286 };
0287
0288 /* Colibri I2C */
0289 gen1-i2c-scl-pc4 {
0290 nvidia,pins = "gen1_i2c_scl_pc4",
0291 "gen1_i2c_sda_pc5";
0292 nvidia,function = "i2c1";
0293 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0294 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0295 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0296 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
0297 };
0298
0299 /* Colibri LCD (L_* resp. LDD<*>) */
0300 lcd-d0-pe0 {
0301 nvidia,pins = "lcd_d0_pe0",
0302 "lcd_d1_pe1",
0303 "lcd_d2_pe2",
0304 "lcd_d3_pe3",
0305 "lcd_d4_pe4",
0306 "lcd_d5_pe5",
0307 "lcd_d6_pe6",
0308 "lcd_d7_pe7",
0309 "lcd_d8_pf0",
0310 "lcd_d9_pf1",
0311 "lcd_d10_pf2",
0312 "lcd_d11_pf3",
0313 "lcd_d12_pf4",
0314 "lcd_d13_pf5",
0315 "lcd_d14_pf6",
0316 "lcd_d15_pf7",
0317 "lcd_d16_pm0",
0318 "lcd_d17_pm1",
0319 "lcd_de_pj1",
0320 "lcd_hsync_pj3",
0321 "lcd_pclk_pb3",
0322 "lcd_vsync_pj4";
0323 nvidia,function = "displaya";
0324 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0325 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0326 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0327 };
0328 /*
0329 * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
0330 * today's display need DE, disable LCD_M1
0331 */
0332 lcd-m1-pw1 {
0333 nvidia,pins = "lcd_m1_pw1";
0334 nvidia,function = "rsvd3";
0335 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0336 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0337 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0338 };
0339
0340 /* Colibri MMC */
0341 kb-row10-ps2 {
0342 nvidia,pins = "kb_row10_ps2";
0343 nvidia,function = "sdmmc2";
0344 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0345 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0346 };
0347 kb-row11-ps3 {
0348 nvidia,pins = "kb_row11_ps3",
0349 "kb_row12_ps4",
0350 "kb_row13_ps5",
0351 "kb_row14_ps6",
0352 "kb_row15_ps7";
0353 nvidia,function = "sdmmc2";
0354 nvidia,pull = <TEGRA_PIN_PULL_UP>;
0355 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0356 };
0357 /* Colibri MMC_CD */
0358 gmi-wp-n-pc7 {
0359 nvidia,pins = "gmi_wp_n_pc7";
0360 nvidia,function = "rsvd1";
0361 nvidia,pull = <TEGRA_PIN_PULL_UP>;
0362 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0363 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0364 };
0365 /* Multiplexed and therefore disabled */
0366 cam-mclk-pcc0 {
0367 nvidia,pins = "cam_mclk_pcc0";
0368 nvidia,function = "vi_alt3";
0369 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0370 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0371 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0372 };
0373 cam-i2c-scl-pbb1 {
0374 nvidia,pins = "cam_i2c_scl_pbb1",
0375 "cam_i2c_sda_pbb2";
0376 nvidia,function = "rsvd3";
0377 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0378 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0379 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0380 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
0381 };
0382 pbb0 {
0383 nvidia,pins = "pbb0",
0384 "pcc1";
0385 nvidia,function = "rsvd2";
0386 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0387 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0388 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0389 };
0390 pbb3 {
0391 nvidia,pins = "pbb3";
0392 nvidia,function = "displayb";
0393 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0394 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0395 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0396 };
0397
0398 /* Colibri nRESET_OUT */
0399 gmi-rst-n-pi4 {
0400 nvidia,pins = "gmi_rst_n_pi4";
0401 nvidia,function = "gmi";
0402 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0403 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0404 };
0405
0406 /*
0407 * Colibri Parallel Camera (Optional)
0408 * pins multiplexed with others and therefore disabled
0409 */
0410 vi-vsync-pd6 {
0411 nvidia,pins = "vi_d0_pt4",
0412 "vi_d1_pd5",
0413 "vi_d2_pl0",
0414 "vi_d3_pl1",
0415 "vi_d4_pl2",
0416 "vi_d5_pl3",
0417 "vi_d6_pl4",
0418 "vi_d7_pl5",
0419 "vi_d8_pl6",
0420 "vi_d9_pl7",
0421 "vi_d10_pt2",
0422 "vi_d11_pt3",
0423 "vi_hsync_pd7",
0424 "vi_mclk_pt1",
0425 "vi_pclk_pt0",
0426 "vi_vsync_pd6";
0427 nvidia,function = "vi";
0428 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0429 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0430 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0431 };
0432
0433 /* Colibri PWM<B> */
0434 sdmmc3-dat2-pb5 {
0435 nvidia,pins = "sdmmc3_dat2_pb5";
0436 nvidia,function = "pwm1";
0437 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0438 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0439 };
0440
0441 /* Colibri PWM<C> */
0442 sdmmc3-clk-pa6 {
0443 nvidia,pins = "sdmmc3_clk_pa6";
0444 nvidia,function = "pwm2";
0445 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0446 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0447 };
0448
0449 /* Colibri PWM<D> */
0450 sdmmc3-cmd-pa7 {
0451 nvidia,pins = "sdmmc3_cmd_pa7";
0452 nvidia,function = "pwm3";
0453 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0454 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0455 };
0456
0457 /* Colibri SSP */
0458 ulpi-clk-py0 {
0459 nvidia,pins = "ulpi_clk_py0",
0460 "ulpi_dir_py1",
0461 "ulpi_nxt_py2",
0462 "ulpi_stp_py3";
0463 nvidia,function = "spi1";
0464 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0465 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0466 };
0467 /* Multiplexed SSPFRM, SSPTXD and therefore disabled */
0468 sdmmc3-dat6-pd3 {
0469 nvidia,pins = "sdmmc3_dat6_pd3",
0470 "sdmmc3_dat7_pd4";
0471 nvidia,function = "spdif";
0472 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0473 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0474 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0475 };
0476
0477 /* Colibri UART-A */
0478 ulpi-data0 {
0479 nvidia,pins = "ulpi_data0_po1",
0480 "ulpi_data1_po2",
0481 "ulpi_data2_po3",
0482 "ulpi_data3_po4",
0483 "ulpi_data4_po5",
0484 "ulpi_data5_po6",
0485 "ulpi_data6_po7",
0486 "ulpi_data7_po0";
0487 nvidia,function = "uarta";
0488 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0489 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0490 };
0491
0492 /* Colibri UART-B */
0493 gmi-a16-pj7 {
0494 nvidia,pins = "gmi_a16_pj7",
0495 "gmi_a17_pb0",
0496 "gmi_a18_pb1",
0497 "gmi_a19_pk7";
0498 nvidia,function = "uartd";
0499 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0500 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0501 };
0502
0503 /* Colibri UART-C */
0504 uart2-rxd {
0505 nvidia,pins = "uart2_rxd_pc3",
0506 "uart2_txd_pc2";
0507 nvidia,function = "uartb";
0508 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0509 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0510 };
0511
0512 /* Colibri USBC_DET */
0513 spdif-out-pk5 {
0514 nvidia,pins = "spdif_out_pk5";
0515 nvidia,function = "rsvd2";
0516 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0517 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0518 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0519 };
0520
0521 /* Colibri USBH_PEN */
0522 spi2-cs1-n-pw2 {
0523 nvidia,pins = "spi2_cs1_n_pw2";
0524 nvidia,function = "spi2_alt";
0525 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0526 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0527 };
0528
0529 /* Colibri USBH_OC */
0530 spi2-cs2-n-pw3 {
0531 nvidia,pins = "spi2_cs2_n_pw3";
0532 nvidia,function = "spi2_alt";
0533 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0534 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0535 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0536 };
0537
0538 /* Colibri VGA not supported and therefore disabled */
0539 crt-hsync-pv6 {
0540 nvidia,pins = "crt_hsync_pv6",
0541 "crt_vsync_pv7";
0542 nvidia,function = "rsvd2";
0543 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0544 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0545 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0546 };
0547
0548 /* eMMC (On-module) */
0549 sdmmc4-clk-pcc4 {
0550 nvidia,pins = "sdmmc4_clk_pcc4",
0551 "sdmmc4_cmd_pt7",
0552 "sdmmc4_rst_n_pcc3";
0553 nvidia,function = "sdmmc4";
0554 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0555 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0556 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0557 };
0558 sdmmc4-dat0-paa0 {
0559 nvidia,pins = "sdmmc4_dat0_paa0",
0560 "sdmmc4_dat1_paa1",
0561 "sdmmc4_dat2_paa2",
0562 "sdmmc4_dat3_paa3",
0563 "sdmmc4_dat4_paa4",
0564 "sdmmc4_dat5_paa5",
0565 "sdmmc4_dat6_paa6",
0566 "sdmmc4_dat7_paa7";
0567 nvidia,function = "sdmmc4";
0568 nvidia,pull = <TEGRA_PIN_PULL_UP>;
0569 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0570 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0571 };
0572
0573 /* LAN_EXT_WAKEUP#, LAN_PME (On-module) */
0574 pex-l0-rst-n-pdd1 {
0575 nvidia,pins = "pex_l0_rst_n_pdd1",
0576 "pex_wake_n_pdd3";
0577 nvidia,function = "rsvd3";
0578 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0579 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0580 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0581 };
0582 /* LAN_V_BUS, LAN_RESET# (On-module) */
0583 pex-l0-clkreq-n-pdd2 {
0584 nvidia,pins = "pex_l0_clkreq_n_pdd2",
0585 "pex_l0_prsnt_n_pdd0";
0586 nvidia,function = "rsvd3";
0587 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0588 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0589 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0590 };
0591
0592 /* nBATT_FAULT(SENSE), nVDD_FAULT(SENSE) */
0593 pex-l2-rst-n-pcc6 {
0594 nvidia,pins = "pex_l2_rst_n_pcc6",
0595 "pex_l2_prsnt_n_pdd7";
0596 nvidia,function = "rsvd3";
0597 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0598 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0599 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0600 };
0601
0602 /* Not connected and therefore disabled */
0603 clk1-req-pee2 {
0604 nvidia,pins = "clk1_req_pee2",
0605 "pex_l1_prsnt_n_pdd4";
0606 nvidia,function = "rsvd3";
0607 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0608 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0609 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0610 };
0611 clk2-req-pcc5 {
0612 nvidia,pins = "clk2_req_pcc5",
0613 "clk3_out_pee0",
0614 "clk3_req_pee1",
0615 "clk_32k_out_pa0",
0616 "hdmi_cec_pee3",
0617 "sys_clk_req_pz5";
0618 nvidia,function = "rsvd2";
0619 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0620 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0621 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0622 };
0623 gmi-dqs-pi2 {
0624 nvidia,pins = "gmi_dqs_pi2",
0625 "kb_col2_pq2",
0626 "kb_col3_pq3",
0627 "kb_col4_pq4",
0628 "kb_col5_pq5",
0629 "kb_row4_pr4";
0630 nvidia,function = "rsvd4";
0631 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0632 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0633 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0634 };
0635 kb-col0-pq0 {
0636 nvidia,pins = "kb_col0_pq0",
0637 "kb_col1_pq1",
0638 "kb_col6_pq6",
0639 "kb_col7_pq7",
0640 "kb_row5_pr5",
0641 "kb_row6_pr6",
0642 "kb_row7_pr7",
0643 "kb_row9_ps1";
0644 nvidia,function = "kbc";
0645 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0646 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0647 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0648 };
0649 kb-row0-pr0 {
0650 nvidia,pins = "kb_row0_pr0",
0651 "kb_row1_pr1",
0652 "kb_row2_pr2",
0653 "kb_row3_pr3";
0654 nvidia,function = "rsvd3";
0655 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0656 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0657 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0658 };
0659 lcd-pwr2-pc6 {
0660 nvidia,pins = "lcd_pwr2_pc6";
0661 nvidia,function = "hdcp";
0662 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0663 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0664 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0665 };
0666
0667 /* Power I2C (On-module) */
0668 pwr-i2c-scl-pz6 {
0669 nvidia,pins = "pwr_i2c_scl_pz6",
0670 "pwr_i2c_sda_pz7";
0671 nvidia,function = "i2cpwr";
0672 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0673 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0674 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0675 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
0676 };
0677
0678 /*
0679 * THERMD_ALERT#, unlatched I2C address pin of LM95245
0680 * temperature sensor therefore requires disabling for
0681 * now
0682 */
0683 lcd-dc1-pd2 {
0684 nvidia,pins = "lcd_dc1_pd2";
0685 nvidia,function = "rsvd3";
0686 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0687 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0688 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0689 };
0690
0691 /* TOUCH_PEN_INT# (On-module) */
0692 pv0 {
0693 nvidia,pins = "pv0";
0694 nvidia,function = "rsvd1";
0695 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0696 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0697 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0698 };
0699 };
0700 };
0701
0702 serial@70006040 {
0703 compatible = "nvidia,tegra30-hsuart";
0704 /delete-property/ reg-shift;
0705 };
0706
0707 serial@70006300 {
0708 compatible = "nvidia,tegra30-hsuart";
0709 /delete-property/ reg-shift;
0710 };
0711
0712 hdmi_ddc: i2c@7000c700 {
0713 clock-frequency = <10000>;
0714 };
0715
0716 /*
0717 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
0718 * touch screen controller (On-module)
0719 */
0720 i2c@7000d000 {
0721 status = "okay";
0722 clock-frequency = <100000>;
0723
0724 /* SGTL5000 audio codec */
0725 sgtl5000: codec@a {
0726 compatible = "fsl,sgtl5000";
0727 reg = <0x0a>;
0728 #sound-dai-cells = <0>;
0729 VDDA-supply = <®_module_3v3_audio>;
0730 VDDD-supply = <®_1v8_vio>;
0731 VDDIO-supply = <®_module_3v3>;
0732 clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
0733 };
0734
0735 pmic: pmic@2d {
0736 compatible = "ti,tps65911";
0737 reg = <0x2d>;
0738
0739 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0740 #interrupt-cells = <2>;
0741 interrupt-controller;
0742 wakeup-source;
0743
0744 ti,system-power-controller;
0745
0746 #gpio-cells = <2>;
0747 gpio-controller;
0748
0749 vcc1-supply = <®_module_3v3>;
0750 vcc2-supply = <®_module_3v3>;
0751 vcc3-supply = <®_1v8_vio>;
0752 vcc4-supply = <®_module_3v3>;
0753 vcc5-supply = <®_module_3v3>;
0754 vcc6-supply = <®_1v8_vio>;
0755 vcc7-supply = <®_5v0_charge_pump>;
0756 vccio-supply = <®_module_3v3>;
0757
0758 regulators {
0759 vdd1_reg: vdd1 {
0760 regulator-name = "+V1.35_VDDIO_DDR";
0761 regulator-min-microvolt = <1350000>;
0762 regulator-max-microvolt = <1350000>;
0763 regulator-always-on;
0764 };
0765
0766 /* SW2: unused */
0767
0768 vddctrl_reg: vddctrl {
0769 regulator-name = "+V1.0_VDD_CPU";
0770 regulator-min-microvolt = <800000>;
0771 regulator-max-microvolt = <1250000>;
0772 regulator-coupled-with = <&vdd_core>;
0773 regulator-coupled-max-spread = <300000>;
0774 regulator-max-step-microvolt = <100000>;
0775 regulator-always-on;
0776
0777 nvidia,tegra-cpu-regulator;
0778 };
0779
0780 reg_1v8_vio: vio {
0781 regulator-name = "+V1.8";
0782 regulator-min-microvolt = <1800000>;
0783 regulator-max-microvolt = <1800000>;
0784 regulator-always-on;
0785 };
0786
0787 /* LDO1: unused */
0788
0789 /*
0790 * EN_+V3.3 switching via FET:
0791 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
0792 * see also +V3.3 fixed supply
0793 */
0794 ldo2_reg: ldo2 {
0795 regulator-name = "EN_+V3.3";
0796 regulator-min-microvolt = <3300000>;
0797 regulator-max-microvolt = <3300000>;
0798 regulator-always-on;
0799 };
0800
0801 /* LDO3: unused */
0802
0803 ldo4_reg: ldo4 {
0804 regulator-name = "+V1.2_VDD_RTC";
0805 regulator-min-microvolt = <1200000>;
0806 regulator-max-microvolt = <1200000>;
0807 regulator-always-on;
0808 };
0809
0810 /*
0811 * +V2.8_AVDD_VDAC:
0812 * only required for (unsupported) analog RGB
0813 */
0814 ldo5_reg: ldo5 {
0815 regulator-name = "+V2.8_AVDD_VDAC";
0816 regulator-min-microvolt = <2800000>;
0817 regulator-max-microvolt = <2800000>;
0818 regulator-always-on;
0819 };
0820
0821 /*
0822 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
0823 * but LDO6 can't set voltage in 50mV
0824 * granularity
0825 */
0826 ldo6_reg: ldo6 {
0827 regulator-name = "+V1.05_AVDD_PLLE";
0828 regulator-min-microvolt = <1100000>;
0829 regulator-max-microvolt = <1100000>;
0830 };
0831
0832 ldo7_reg: ldo7 {
0833 regulator-name = "+V1.2_AVDD_PLL";
0834 regulator-min-microvolt = <1200000>;
0835 regulator-max-microvolt = <1200000>;
0836 regulator-always-on;
0837 };
0838
0839 ldo8_reg: ldo8 {
0840 regulator-name = "+V1.0_VDD_DDR_HS";
0841 regulator-min-microvolt = <1000000>;
0842 regulator-max-microvolt = <1000000>;
0843 regulator-always-on;
0844 };
0845 };
0846 };
0847
0848 /* STMPE811 touch screen controller */
0849 touchscreen@41 {
0850 compatible = "st,stmpe811";
0851 reg = <0x41>;
0852 irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
0853 interrupt-controller;
0854 id = <0>;
0855 blocks = <0x5>;
0856 irq-trigger = <0x1>;
0857 /* 3.25 MHz ADC clock speed */
0858 st,adc-freq = <1>;
0859 /* 12-bit ADC */
0860 st,mod-12b = <1>;
0861 /* internal ADC reference */
0862 st,ref-sel = <0>;
0863 /* ADC converstion time: 80 clocks */
0864 st,sample-time = <4>;
0865 /* forbid to use ADC channels 3-0 (touch) */
0866
0867 stmpe_touchscreen {
0868 compatible = "st,stmpe-ts";
0869 /* 8 sample average control */
0870 st,ave-ctrl = <3>;
0871 /* 7 length fractional part in z */
0872 st,fraction-z = <7>;
0873 /*
0874 * 50 mA typical 80 mA max touchscreen drivers
0875 * current limit value
0876 */
0877 st,i-drive = <1>;
0878 /* 1 ms panel driver settling time */
0879 st,settling = <3>;
0880 /* 5 ms touch detect interrupt delay */
0881 st,touch-det-delay = <5>;
0882 };
0883
0884 stmpe_adc {
0885 compatible = "st,stmpe-adc";
0886 st,norequest-mask = <0x0F>;
0887 };
0888 };
0889
0890 /*
0891 * LM95245 temperature sensor
0892 * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
0893 */
0894 temp-sensor@4c {
0895 compatible = "national,lm95245";
0896 reg = <0x4c>;
0897 };
0898
0899 /* SW: +V1.2_VDD_CORE */
0900 vdd_core: regulator@60 {
0901 compatible = "ti,tps62362";
0902 reg = <0x60>;
0903
0904 regulator-name = "tps62362-vout";
0905 regulator-min-microvolt = <900000>;
0906 regulator-max-microvolt = <1400000>;
0907 regulator-coupled-with = <&vddctrl_reg>;
0908 regulator-coupled-max-spread = <300000>;
0909 regulator-max-step-microvolt = <100000>;
0910 regulator-boot-on;
0911 regulator-always-on;
0912
0913 nvidia,tegra-core-regulator;
0914 };
0915 };
0916
0917 pmc@7000e400 {
0918 nvidia,invert-interrupt;
0919 nvidia,suspend-mode = <1>;
0920 nvidia,cpu-pwr-good-time = <5000>;
0921 nvidia,cpu-pwr-off-time = <5000>;
0922 nvidia,core-pwr-good-time = <3845 3845>;
0923 nvidia,core-pwr-off-time = <0>;
0924 nvidia,core-power-req-active-high;
0925 nvidia,sys-clock-req-active-high;
0926 core-supply = <&vdd_core>;
0927
0928 /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
0929 i2c-thermtrip {
0930 nvidia,i2c-controller-id = <4>;
0931 nvidia,bus-addr = <0x2d>;
0932 nvidia,reg-addr = <0x3f>;
0933 nvidia,reg-data = <0x1>;
0934 };
0935 };
0936
0937 hda@70030000 {
0938 status = "okay";
0939 };
0940
0941 ahub@70080000 {
0942 i2s@70080500 {
0943 status = "okay";
0944 };
0945 };
0946
0947 /* eMMC */
0948 mmc@78000600 {
0949 status = "okay";
0950 bus-width = <8>;
0951 non-removable;
0952 vmmc-supply = <®_module_3v3>; /* VCC */
0953 vqmmc-supply = <®_1v8_vio>; /* VCCQ */
0954 mmc-ddr-1_8v;
0955 };
0956
0957 /* EHCI instance 1: USB2_DP/N -> AX88772B (On-module) */
0958 usb@7d004000 {
0959 status = "okay";
0960 #address-cells = <1>;
0961 #size-cells = <0>;
0962
0963 ethernet@1 {
0964 compatible = "usbb95,772b";
0965 reg = <1>;
0966 local-mac-address = [00 00 00 00 00 00];
0967 };
0968 };
0969
0970 usb-phy@7d004000 {
0971 status = "okay";
0972 vbus-supply = <®_lan_v_bus>;
0973 };
0974
0975 clk32k_in: xtal1 {
0976 compatible = "fixed-clock";
0977 #clock-cells = <0>;
0978 clock-frequency = <32768>;
0979 };
0980
0981 reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
0982 compatible = "regulator-fixed";
0983 regulator-name = "+V1.8_AVDD_HDMI_PLL";
0984 regulator-min-microvolt = <1800000>;
0985 regulator-max-microvolt = <1800000>;
0986 enable-active-high;
0987 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
0988 vin-supply = <®_1v8_vio>;
0989 };
0990
0991 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
0992 compatible = "regulator-fixed";
0993 regulator-name = "+V3.3_AVDD_HDMI";
0994 regulator-min-microvolt = <3300000>;
0995 regulator-max-microvolt = <3300000>;
0996 enable-active-high;
0997 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
0998 vin-supply = <®_module_3v3>;
0999 };
1000
1001 reg_5v0_charge_pump: regulator-5v0-charge-pump {
1002 compatible = "regulator-fixed";
1003 regulator-name = "+V5.0";
1004 regulator-min-microvolt = <5000000>;
1005 regulator-max-microvolt = <5000000>;
1006 regulator-always-on;
1007 };
1008
1009 reg_lan_v_bus: regulator-lan-v-bus {
1010 compatible = "regulator-fixed";
1011 regulator-name = "LAN_V_BUS";
1012 regulator-min-microvolt = <5000000>;
1013 regulator-max-microvolt = <5000000>;
1014 enable-active-high;
1015 gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
1016 };
1017
1018 reg_module_3v3: regulator-module-3v3 {
1019 compatible = "regulator-fixed";
1020 regulator-name = "+V3.3";
1021 regulator-min-microvolt = <3300000>;
1022 regulator-max-microvolt = <3300000>;
1023 regulator-always-on;
1024 };
1025
1026 reg_module_3v3_audio: regulator-module-3v3-audio {
1027 compatible = "regulator-fixed";
1028 regulator-name = "+V3.3_AUDIO_AVDD_S";
1029 regulator-min-microvolt = <3300000>;
1030 regulator-max-microvolt = <3300000>;
1031 regulator-always-on;
1032 };
1033
1034 sound {
1035 compatible = "toradex,tegra-audio-sgtl5000-colibri_t30",
1036 "nvidia,tegra-audio-sgtl5000";
1037 nvidia,model = "Toradex Colibri T30";
1038 nvidia,audio-routing =
1039 "Headphone Jack", "HP_OUT",
1040 "LINE_IN", "Line In Jack",
1041 "MIC_IN", "Mic Jack";
1042 nvidia,i2s-controller = <&tegra_i2s2>;
1043 nvidia,audio-codec = <&sgtl5000>;
1044 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
1045 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1046 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1047 clock-names = "pll_a", "pll_a_out0", "mclk";
1048
1049 assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
1050 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1051
1052 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1053 <&tegra_car TEGRA30_CLK_EXTERN1>;
1054 };
1055 };
1056
1057 &gpio {
1058 lan-reset-n-hog {
1059 gpio-hog;
1060 gpios = <TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
1061 output-high;
1062 line-name = "LAN_RESET#";
1063 };
1064 };
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