0001 // SPDX-License-Identifier: GPL-2.0
0002 #include "tegra30.dtsi"
0003
0004 /*
0005 * Toradex Apalis T30 Module Device Tree
0006 * Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C, V1.0E
0007 */
0008 / {
0009 memory@80000000 {
0010 reg = <0x80000000 0x40000000>;
0011 };
0012
0013 pcie@3000 {
0014 status = "okay";
0015 avdd-pexa-supply = <&vdd2_reg>;
0016 avdd-pexb-supply = <&vdd2_reg>;
0017 avdd-pex-pll-supply = <&vdd2_reg>;
0018 avdd-plle-supply = <&ldo6_reg>;
0019 hvdd-pex-supply = <®_module_3v3>;
0020 vddio-pex-ctl-supply = <®_module_3v3>;
0021 vdd-pexa-supply = <&vdd2_reg>;
0022 vdd-pexb-supply = <&vdd2_reg>;
0023
0024 /* Apalis type specific */
0025 pci@1,0 {
0026 nvidia,num-lanes = <4>;
0027 };
0028
0029 /* Apalis PCIe */
0030 pci@2,0 {
0031 nvidia,num-lanes = <1>;
0032 };
0033
0034 /* I210/I211 Gigabit Ethernet Controller (on-module) */
0035 pci@3,0 {
0036 status = "okay";
0037 nvidia,num-lanes = <1>;
0038
0039 ethernet@0,0 {
0040 reg = <0 0 0 0 0>;
0041 local-mac-address = [00 00 00 00 00 00];
0042 };
0043 };
0044 };
0045
0046 host1x@50000000 {
0047 hdmi@54280000 {
0048 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
0049 nvidia,hpd-gpio =
0050 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
0051 pll-supply = <®_1v8_avdd_hdmi_pll>;
0052 vdd-supply = <®_3v3_avdd_hdmi>;
0053 };
0054 };
0055
0056 pinmux@70000868 {
0057 pinctrl-names = "default";
0058 pinctrl-0 = <&state_default>;
0059
0060 state_default: pinmux {
0061 /* Analogue Audio (On-module) */
0062 clk1-out-pw4 {
0063 nvidia,pins = "clk1_out_pw4";
0064 nvidia,function = "extperiph1";
0065 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0066 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0067 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0068 };
0069 dap3-fs-pp0 {
0070 nvidia,pins = "dap3_fs_pp0",
0071 "dap3_sclk_pp3",
0072 "dap3_din_pp1",
0073 "dap3_dout_pp2";
0074 nvidia,function = "i2s2";
0075 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0076 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0077 };
0078
0079 /* Apalis BKL1_ON */
0080 pv2 {
0081 nvidia,pins = "pv2";
0082 nvidia,function = "rsvd4";
0083 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0084 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0085 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0086 };
0087
0088 /* Apalis BKL1_PWM */
0089 uart3-rts-n-pc0 {
0090 nvidia,pins = "uart3_rts_n_pc0";
0091 nvidia,function = "pwm0";
0092 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0093 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0094 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0095 };
0096 /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
0097 uart3-cts-n-pa1 {
0098 nvidia,pins = "uart3_cts_n_pa1";
0099 nvidia,function = "rsvd2";
0100 nvidia,pull = <TEGRA_PIN_PULL_UP>;
0101 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0102 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0103 };
0104
0105 /* Apalis CAN1 on SPI6 */
0106 spi2-cs0-n-px3 {
0107 nvidia,pins = "spi2_cs0_n_px3",
0108 "spi2_miso_px1",
0109 "spi2_mosi_px0",
0110 "spi2_sck_px2";
0111 nvidia,function = "spi6";
0112 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0113 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0114 };
0115 /* CAN_INT1 */
0116 spi2-cs1-n-pw2 {
0117 nvidia,pins = "spi2_cs1_n_pw2";
0118 nvidia,function = "spi3";
0119 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0120 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0121 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0122 };
0123
0124 /* Apalis CAN2 on SPI4 */
0125 gmi-a16-pj7 {
0126 nvidia,pins = "gmi_a16_pj7",
0127 "gmi_a17_pb0",
0128 "gmi_a18_pb1",
0129 "gmi_a19_pk7";
0130 nvidia,function = "spi4";
0131 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0132 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0133 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0134 };
0135 /* CAN_INT2 */
0136 spi2-cs2-n-pw3 {
0137 nvidia,pins = "spi2_cs2_n_pw3";
0138 nvidia,function = "spi3";
0139 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0140 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0141 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0142 };
0143
0144 /* Apalis Digital Audio */
0145 clk1-req-pee2 {
0146 nvidia,pins = "clk1_req_pee2";
0147 nvidia,function = "hda";
0148 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0149 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0150 };
0151 clk2-out-pw5 {
0152 nvidia,pins = "clk2_out_pw5";
0153 nvidia,function = "extperiph2";
0154 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0155 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0156 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0157 };
0158 dap1-fs-pn0 {
0159 nvidia,pins = "dap1_fs_pn0",
0160 "dap1_din_pn1",
0161 "dap1_dout_pn2",
0162 "dap1_sclk_pn3";
0163 nvidia,function = "hda";
0164 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0165 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0166 };
0167
0168 /* Apalis GPIO */
0169 kb-col0-pq0 {
0170 nvidia,pins = "kb_col0_pq0",
0171 "kb_col1_pq1",
0172 "kb_row10_ps2",
0173 "kb_row11_ps3",
0174 "kb_row12_ps4",
0175 "kb_row13_ps5",
0176 "kb_row14_ps6",
0177 "kb_row15_ps7";
0178 nvidia,function = "kbc";
0179 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0180 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0181 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0182 };
0183 /* Multiplexed and therefore disabled */
0184 owr {
0185 nvidia,pins = "owr";
0186 nvidia,function = "rsvd3";
0187 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0188 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0189 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0190 };
0191
0192 /* Apalis HDMI1 */
0193 hdmi-cec-pee3 {
0194 nvidia,pins = "hdmi_cec_pee3";
0195 nvidia,function = "cec";
0196 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0197 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0198 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0199 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
0200 };
0201 hdmi-int-pn7 {
0202 nvidia,pins = "hdmi_int_pn7";
0203 nvidia,function = "hdmi";
0204 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0205 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0206 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0207 };
0208
0209 /* Apalis I2C1 */
0210 gen1-i2c-scl-pc4 {
0211 nvidia,pins = "gen1_i2c_scl_pc4",
0212 "gen1_i2c_sda_pc5";
0213 nvidia,function = "i2c1";
0214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0215 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0216 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0217 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
0218 };
0219
0220 /* Apalis I2C2 (DDC) */
0221 ddc-scl-pv4 {
0222 nvidia,pins = "ddc_scl_pv4",
0223 "ddc_sda_pv5";
0224 nvidia,function = "i2c4";
0225 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0226 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0227 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0228 };
0229
0230 /* Apalis I2C3 (CAM) */
0231 cam-i2c-scl-pbb1 {
0232 nvidia,pins = "cam_i2c_scl_pbb1",
0233 "cam_i2c_sda_pbb2";
0234 nvidia,function = "i2c3";
0235 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0236 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0237 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0238 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
0239 };
0240
0241 /* Apalis LCD1 */
0242 lcd-d0-pe0 {
0243 nvidia,pins = "lcd_d0_pe0",
0244 "lcd_d1_pe1",
0245 "lcd_d2_pe2",
0246 "lcd_d3_pe3",
0247 "lcd_d4_pe4",
0248 "lcd_d5_pe5",
0249 "lcd_d6_pe6",
0250 "lcd_d7_pe7",
0251 "lcd_d8_pf0",
0252 "lcd_d9_pf1",
0253 "lcd_d10_pf2",
0254 "lcd_d11_pf3",
0255 "lcd_d12_pf4",
0256 "lcd_d13_pf5",
0257 "lcd_d14_pf6",
0258 "lcd_d15_pf7",
0259 "lcd_d16_pm0",
0260 "lcd_d17_pm1",
0261 "lcd_d18_pm2",
0262 "lcd_d19_pm3",
0263 "lcd_d20_pm4",
0264 "lcd_d21_pm5",
0265 "lcd_d22_pm6",
0266 "lcd_d23_pm7",
0267 "lcd_de_pj1",
0268 "lcd_hsync_pj3",
0269 "lcd_pclk_pb3",
0270 "lcd_vsync_pj4";
0271 nvidia,function = "displaya";
0272 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0273 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0274 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0275 };
0276
0277 /* Apalis MMC1 */
0278 sdmmc3-clk-pa6 {
0279 nvidia,pins = "sdmmc3_clk_pa6";
0280 nvidia,function = "sdmmc3";
0281 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0282 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0283 };
0284 sdmmc3-dat0-pb7 {
0285 nvidia,pins = "sdmmc3_cmd_pa7",
0286 "sdmmc3_dat0_pb7",
0287 "sdmmc3_dat1_pb6",
0288 "sdmmc3_dat2_pb5",
0289 "sdmmc3_dat3_pb4",
0290 "sdmmc3_dat4_pd1",
0291 "sdmmc3_dat5_pd0",
0292 "sdmmc3_dat6_pd3",
0293 "sdmmc3_dat7_pd4";
0294 nvidia,function = "sdmmc3";
0295 nvidia,pull = <TEGRA_PIN_PULL_UP>;
0296 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0297 };
0298 /* Apalis MMC1_CD# */
0299 pv3 {
0300 nvidia,pins = "pv3";
0301 nvidia,function = "rsvd2";
0302 nvidia,pull = <TEGRA_PIN_PULL_UP>;
0303 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0304 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0305 };
0306
0307 /* Apalis Parallel Camera */
0308 cam-mclk-pcc0 {
0309 nvidia,pins = "cam_mclk_pcc0";
0310 nvidia,function = "vi_alt3";
0311 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0312 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0313 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0314 };
0315 vi-vsync-pd6 {
0316 nvidia,pins = "vi_d0_pt4",
0317 "vi_d1_pd5",
0318 "vi_d2_pl0",
0319 "vi_d3_pl1",
0320 "vi_d4_pl2",
0321 "vi_d5_pl3",
0322 "vi_d6_pl4",
0323 "vi_d7_pl5",
0324 "vi_d8_pl6",
0325 "vi_d9_pl7",
0326 "vi_d10_pt2",
0327 "vi_d11_pt3",
0328 "vi_hsync_pd7",
0329 "vi_pclk_pt0",
0330 "vi_vsync_pd6";
0331 nvidia,function = "vi";
0332 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0333 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0334 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0335 };
0336 /* Multiplexed and therefore disabled */
0337 kb-col2-pq2 {
0338 nvidia,pins = "kb_col2_pq2",
0339 "kb_col3_pq3",
0340 "kb_col4_pq4",
0341 "kb_row4_pr4";
0342 nvidia,function = "rsvd4";
0343 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0344 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0345 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0346 };
0347 kb-row0-pr0 {
0348 nvidia,pins = "kb_row0_pr0",
0349 "kb_row1_pr1",
0350 "kb_row2_pr2",
0351 "kb_row3_pr3";
0352 nvidia,function = "rsvd3";
0353 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0354 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0355 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0356 };
0357 kb-row5-pr5 {
0358 nvidia,pins = "kb_row5_pr5",
0359 "kb_row6_pr6",
0360 "kb_row7_pr7";
0361 nvidia,function = "kbc";
0362 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0363 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0364 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0365 };
0366 /*
0367 * VI level-shifter direction
0368 * (pull-down => default direction input)
0369 */
0370 vi-mclk-pt1 {
0371 nvidia,pins = "vi_mclk_pt1";
0372 nvidia,function = "vi_alt3";
0373 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0374 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0375 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0376 };
0377
0378 /* Apalis PWM1 */
0379 pu6 {
0380 nvidia,pins = "pu6";
0381 nvidia,function = "pwm3";
0382 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0383 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0384 };
0385
0386 /* Apalis PWM2 */
0387 pu5 {
0388 nvidia,pins = "pu5";
0389 nvidia,function = "pwm2";
0390 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0391 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0392 };
0393
0394 /* Apalis PWM3 */
0395 pu4 {
0396 nvidia,pins = "pu4";
0397 nvidia,function = "pwm1";
0398 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0399 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0400 };
0401
0402 /* Apalis PWM4 */
0403 pu3 {
0404 nvidia,pins = "pu3";
0405 nvidia,function = "pwm0";
0406 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0407 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0408 };
0409
0410 /* Apalis RESET_MOCI# */
0411 gmi-rst-n-pi4 {
0412 nvidia,pins = "gmi_rst_n_pi4";
0413 nvidia,function = "gmi";
0414 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0415 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0416 };
0417
0418 /* Apalis SATA1_ACT# */
0419 pex-l0-prsnt-n-pdd0 {
0420 nvidia,pins = "pex_l0_prsnt_n_pdd0";
0421 nvidia,function = "rsvd3";
0422 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0423 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0424 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0425 };
0426
0427 /* Apalis SD1 */
0428 sdmmc1-clk-pz0 {
0429 nvidia,pins = "sdmmc1_clk_pz0";
0430 nvidia,function = "sdmmc1";
0431 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0432 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0433 };
0434 sdmmc1-cmd-pz1 {
0435 nvidia,pins = "sdmmc1_cmd_pz1",
0436 "sdmmc1_dat0_py7",
0437 "sdmmc1_dat1_py6",
0438 "sdmmc1_dat2_py5",
0439 "sdmmc1_dat3_py4";
0440 nvidia,function = "sdmmc1";
0441 nvidia,pull = <TEGRA_PIN_PULL_UP>;
0442 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0443 };
0444 /* Apalis SD1_CD# */
0445 clk2-req-pcc5 {
0446 nvidia,pins = "clk2_req_pcc5";
0447 nvidia,function = "rsvd2";
0448 nvidia,pull = <TEGRA_PIN_PULL_UP>;
0449 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0450 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0451 };
0452
0453 /* Apalis SPDIF1 */
0454 spdif-out-pk5 {
0455 nvidia,pins = "spdif_out_pk5",
0456 "spdif_in_pk6";
0457 nvidia,function = "spdif";
0458 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0459 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0460 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0461 };
0462
0463 /* Apalis SPI1 */
0464 spi1-sck-px5 {
0465 nvidia,pins = "spi1_sck_px5",
0466 "spi1_mosi_px4",
0467 "spi1_miso_px7",
0468 "spi1_cs0_n_px6";
0469 nvidia,function = "spi1";
0470 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0471 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0472 };
0473
0474 /* Apalis SPI2 */
0475 lcd-sck-pz4 {
0476 nvidia,pins = "lcd_sck_pz4",
0477 "lcd_sdout_pn5",
0478 "lcd_sdin_pz2",
0479 "lcd_cs0_n_pn4";
0480 nvidia,function = "spi5";
0481 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0482 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0483 };
0484
0485 /*
0486 * Apalis TS (Low-speed type specific)
0487 * pins may be used as GPIOs
0488 */
0489 kb-col5-pq5 {
0490 nvidia,pins = "kb_col5_pq5";
0491 nvidia,function = "rsvd4";
0492 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0493 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0494 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0495 };
0496 kb-col6-pq6 {
0497 nvidia,pins = "kb_col6_pq6",
0498 "kb_col7_pq7",
0499 "kb_row8_ps0",
0500 "kb_row9_ps1";
0501 nvidia,function = "kbc";
0502 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0503 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0504 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0505 };
0506
0507 /* Apalis UART1 */
0508 ulpi-data0 {
0509 nvidia,pins = "ulpi_data0_po1",
0510 "ulpi_data1_po2",
0511 "ulpi_data2_po3",
0512 "ulpi_data3_po4",
0513 "ulpi_data4_po5",
0514 "ulpi_data5_po6",
0515 "ulpi_data6_po7",
0516 "ulpi_data7_po0";
0517 nvidia,function = "uarta";
0518 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0519 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0520 };
0521
0522 /* Apalis UART2 */
0523 ulpi-clk-py0 {
0524 nvidia,pins = "ulpi_clk_py0",
0525 "ulpi_dir_py1",
0526 "ulpi_nxt_py2",
0527 "ulpi_stp_py3";
0528 nvidia,function = "uartd";
0529 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0530 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0531 };
0532
0533 /* Apalis UART3 */
0534 uart2-rxd-pc3 {
0535 nvidia,pins = "uart2_rxd_pc3",
0536 "uart2_txd_pc2";
0537 nvidia,function = "uartb";
0538 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0539 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0540 };
0541
0542 /* Apalis UART4 */
0543 uart3-rxd-pw7 {
0544 nvidia,pins = "uart3_rxd_pw7",
0545 "uart3_txd_pw6";
0546 nvidia,function = "uartc";
0547 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0548 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0549 };
0550
0551 /* Apalis USBH_EN */
0552 pex-l0-rst-n-pdd1 {
0553 nvidia,pins = "pex_l0_rst_n_pdd1";
0554 nvidia,function = "rsvd3";
0555 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0556 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0557 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0558 };
0559
0560 /* Apalis USBH_OC# */
0561 pex-l0-clkreq-n-pdd2 {
0562 nvidia,pins = "pex_l0_clkreq_n_pdd2";
0563 nvidia,function = "rsvd3";
0564 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0565 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0566 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0567 };
0568
0569 /* Apalis USBO1_EN */
0570 gen2-i2c-scl-pt5 {
0571 nvidia,pins = "gen2_i2c_scl_pt5";
0572 nvidia,function = "rsvd4";
0573 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
0574 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0575 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0576 };
0577
0578 /* Apalis USBO1_OC# */
0579 gen2-i2c-sda-pt6 {
0580 nvidia,pins = "gen2_i2c_sda_pt6";
0581 nvidia,function = "rsvd4";
0582 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
0583 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0584 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0585 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0586 };
0587
0588 /* Apalis VGA1 not supported and therefore disabled */
0589 crt-hsync-pv6 {
0590 nvidia,pins = "crt_hsync_pv6",
0591 "crt_vsync_pv7";
0592 nvidia,function = "rsvd2";
0593 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0594 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0595 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0596 };
0597
0598 /* Apalis WAKE1_MICO */
0599 pv1 {
0600 nvidia,pins = "pv1";
0601 nvidia,function = "rsvd1";
0602 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0603 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0604 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0605 };
0606
0607 /* eMMC (On-module) */
0608 sdmmc4-clk-pcc4 {
0609 nvidia,pins = "sdmmc4_clk_pcc4",
0610 "sdmmc4_cmd_pt7",
0611 "sdmmc4_rst_n_pcc3";
0612 nvidia,function = "sdmmc4";
0613 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0614 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0615 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0616 };
0617 sdmmc4-dat0-paa0 {
0618 nvidia,pins = "sdmmc4_dat0_paa0",
0619 "sdmmc4_dat1_paa1",
0620 "sdmmc4_dat2_paa2",
0621 "sdmmc4_dat3_paa3",
0622 "sdmmc4_dat4_paa4",
0623 "sdmmc4_dat5_paa5",
0624 "sdmmc4_dat6_paa6",
0625 "sdmmc4_dat7_paa7";
0626 nvidia,function = "sdmmc4";
0627 nvidia,pull = <TEGRA_PIN_PULL_UP>;
0628 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0629 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0630 };
0631
0632 /* LAN i210/i211 DEV_OFF_N, PE_RST_N (On-module) */
0633 pex-l2-prsnt-n-pdd7 {
0634 nvidia,pins = "pex_l2_prsnt_n_pdd7",
0635 "pex_l2_rst_n_pcc6";
0636 nvidia,function = "pcie";
0637 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0638 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0639 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0640 };
0641 /* LAN i210/i211 PE_WAKE_N, SDP3 (On-module) */
0642 pex-wake-n-pdd3 {
0643 nvidia,pins = "pex_wake_n_pdd3",
0644 "pex_l2_clkreq_n_pcc7";
0645 nvidia,function = "pcie";
0646 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0647 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0648 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0649 };
0650 /* LAN i210/i211 SMB_ALERT_N (On-module) */
0651 sys-clk-req-pz5 {
0652 nvidia,pins = "sys_clk_req_pz5";
0653 nvidia,function = "rsvd2";
0654 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0655 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0656 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0657 };
0658
0659 /* LVDS Transceiver Configuration */
0660 pbb0 {
0661 nvidia,pins = "pbb0",
0662 "pbb7",
0663 "pcc1",
0664 "pcc2";
0665 nvidia,function = "rsvd2";
0666 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0667 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0668 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0669 };
0670 pbb3 {
0671 nvidia,pins = "pbb3",
0672 "pbb4",
0673 "pbb5",
0674 "pbb6";
0675 nvidia,function = "displayb";
0676 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0677 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0678 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0679 };
0680
0681 /* Not connected and therefore disabled */
0682 clk-32k-out-pa0 {
0683 nvidia,pins = "clk3_out_pee0",
0684 "clk3_req_pee1",
0685 "clk_32k_out_pa0",
0686 "dap4_din_pp5",
0687 "dap4_dout_pp6",
0688 "dap4_fs_pp4",
0689 "dap4_sclk_pp7";
0690 nvidia,function = "rsvd2";
0691 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0692 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0693 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0694 };
0695 dap2-fs-pa2 {
0696 nvidia,pins = "dap2_fs_pa2",
0697 "dap2_sclk_pa3",
0698 "dap2_din_pa4",
0699 "dap2_dout_pa5",
0700 "lcd_dc0_pn6",
0701 "lcd_m1_pw1",
0702 "lcd_pwr1_pc1",
0703 "pex_l1_clkreq_n_pdd6",
0704 "pex_l1_prsnt_n_pdd4",
0705 "pex_l1_rst_n_pdd5";
0706 nvidia,function = "rsvd3";
0707 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0708 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0709 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0710 };
0711 gmi-ad0-pg0 {
0712 nvidia,pins = "gmi_ad0_pg0",
0713 "gmi_ad2_pg2",
0714 "gmi_ad3_pg3",
0715 "gmi_ad4_pg4",
0716 "gmi_ad5_pg5",
0717 "gmi_ad6_pg6",
0718 "gmi_ad7_pg7",
0719 "gmi_ad8_ph0",
0720 "gmi_ad9_ph1",
0721 "gmi_ad10_ph2",
0722 "gmi_ad11_ph3",
0723 "gmi_ad12_ph4",
0724 "gmi_ad13_ph5",
0725 "gmi_ad14_ph6",
0726 "gmi_ad15_ph7",
0727 "gmi_adv_n_pk0",
0728 "gmi_clk_pk1",
0729 "gmi_cs4_n_pk2",
0730 "gmi_cs2_n_pk3",
0731 "gmi_dqs_pi2",
0732 "gmi_iordy_pi5",
0733 "gmi_oe_n_pi1",
0734 "gmi_wait_pi7",
0735 "gmi_wr_n_pi0",
0736 "lcd_cs1_n_pw0",
0737 "pu0",
0738 "pu1",
0739 "pu2";
0740 nvidia,function = "rsvd4";
0741 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0742 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0743 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0744 };
0745 gmi-cs0-n-pj0 {
0746 nvidia,pins = "gmi_cs0_n_pj0",
0747 "gmi_cs1_n_pj2",
0748 "gmi_cs3_n_pk4";
0749 nvidia,function = "rsvd1";
0750 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0751 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0752 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0753 };
0754 gmi-cs6-n-pi3 {
0755 nvidia,pins = "gmi_cs6_n_pi3";
0756 nvidia,function = "sata";
0757 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0758 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0759 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0760 };
0761 gmi-cs7-n-pi6 {
0762 nvidia,pins = "gmi_cs7_n_pi6";
0763 nvidia,function = "gmi_alt";
0764 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0765 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0766 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0767 };
0768 lcd-pwr0-pb2 {
0769 nvidia,pins = "lcd_pwr0_pb2",
0770 "lcd_pwr2_pc6",
0771 "lcd_wr_n_pz3";
0772 nvidia,function = "hdcp";
0773 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0774 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0775 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0776 };
0777 uart2-cts-n-pj5 {
0778 nvidia,pins = "uart2_cts_n_pj5",
0779 "uart2_rts_n_pj6";
0780 nvidia,function = "gmi";
0781 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0782 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0783 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0784 };
0785
0786 /* Power I2C (On-module) */
0787 pwr-i2c-scl-pz6 {
0788 nvidia,pins = "pwr_i2c_scl_pz6",
0789 "pwr_i2c_sda_pz7";
0790 nvidia,function = "i2cpwr";
0791 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0792 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0793 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0794 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
0795 };
0796
0797 /*
0798 * THERMD_ALERT#, unlatched I2C address pin of LM95245
0799 * temperature sensor therefore requires disabling for
0800 * now
0801 */
0802 lcd-dc1-pd2 {
0803 nvidia,pins = "lcd_dc1_pd2";
0804 nvidia,function = "rsvd3";
0805 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0806 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0807 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
0808 };
0809
0810 /* TOUCH_PEN_INT# (On-module) */
0811 pv0 {
0812 nvidia,pins = "pv0";
0813 nvidia,function = "rsvd1";
0814 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0815 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0816 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
0817 };
0818 };
0819 };
0820
0821 serial@70006040 {
0822 compatible = "nvidia,tegra30-hsuart";
0823 /delete-property/ reg-shift;
0824 };
0825
0826 serial@70006200 {
0827 compatible = "nvidia,tegra30-hsuart";
0828 /delete-property/ reg-shift;
0829 };
0830
0831 serial@70006300 {
0832 compatible = "nvidia,tegra30-hsuart";
0833 /delete-property/ reg-shift;
0834 };
0835
0836 hdmi_ddc: i2c@7000c700 {
0837 clock-frequency = <10000>;
0838 };
0839
0840 /*
0841 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
0842 * touch screen controller
0843 */
0844 i2c@7000d000 {
0845 status = "okay";
0846 clock-frequency = <100000>;
0847
0848 /* SGTL5000 audio codec */
0849 sgtl5000: codec@a {
0850 compatible = "fsl,sgtl5000";
0851 reg = <0x0a>;
0852 #sound-dai-cells = <0>;
0853 VDDA-supply = <®_module_3v3_audio>;
0854 VDDD-supply = <®_1v8_vio>;
0855 VDDIO-supply = <®_module_3v3>;
0856 clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
0857 };
0858
0859 pmic: pmic@2d {
0860 compatible = "ti,tps65911";
0861 reg = <0x2d>;
0862
0863 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0864 #interrupt-cells = <2>;
0865 interrupt-controller;
0866 wakeup-source;
0867
0868 ti,system-power-controller;
0869
0870 #gpio-cells = <2>;
0871 gpio-controller;
0872
0873 vcc1-supply = <®_module_3v3>;
0874 vcc2-supply = <®_module_3v3>;
0875 vcc3-supply = <®_1v8_vio>;
0876 vcc4-supply = <®_module_3v3>;
0877 vcc5-supply = <®_module_3v3>;
0878 vcc6-supply = <®_1v8_vio>;
0879 vcc7-supply = <®_5v0_charge_pump>;
0880 vccio-supply = <®_module_3v3>;
0881
0882 regulators {
0883 vdd1_reg: vdd1 {
0884 regulator-name = "+V1.35_VDDIO_DDR";
0885 regulator-min-microvolt = <1350000>;
0886 regulator-max-microvolt = <1350000>;
0887 regulator-always-on;
0888 };
0889
0890 vdd2_reg: vdd2 {
0891 regulator-name = "+V1.05";
0892 regulator-min-microvolt = <1050000>;
0893 regulator-max-microvolt = <1050000>;
0894 };
0895
0896 vddctrl_reg: vddctrl {
0897 regulator-name = "+V1.0_VDD_CPU";
0898 regulator-min-microvolt = <1150000>;
0899 regulator-max-microvolt = <1150000>;
0900 regulator-always-on;
0901 };
0902
0903 reg_1v8_vio: vio {
0904 regulator-name = "+V1.8";
0905 regulator-min-microvolt = <1800000>;
0906 regulator-max-microvolt = <1800000>;
0907 regulator-always-on;
0908 };
0909
0910 /* LDO1: unused */
0911
0912 /*
0913 * EN_+V3.3 switching via FET:
0914 * +V3.3_AUDIO_AVDD_S, +V3.3
0915 * see also +V3.3 fixed supply
0916 */
0917 ldo2_reg: ldo2 {
0918 regulator-name = "EN_+V3.3";
0919 regulator-min-microvolt = <3300000>;
0920 regulator-max-microvolt = <3300000>;
0921 regulator-always-on;
0922 };
0923
0924 ldo3_reg: ldo3 {
0925 regulator-name = "+V1.2_CSI";
0926 regulator-min-microvolt = <1200000>;
0927 regulator-max-microvolt = <1200000>;
0928 };
0929
0930 ldo4_reg: ldo4 {
0931 regulator-name = "+V1.2_VDD_RTC";
0932 regulator-min-microvolt = <1200000>;
0933 regulator-max-microvolt = <1200000>;
0934 regulator-always-on;
0935 };
0936
0937 /*
0938 * +V2.8_AVDD_VDAC:
0939 * only required for (unsupported) analog RGB
0940 */
0941 ldo5_reg: ldo5 {
0942 regulator-name = "+V2.8_AVDD_VDAC";
0943 regulator-min-microvolt = <2800000>;
0944 regulator-max-microvolt = <2800000>;
0945 regulator-always-on;
0946 };
0947
0948 /*
0949 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
0950 * but LDO6 can't set voltage in 50mV
0951 * granularity
0952 */
0953 ldo6_reg: ldo6 {
0954 regulator-name = "+V1.05_AVDD_PLLE";
0955 regulator-min-microvolt = <1100000>;
0956 regulator-max-microvolt = <1100000>;
0957 };
0958
0959 ldo7_reg: ldo7 {
0960 regulator-name = "+V1.2_AVDD_PLL";
0961 regulator-min-microvolt = <1200000>;
0962 regulator-max-microvolt = <1200000>;
0963 regulator-always-on;
0964 };
0965
0966 ldo8_reg: ldo8 {
0967 regulator-name = "+V1.0_VDD_DDR_HS";
0968 regulator-min-microvolt = <1000000>;
0969 regulator-max-microvolt = <1000000>;
0970 regulator-always-on;
0971 };
0972 };
0973 };
0974
0975 /* STMPE811 touch screen controller */
0976 touchscreen@41 {
0977 compatible = "st,stmpe811";
0978 reg = <0x41>;
0979 irq-gpio = <&gpio TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
0980 interrupt-controller;
0981 id = <0>;
0982 blocks = <0x5>;
0983 irq-trigger = <0x1>;
0984 /* 3.25 MHz ADC clock speed */
0985 st,adc-freq = <1>;
0986 /* 12-bit ADC */
0987 st,mod-12b = <1>;
0988 /* internal ADC reference */
0989 st,ref-sel = <0>;
0990 /* ADC converstion time: 80 clocks */
0991 st,sample-time = <4>;
0992
0993 stmpe_touchscreen {
0994 compatible = "st,stmpe-ts";
0995 /* 8 sample average control */
0996 st,ave-ctrl = <3>;
0997 /* 7 length fractional part in z */
0998 st,fraction-z = <7>;
0999 /*
1000 * 50 mA typical 80 mA max touchscreen drivers
1001 * current limit value
1002 */
1003 st,i-drive = <1>;
1004 /* 1 ms panel driver settling time */
1005 st,settling = <3>;
1006 /* 5 ms touch detect interrupt delay */
1007 st,touch-det-delay = <5>;
1008 };
1009
1010 stmpe_adc {
1011 compatible = "st,stmpe-adc";
1012 /* forbid to use ADC channels 3-0 (touch) */
1013 st,norequest-mask = <0x0F>;
1014 };
1015 };
1016
1017 /*
1018 * LM95245 temperature sensor
1019 * Note: OVERT1# directly connected to TPS65911 PMIC PWRDN
1020 */
1021 temp-sensor@4c {
1022 compatible = "national,lm95245";
1023 reg = <0x4c>;
1024 };
1025
1026 /* SW: +V1.2_VDD_CORE */
1027 regulator@60 {
1028 compatible = "ti,tps62362";
1029 reg = <0x60>;
1030
1031 regulator-name = "tps62362-vout";
1032 regulator-min-microvolt = <900000>;
1033 regulator-max-microvolt = <1400000>;
1034 regulator-boot-on;
1035 regulator-always-on;
1036 };
1037 };
1038
1039 /* SPI4: CAN2 */
1040 spi@7000da00 {
1041 status = "okay";
1042 spi-max-frequency = <10000000>;
1043
1044 can@1 {
1045 compatible = "microchip,mcp2515";
1046 reg = <1>;
1047 clocks = <&clk16m>;
1048 interrupt-parent = <&gpio>;
1049 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_FALLING>;
1050 spi-max-frequency = <10000000>;
1051 };
1052 };
1053
1054 /* SPI6: CAN1 */
1055 spi@7000de00 {
1056 status = "okay";
1057 spi-max-frequency = <10000000>;
1058
1059 can@0 {
1060 compatible = "microchip,mcp2515";
1061 reg = <0>;
1062 clocks = <&clk16m>;
1063 interrupt-parent = <&gpio>;
1064 interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_FALLING>;
1065 spi-max-frequency = <10000000>;
1066 };
1067 };
1068
1069 pmc@7000e400 {
1070 nvidia,invert-interrupt;
1071 nvidia,suspend-mode = <1>;
1072 nvidia,cpu-pwr-good-time = <5000>;
1073 nvidia,cpu-pwr-off-time = <5000>;
1074 nvidia,core-pwr-good-time = <3845 3845>;
1075 nvidia,core-pwr-off-time = <0>;
1076 nvidia,core-power-req-active-high;
1077 nvidia,sys-clock-req-active-high;
1078
1079 /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */
1080 i2c-thermtrip {
1081 nvidia,i2c-controller-id = <4>;
1082 nvidia,bus-addr = <0x2d>;
1083 nvidia,reg-addr = <0x3f>;
1084 nvidia,reg-data = <0x1>;
1085 };
1086 };
1087
1088 hda@70030000 {
1089 status = "okay";
1090 };
1091
1092 ahub@70080000 {
1093 i2s@70080500 {
1094 status = "okay";
1095 };
1096 };
1097
1098 /* eMMC */
1099 mmc@78000600 {
1100 status = "okay";
1101 bus-width = <8>;
1102 non-removable;
1103 vmmc-supply = <®_module_3v3>; /* VCC */
1104 vqmmc-supply = <®_1v8_vio>; /* VCCQ */
1105 mmc-ddr-1_8v;
1106 };
1107
1108 clk32k_in: xtal1 {
1109 compatible = "fixed-clock";
1110 #clock-cells = <0>;
1111 clock-frequency = <32768>;
1112 };
1113
1114 clk16m: osc4 {
1115 compatible = "fixed-clock";
1116 #clock-cells = <0>;
1117 clock-frequency = <16000000>;
1118 };
1119
1120 reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll {
1121 compatible = "regulator-fixed";
1122 regulator-name = "+V1.8_AVDD_HDMI_PLL";
1123 regulator-min-microvolt = <1800000>;
1124 regulator-max-microvolt = <1800000>;
1125 enable-active-high;
1126 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1127 vin-supply = <®_1v8_vio>;
1128 };
1129
1130 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
1131 compatible = "regulator-fixed";
1132 regulator-name = "+V3.3_AVDD_HDMI";
1133 regulator-min-microvolt = <3300000>;
1134 regulator-max-microvolt = <3300000>;
1135 enable-active-high;
1136 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1137 vin-supply = <®_module_3v3>;
1138 };
1139
1140 reg_5v0_charge_pump: regulator-5v0-charge-pump {
1141 compatible = "regulator-fixed";
1142 regulator-name = "+V5.0";
1143 regulator-min-microvolt = <5000000>;
1144 regulator-max-microvolt = <5000000>;
1145 regulator-always-on;
1146 };
1147
1148 reg_module_3v3: regulator-module-3v3 {
1149 compatible = "regulator-fixed";
1150 regulator-name = "+V3.3";
1151 regulator-min-microvolt = <3300000>;
1152 regulator-max-microvolt = <3300000>;
1153 regulator-always-on;
1154 };
1155
1156 reg_module_3v3_audio: regulator-module-3v3-audio {
1157 compatible = "regulator-fixed";
1158 regulator-name = "+V3.3_AUDIO_AVDD_S";
1159 regulator-min-microvolt = <3300000>;
1160 regulator-max-microvolt = <3300000>;
1161 regulator-always-on;
1162 };
1163
1164 sound {
1165 compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
1166 "nvidia,tegra-audio-sgtl5000";
1167 nvidia,model = "Toradex Apalis T30";
1168 nvidia,audio-routing =
1169 "Headphone Jack", "HP_OUT",
1170 "LINE_IN", "Line In Jack",
1171 "MIC_IN", "Mic Jack";
1172 nvidia,i2s-controller = <&tegra_i2s2>;
1173 nvidia,audio-codec = <&sgtl5000>;
1174 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
1175 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1176 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1177 clock-names = "pll_a", "pll_a_out0", "mclk";
1178
1179 assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
1180 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1181
1182 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1183 <&tegra_car TEGRA30_CLK_EXTERN1>;
1184 };
1185 };
