0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <dt-bindings/clock/tegra20-car.h>
0003 #include <dt-bindings/gpio/tegra-gpio.h>
0004 #include <dt-bindings/memory/tegra20-mc.h>
0005 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
0006 #include <dt-bindings/interrupt-controller/arm-gic.h>
0007 #include <dt-bindings/soc/tegra-pmc.h>
0008
0009 #include "tegra20-peripherals-opp.dtsi"
0010
0011 / {
0012 compatible = "nvidia,tegra20";
0013 interrupt-parent = <&lic>;
0014 #address-cells = <1>;
0015 #size-cells = <1>;
0016
0017 memory@0 {
0018 device_type = "memory";
0019 reg = <0 0>;
0020 };
0021
0022 sram@40000000 {
0023 compatible = "mmio-sram";
0024 reg = <0x40000000 0x40000>;
0025 #address-cells = <1>;
0026 #size-cells = <1>;
0027 ranges = <0 0x40000000 0x40000>;
0028
0029 vde_pool: sram@400 {
0030 reg = <0x400 0x3fc00>;
0031 pool;
0032 };
0033 };
0034
0035 host1x@50000000 {
0036 compatible = "nvidia,tegra20-host1x";
0037 reg = <0x50000000 0x00024000>;
0038 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
0039 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
0040 interrupt-names = "syncpt", "host1x";
0041 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
0042 clock-names = "host1x";
0043 resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>;
0044 reset-names = "host1x", "mc";
0045 power-domains = <&pd_core>;
0046 operating-points-v2 = <&host1x_dvfs_opp_table>;
0047
0048 #address-cells = <1>;
0049 #size-cells = <1>;
0050
0051 ranges = <0x54000000 0x54000000 0x04000000>;
0052
0053 mpe@54040000 {
0054 compatible = "nvidia,tegra20-mpe";
0055 reg = <0x54040000 0x00040000>;
0056 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
0057 clocks = <&tegra_car TEGRA20_CLK_MPE>;
0058 resets = <&tegra_car 60>;
0059 reset-names = "mpe";
0060 power-domains = <&pd_mpe>;
0061 operating-points-v2 = <&mpe_dvfs_opp_table>;
0062 status = "disabled";
0063 };
0064
0065 vi@54080000 {
0066 compatible = "nvidia,tegra20-vi";
0067 reg = <0x54080000 0x00040000>;
0068 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0069 clocks = <&tegra_car TEGRA20_CLK_VI>;
0070 resets = <&tegra_car 20>;
0071 reset-names = "vi";
0072 power-domains = <&pd_venc>;
0073 operating-points-v2 = <&vi_dvfs_opp_table>;
0074 status = "disabled";
0075 };
0076
0077 epp@540c0000 {
0078 compatible = "nvidia,tegra20-epp";
0079 reg = <0x540c0000 0x00040000>;
0080 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
0081 clocks = <&tegra_car TEGRA20_CLK_EPP>;
0082 resets = <&tegra_car 19>;
0083 reset-names = "epp";
0084 power-domains = <&pd_core>;
0085 operating-points-v2 = <&epp_dvfs_opp_table>;
0086 status = "disabled";
0087 };
0088
0089 isp@54100000 {
0090 compatible = "nvidia,tegra20-isp";
0091 reg = <0x54100000 0x00040000>;
0092 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0093 clocks = <&tegra_car TEGRA20_CLK_ISP>;
0094 resets = <&tegra_car 23>;
0095 reset-names = "isp";
0096 power-domains = <&pd_venc>;
0097 status = "disabled";
0098 };
0099
0100 gr2d@54140000 {
0101 compatible = "nvidia,tegra20-gr2d";
0102 reg = <0x54140000 0x00040000>;
0103 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0104 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
0105 resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
0106 reset-names = "2d", "mc";
0107 power-domains = <&pd_core>;
0108 operating-points-v2 = <&gr2d_dvfs_opp_table>;
0109 };
0110
0111 gr3d@54180000 {
0112 compatible = "nvidia,tegra20-gr3d";
0113 reg = <0x54180000 0x00040000>;
0114 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
0115 resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
0116 reset-names = "3d", "mc";
0117 power-domains = <&pd_3d>;
0118 operating-points-v2 = <&gr3d_dvfs_opp_table>;
0119 };
0120
0121 dc@54200000 {
0122 compatible = "nvidia,tegra20-dc";
0123 reg = <0x54200000 0x00040000>;
0124 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0125 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
0126 <&tegra_car TEGRA20_CLK_PLL_P>;
0127 clock-names = "dc", "parent";
0128 resets = <&tegra_car 27>;
0129 reset-names = "dc";
0130 power-domains = <&pd_core>;
0131 operating-points-v2 = <&disp1_dvfs_opp_table>;
0132
0133 nvidia,head = <0>;
0134
0135 interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>,
0136 <&mc TEGRA20_MC_DISPLAY0B &emc>,
0137 <&mc TEGRA20_MC_DISPLAY1B &emc>,
0138 <&mc TEGRA20_MC_DISPLAY0C &emc>,
0139 <&mc TEGRA20_MC_DISPLAYHC &emc>;
0140 interconnect-names = "wina",
0141 "winb",
0142 "winb-vfilter",
0143 "winc",
0144 "cursor";
0145
0146 rgb {
0147 status = "disabled";
0148 };
0149 };
0150
0151 dc@54240000 {
0152 compatible = "nvidia,tegra20-dc";
0153 reg = <0x54240000 0x00040000>;
0154 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0155 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
0156 <&tegra_car TEGRA20_CLK_PLL_P>;
0157 clock-names = "dc", "parent";
0158 resets = <&tegra_car 26>;
0159 reset-names = "dc";
0160 power-domains = <&pd_core>;
0161 operating-points-v2 = <&disp2_dvfs_opp_table>;
0162
0163 nvidia,head = <1>;
0164
0165 interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>,
0166 <&mc TEGRA20_MC_DISPLAY0BB &emc>,
0167 <&mc TEGRA20_MC_DISPLAY1BB &emc>,
0168 <&mc TEGRA20_MC_DISPLAY0CB &emc>,
0169 <&mc TEGRA20_MC_DISPLAYHCB &emc>;
0170 interconnect-names = "wina",
0171 "winb",
0172 "winb-vfilter",
0173 "winc",
0174 "cursor";
0175
0176 rgb {
0177 status = "disabled";
0178 };
0179 };
0180
0181 tegra_hdmi: hdmi@54280000 {
0182 compatible = "nvidia,tegra20-hdmi";
0183 reg = <0x54280000 0x00040000>;
0184 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0185 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
0186 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
0187 clock-names = "hdmi", "parent";
0188 resets = <&tegra_car 51>;
0189 reset-names = "hdmi";
0190 power-domains = <&pd_core>;
0191 operating-points-v2 = <&hdmi_dvfs_opp_table>;
0192 #sound-dai-cells = <0>;
0193 status = "disabled";
0194 };
0195
0196 tvo@542c0000 {
0197 compatible = "nvidia,tegra20-tvo";
0198 reg = <0x542c0000 0x00040000>;
0199 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0200 clocks = <&tegra_car TEGRA20_CLK_TVO>;
0201 power-domains = <&pd_core>;
0202 operating-points-v2 = <&tvo_dvfs_opp_table>;
0203 status = "disabled";
0204 };
0205
0206 dsi@54300000 {
0207 compatible = "nvidia,tegra20-dsi";
0208 reg = <0x54300000 0x00040000>;
0209 clocks = <&tegra_car TEGRA20_CLK_DSI>,
0210 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
0211 clock-names = "dsi", "parent";
0212 resets = <&tegra_car 48>;
0213 reset-names = "dsi";
0214 power-domains = <&pd_core>;
0215 operating-points-v2 = <&dsi_dvfs_opp_table>;
0216 status = "disabled";
0217 };
0218 };
0219
0220 timer@50040600 {
0221 compatible = "arm,cortex-a9-twd-timer";
0222 interrupt-parent = <&intc>;
0223 reg = <0x50040600 0x20>;
0224 interrupts = <GIC_PPI 13
0225 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
0226 clocks = <&tegra_car TEGRA20_CLK_TWD>;
0227 };
0228
0229 intc: interrupt-controller@50041000 {
0230 compatible = "arm,cortex-a9-gic";
0231 reg = <0x50041000 0x1000>,
0232 <0x50040100 0x0100>;
0233 interrupt-controller;
0234 #interrupt-cells = <3>;
0235 interrupt-parent = <&intc>;
0236 };
0237
0238 cache-controller@50043000 {
0239 compatible = "arm,pl310-cache";
0240 reg = <0x50043000 0x1000>;
0241 arm,data-latency = <5 5 2>;
0242 arm,tag-latency = <4 4 2>;
0243 cache-unified;
0244 cache-level = <2>;
0245 };
0246
0247 lic: interrupt-controller@60004000 {
0248 compatible = "nvidia,tegra20-ictlr";
0249 reg = <0x60004000 0x100>,
0250 <0x60004100 0x50>,
0251 <0x60004200 0x50>,
0252 <0x60004300 0x50>;
0253 interrupt-controller;
0254 #interrupt-cells = <3>;
0255 interrupt-parent = <&intc>;
0256 };
0257
0258 timer@60005000 {
0259 compatible = "nvidia,tegra20-timer";
0260 reg = <0x60005000 0x60>;
0261 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0262 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0263 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
0264 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0265 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
0266 };
0267
0268 tegra_car: clock@60006000 {
0269 compatible = "nvidia,tegra20-car";
0270 reg = <0x60006000 0x1000>;
0271 #clock-cells = <1>;
0272 #reset-cells = <1>;
0273
0274 sclk {
0275 compatible = "nvidia,tegra20-sclk";
0276 clocks = <&tegra_car TEGRA20_CLK_SCLK>;
0277 power-domains = <&pd_core>;
0278 operating-points-v2 = <&sclk_dvfs_opp_table>;
0279 };
0280 };
0281
0282 flow-controller@60007000 {
0283 compatible = "nvidia,tegra20-flowctrl";
0284 reg = <0x60007000 0x1000>;
0285 };
0286
0287 apbdma: dma@6000a000 {
0288 compatible = "nvidia,tegra20-apbdma";
0289 reg = <0x6000a000 0x1200>;
0290 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0291 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
0292 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
0293 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
0294 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
0295 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
0296 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
0297 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
0298 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
0299 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
0300 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
0301 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
0302 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
0303 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
0304 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
0305 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
0306 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
0307 resets = <&tegra_car 34>;
0308 reset-names = "dma";
0309 #dma-cells = <1>;
0310 };
0311
0312 ahb@6000c000 {
0313 compatible = "nvidia,tegra20-ahb";
0314 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
0315 };
0316
0317 gpio: gpio@6000d000 {
0318 compatible = "nvidia,tegra20-gpio";
0319 reg = <0x6000d000 0x1000>;
0320 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
0321 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
0322 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
0323 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
0324 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
0325 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0326 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0327 #gpio-cells = <2>;
0328 gpio-controller;
0329 #interrupt-cells = <2>;
0330 interrupt-controller;
0331 gpio-ranges = <&pinmux 0 0 224>;
0332 };
0333
0334 vde@6001a000 {
0335 compatible = "nvidia,tegra20-vde";
0336 reg = <0x6001a000 0x1000>, /* Syntax Engine */
0337 <0x6001b000 0x1000>, /* Video Bitstream Engine */
0338 <0x6001c000 0x100>, /* Macroblock Engine */
0339 <0x6001c200 0x100>, /* Post-processing Engine */
0340 <0x6001c400 0x100>, /* Motion Compensation Engine */
0341 <0x6001c600 0x100>, /* Transform Engine */
0342 <0x6001c800 0x100>, /* Pixel prediction block */
0343 <0x6001ca00 0x100>, /* Video DMA */
0344 <0x6001d800 0x300>; /* Video frame controls */
0345 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
0346 "tfe", "ppb", "vdma", "frameid";
0347 iram = <&vde_pool>; /* IRAM region */
0348 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
0349 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
0350 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
0351 interrupt-names = "sync-token", "bsev", "sxe";
0352 clocks = <&tegra_car TEGRA20_CLK_VDE>;
0353 reset-names = "vde", "mc";
0354 resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>;
0355 power-domains = <&pd_vde>;
0356 operating-points-v2 = <&vde_dvfs_opp_table>;
0357 };
0358
0359 apbmisc@70000800 {
0360 compatible = "nvidia,tegra20-apbmisc";
0361 reg = <0x70000800 0x64>, /* Chip revision */
0362 <0x70000008 0x04>; /* Strapping options */
0363 };
0364
0365 pinmux: pinmux@70000014 {
0366 compatible = "nvidia,tegra20-pinmux";
0367 reg = <0x70000014 0x10>, /* Tri-state registers */
0368 <0x70000080 0x20>, /* Mux registers */
0369 <0x700000a0 0x14>, /* Pull-up/down registers */
0370 <0x70000868 0xa8>; /* Pad control registers */
0371 };
0372
0373 das@70000c00 {
0374 compatible = "nvidia,tegra20-das";
0375 reg = <0x70000c00 0x80>;
0376 };
0377
0378 tegra_ac97: ac97@70002000 {
0379 compatible = "nvidia,tegra20-ac97";
0380 reg = <0x70002000 0x200>;
0381 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
0382 clocks = <&tegra_car TEGRA20_CLK_AC97>;
0383 resets = <&tegra_car 3>;
0384 reset-names = "ac97";
0385 dmas = <&apbdma 12>, <&apbdma 12>;
0386 dma-names = "rx", "tx";
0387 status = "disabled";
0388 };
0389
0390 tegra_spdif: spdif@70002400 {
0391 compatible = "nvidia,tegra20-spdif";
0392 reg = <0x70002400 0x200>;
0393 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0394 clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>,
0395 <&tegra_car TEGRA20_CLK_SPDIF_IN>;
0396 clock-names = "out", "in";
0397 resets = <&tegra_car 10>;
0398 dmas = <&apbdma 3>, <&apbdma 3>;
0399 dma-names = "rx", "tx";
0400 #sound-dai-cells = <0>;
0401 status = "disabled";
0402
0403 assigned-clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>;
0404 assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_A_OUT0>;
0405 };
0406
0407 tegra_i2s1: i2s@70002800 {
0408 compatible = "nvidia,tegra20-i2s";
0409 reg = <0x70002800 0x200>;
0410 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0411 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
0412 resets = <&tegra_car 11>;
0413 reset-names = "i2s";
0414 dmas = <&apbdma 2>, <&apbdma 2>;
0415 dma-names = "rx", "tx";
0416 status = "disabled";
0417 };
0418
0419 tegra_i2s2: i2s@70002a00 {
0420 compatible = "nvidia,tegra20-i2s";
0421 reg = <0x70002a00 0x200>;
0422 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0423 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
0424 resets = <&tegra_car 18>;
0425 reset-names = "i2s";
0426 dmas = <&apbdma 1>, <&apbdma 1>;
0427 dma-names = "rx", "tx";
0428 status = "disabled";
0429 };
0430
0431 /*
0432 * There are two serial driver i.e. 8250 based simple serial
0433 * driver and APB DMA based serial driver for higher baudrate
0434 * and performace. To enable the 8250 based driver, the compatible
0435 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
0436 * driver, the compatible is "nvidia,tegra20-hsuart".
0437 */
0438 uarta: serial@70006000 {
0439 compatible = "nvidia,tegra20-uart";
0440 reg = <0x70006000 0x40>;
0441 reg-shift = <2>;
0442 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0443 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
0444 resets = <&tegra_car 6>;
0445 reset-names = "serial";
0446 dmas = <&apbdma 8>, <&apbdma 8>;
0447 dma-names = "rx", "tx";
0448 status = "disabled";
0449 };
0450
0451 uartb: serial@70006040 {
0452 compatible = "nvidia,tegra20-uart";
0453 reg = <0x70006040 0x40>;
0454 reg-shift = <2>;
0455 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0456 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
0457 resets = <&tegra_car 7>;
0458 reset-names = "serial";
0459 dmas = <&apbdma 9>, <&apbdma 9>;
0460 dma-names = "rx", "tx";
0461 status = "disabled";
0462 };
0463
0464 uartc: serial@70006200 {
0465 compatible = "nvidia,tegra20-uart";
0466 reg = <0x70006200 0x100>;
0467 reg-shift = <2>;
0468 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0469 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
0470 resets = <&tegra_car 55>;
0471 reset-names = "serial";
0472 dmas = <&apbdma 10>, <&apbdma 10>;
0473 dma-names = "rx", "tx";
0474 status = "disabled";
0475 };
0476
0477 uartd: serial@70006300 {
0478 compatible = "nvidia,tegra20-uart";
0479 reg = <0x70006300 0x100>;
0480 reg-shift = <2>;
0481 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0482 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
0483 resets = <&tegra_car 65>;
0484 reset-names = "serial";
0485 dmas = <&apbdma 19>, <&apbdma 19>;
0486 dma-names = "rx", "tx";
0487 status = "disabled";
0488 };
0489
0490 uarte: serial@70006400 {
0491 compatible = "nvidia,tegra20-uart";
0492 reg = <0x70006400 0x100>;
0493 reg-shift = <2>;
0494 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0495 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
0496 resets = <&tegra_car 66>;
0497 reset-names = "serial";
0498 dmas = <&apbdma 20>, <&apbdma 20>;
0499 dma-names = "rx", "tx";
0500 status = "disabled";
0501 };
0502
0503 nand-controller@70008000 {
0504 compatible = "nvidia,tegra20-nand";
0505 reg = <0x70008000 0x100>;
0506 #address-cells = <1>;
0507 #size-cells = <0>;
0508 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0509 clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
0510 clock-names = "nand";
0511 resets = <&tegra_car 13>;
0512 reset-names = "nand";
0513 assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
0514 assigned-clock-rates = <150000000>;
0515 power-domains = <&pd_core>;
0516 operating-points-v2 = <&ndflash_dvfs_opp_table>;
0517 status = "disabled";
0518 };
0519
0520 gmi@70009000 {
0521 compatible = "nvidia,tegra20-gmi";
0522 reg = <0x70009000 0x1000>;
0523 #address-cells = <2>;
0524 #size-cells = <1>;
0525 ranges = <0 0 0xd0000000 0xfffffff>;
0526 clocks = <&tegra_car TEGRA20_CLK_NOR>;
0527 clock-names = "gmi";
0528 resets = <&tegra_car 42>;
0529 reset-names = "gmi";
0530 power-domains = <&pd_core>;
0531 operating-points-v2 = <&nor_dvfs_opp_table>;
0532 status = "disabled";
0533 };
0534
0535 pwm: pwm@7000a000 {
0536 compatible = "nvidia,tegra20-pwm";
0537 reg = <0x7000a000 0x100>;
0538 #pwm-cells = <2>;
0539 clocks = <&tegra_car TEGRA20_CLK_PWM>;
0540 resets = <&tegra_car 17>;
0541 reset-names = "pwm";
0542 status = "disabled";
0543 };
0544
0545 rtc@7000e000 {
0546 compatible = "nvidia,tegra20-rtc";
0547 reg = <0x7000e000 0x100>;
0548 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0549 clocks = <&tegra_car TEGRA20_CLK_RTC>;
0550 };
0551
0552 i2c@7000c000 {
0553 compatible = "nvidia,tegra20-i2c";
0554 reg = <0x7000c000 0x100>;
0555 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0556 #address-cells = <1>;
0557 #size-cells = <0>;
0558 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
0559 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
0560 clock-names = "div-clk", "fast-clk";
0561 resets = <&tegra_car 12>;
0562 reset-names = "i2c";
0563 dmas = <&apbdma 21>, <&apbdma 21>;
0564 dma-names = "rx", "tx";
0565 status = "disabled";
0566 };
0567
0568 spi@7000c380 {
0569 compatible = "nvidia,tegra20-sflash";
0570 reg = <0x7000c380 0x80>;
0571 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
0572 #address-cells = <1>;
0573 #size-cells = <0>;
0574 clocks = <&tegra_car TEGRA20_CLK_SPI>;
0575 resets = <&tegra_car 43>;
0576 reset-names = "spi";
0577 dmas = <&apbdma 11>, <&apbdma 11>;
0578 dma-names = "rx", "tx";
0579 status = "disabled";
0580 };
0581
0582 i2c2: i2c@7000c400 {
0583 compatible = "nvidia,tegra20-i2c";
0584 reg = <0x7000c400 0x100>;
0585 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0586 #address-cells = <1>;
0587 #size-cells = <0>;
0588 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
0589 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
0590 clock-names = "div-clk", "fast-clk";
0591 resets = <&tegra_car 54>;
0592 reset-names = "i2c";
0593 dmas = <&apbdma 22>, <&apbdma 22>;
0594 dma-names = "rx", "tx";
0595 status = "disabled";
0596 };
0597
0598 i2c@7000c500 {
0599 compatible = "nvidia,tegra20-i2c";
0600 reg = <0x7000c500 0x100>;
0601 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0602 #address-cells = <1>;
0603 #size-cells = <0>;
0604 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
0605 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
0606 clock-names = "div-clk", "fast-clk";
0607 resets = <&tegra_car 67>;
0608 reset-names = "i2c";
0609 dmas = <&apbdma 23>, <&apbdma 23>;
0610 dma-names = "rx", "tx";
0611 status = "disabled";
0612 };
0613
0614 i2c@7000d000 {
0615 compatible = "nvidia,tegra20-i2c-dvc";
0616 reg = <0x7000d000 0x200>;
0617 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
0618 #address-cells = <1>;
0619 #size-cells = <0>;
0620 clocks = <&tegra_car TEGRA20_CLK_DVC>,
0621 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
0622 clock-names = "div-clk", "fast-clk";
0623 resets = <&tegra_car 47>;
0624 reset-names = "i2c";
0625 dmas = <&apbdma 24>, <&apbdma 24>;
0626 dma-names = "rx", "tx";
0627 status = "disabled";
0628 };
0629
0630 spi@7000d400 {
0631 compatible = "nvidia,tegra20-slink";
0632 reg = <0x7000d400 0x200>;
0633 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
0634 #address-cells = <1>;
0635 #size-cells = <0>;
0636 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
0637 resets = <&tegra_car 41>;
0638 reset-names = "spi";
0639 dmas = <&apbdma 15>, <&apbdma 15>;
0640 dma-names = "rx", "tx";
0641 status = "disabled";
0642 };
0643
0644 spi@7000d600 {
0645 compatible = "nvidia,tegra20-slink";
0646 reg = <0x7000d600 0x200>;
0647 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0648 #address-cells = <1>;
0649 #size-cells = <0>;
0650 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
0651 resets = <&tegra_car 44>;
0652 reset-names = "spi";
0653 dmas = <&apbdma 16>, <&apbdma 16>;
0654 dma-names = "rx", "tx";
0655 status = "disabled";
0656 };
0657
0658 spi@7000d800 {
0659 compatible = "nvidia,tegra20-slink";
0660 reg = <0x7000d800 0x200>;
0661 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0662 #address-cells = <1>;
0663 #size-cells = <0>;
0664 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
0665 resets = <&tegra_car 46>;
0666 reset-names = "spi";
0667 dmas = <&apbdma 17>, <&apbdma 17>;
0668 dma-names = "rx", "tx";
0669 status = "disabled";
0670 };
0671
0672 spi@7000da00 {
0673 compatible = "nvidia,tegra20-slink";
0674 reg = <0x7000da00 0x200>;
0675 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
0676 #address-cells = <1>;
0677 #size-cells = <0>;
0678 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
0679 resets = <&tegra_car 68>;
0680 reset-names = "spi";
0681 dmas = <&apbdma 18>, <&apbdma 18>;
0682 dma-names = "rx", "tx";
0683 status = "disabled";
0684 };
0685
0686 kbc@7000e200 {
0687 compatible = "nvidia,tegra20-kbc";
0688 reg = <0x7000e200 0x100>;
0689 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
0690 clocks = <&tegra_car TEGRA20_CLK_KBC>;
0691 resets = <&tegra_car 36>;
0692 reset-names = "kbc";
0693 status = "disabled";
0694 };
0695
0696 tegra_pmc: pmc@7000e400 {
0697 compatible = "nvidia,tegra20-pmc";
0698 reg = <0x7000e400 0x400>;
0699 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
0700 clock-names = "pclk", "clk32k_in";
0701 #clock-cells = <1>;
0702
0703 pd_core: core-domain {
0704 #power-domain-cells = <0>;
0705 operating-points-v2 = <&core_opp_table>;
0706 };
0707
0708 powergates {
0709 pd_3d: td {
0710 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
0711 resets = <&mc TEGRA20_MC_RESET_3D>,
0712 <&tegra_car TEGRA20_CLK_GR3D>;
0713 power-domains = <&pd_core>;
0714 #power-domain-cells = <0>;
0715 };
0716
0717 pd_venc: venc {
0718 clocks = <&tegra_car TEGRA20_CLK_ISP>,
0719 <&tegra_car TEGRA20_CLK_VI>,
0720 <&tegra_car TEGRA20_CLK_CSI>;
0721 resets = <&mc TEGRA20_MC_RESET_ISP>,
0722 <&mc TEGRA20_MC_RESET_VI>,
0723 <&tegra_car TEGRA20_CLK_ISP>,
0724 <&tegra_car 20 /* VI */>,
0725 <&tegra_car TEGRA20_CLK_CSI>;
0726 power-domains = <&pd_core>;
0727 #power-domain-cells = <0>;
0728 };
0729
0730 pd_vde: vdec {
0731 clocks = <&tegra_car TEGRA20_CLK_VDE>;
0732 resets = <&mc TEGRA20_MC_RESET_VDE>,
0733 <&tegra_car TEGRA20_CLK_VDE>;
0734 power-domains = <&pd_core>;
0735 #power-domain-cells = <0>;
0736 };
0737
0738 pd_mpe: mpe {
0739 clocks = <&tegra_car TEGRA20_CLK_MPE>;
0740 resets = <&mc TEGRA20_MC_RESET_MPEA>,
0741 <&mc TEGRA20_MC_RESET_MPEB>,
0742 <&mc TEGRA20_MC_RESET_MPEC>,
0743 <&tegra_car TEGRA20_CLK_MPE>;
0744 power-domains = <&pd_core>;
0745 #power-domain-cells = <0>;
0746 };
0747 };
0748 };
0749
0750 mc: memory-controller@7000f000 {
0751 compatible = "nvidia,tegra20-mc-gart";
0752 reg = <0x7000f000 0x00000400>, /* controller registers */
0753 <0x58000000 0x02000000>; /* GART aperture */
0754 clocks = <&tegra_car TEGRA20_CLK_MC>;
0755 clock-names = "mc";
0756 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0757 #reset-cells = <1>;
0758 #iommu-cells = <0>;
0759 #interconnect-cells = <1>;
0760 };
0761
0762 emc: memory-controller@7000f400 {
0763 compatible = "nvidia,tegra20-emc";
0764 reg = <0x7000f400 0x400>;
0765 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
0766 clocks = <&tegra_car TEGRA20_CLK_EMC>;
0767 power-domains = <&pd_core>;
0768 #address-cells = <1>;
0769 #size-cells = <0>;
0770 #interconnect-cells = <0>;
0771
0772 nvidia,memory-controller = <&mc>;
0773 operating-points-v2 = <&emc_icc_dvfs_opp_table>;
0774 };
0775
0776 fuse@7000f800 {
0777 compatible = "nvidia,tegra20-efuse";
0778 reg = <0x7000f800 0x400>;
0779 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
0780 clock-names = "fuse";
0781 resets = <&tegra_car 39>;
0782 reset-names = "fuse";
0783 };
0784
0785 pcie@80003000 {
0786 compatible = "nvidia,tegra20-pcie";
0787 device_type = "pci";
0788 reg = <0x80003000 0x00000800>, /* PADS registers */
0789 <0x80003800 0x00000200>, /* AFI registers */
0790 <0x90000000 0x10000000>; /* configuration space */
0791 reg-names = "pads", "afi", "cs";
0792 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
0793 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
0794 interrupt-names = "intr", "msi";
0795
0796 #interrupt-cells = <1>;
0797 interrupt-map-mask = <0 0 0 0>;
0798 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
0799
0800 bus-range = <0x00 0xff>;
0801 #address-cells = <3>;
0802 #size-cells = <2>;
0803
0804 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */
0805 <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */
0806 <0x01000000 0 0 0x82000000 0 0x00010000>, /* downstream I/O */
0807 <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */
0808 <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
0809
0810 clocks = <&tegra_car TEGRA20_CLK_PEX>,
0811 <&tegra_car TEGRA20_CLK_AFI>,
0812 <&tegra_car TEGRA20_CLK_PLL_E>;
0813 clock-names = "pex", "afi", "pll_e";
0814 resets = <&tegra_car 70>,
0815 <&tegra_car 72>,
0816 <&tegra_car 74>;
0817 reset-names = "pex", "afi", "pcie_x";
0818 power-domains = <&pd_core>;
0819 operating-points-v2 = <&pcie_dvfs_opp_table>;
0820
0821 status = "disabled";
0822
0823 pci@1,0 {
0824 device_type = "pci";
0825 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
0826 reg = <0x000800 0 0 0 0>;
0827 bus-range = <0x00 0xff>;
0828 status = "disabled";
0829
0830 #address-cells = <3>;
0831 #size-cells = <2>;
0832 ranges;
0833
0834 nvidia,num-lanes = <2>;
0835 };
0836
0837 pci@2,0 {
0838 device_type = "pci";
0839 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
0840 reg = <0x001000 0 0 0 0>;
0841 bus-range = <0x00 0xff>;
0842 status = "disabled";
0843
0844 #address-cells = <3>;
0845 #size-cells = <2>;
0846 ranges;
0847
0848 nvidia,num-lanes = <2>;
0849 };
0850 };
0851
0852 usb@c5000000 {
0853 compatible = "nvidia,tegra20-ehci";
0854 reg = <0xc5000000 0x4000>;
0855 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0856 phy_type = "utmi";
0857 clocks = <&tegra_car TEGRA20_CLK_USBD>;
0858 resets = <&tegra_car 22>;
0859 reset-names = "usb";
0860 nvidia,needs-double-reset;
0861 nvidia,phy = <&phy1>;
0862 power-domains = <&pd_core>;
0863 operating-points-v2 = <&usbd_dvfs_opp_table>;
0864 status = "disabled";
0865 };
0866
0867 phy1: usb-phy@c5000000 {
0868 compatible = "nvidia,tegra20-usb-phy";
0869 reg = <0xc5000000 0x4000>,
0870 <0xc5000000 0x4000>;
0871 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0872 phy_type = "utmi";
0873 clocks = <&tegra_car TEGRA20_CLK_USBD>,
0874 <&tegra_car TEGRA20_CLK_PLL_U>,
0875 <&tegra_car TEGRA20_CLK_CLK_M>,
0876 <&tegra_car TEGRA20_CLK_USBD>;
0877 clock-names = "reg", "pll_u", "timer", "utmi-pads";
0878 resets = <&tegra_car 22>, <&tegra_car 22>;
0879 reset-names = "usb", "utmi-pads";
0880 #phy-cells = <0>;
0881 nvidia,has-legacy-mode;
0882 nvidia,hssync-start-delay = <9>;
0883 nvidia,idle-wait-delay = <17>;
0884 nvidia,elastic-limit = <16>;
0885 nvidia,term-range-adj = <6>;
0886 nvidia,xcvr-setup = <9>;
0887 nvidia,xcvr-lsfslew = <1>;
0888 nvidia,xcvr-lsrslew = <1>;
0889 nvidia,has-utmi-pad-registers;
0890 nvidia,pmc = <&tegra_pmc 0>;
0891 status = "disabled";
0892 };
0893
0894 usb@c5004000 {
0895 compatible = "nvidia,tegra20-ehci";
0896 reg = <0xc5004000 0x4000>;
0897 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
0898 phy_type = "ulpi";
0899 clocks = <&tegra_car TEGRA20_CLK_USB2>;
0900 resets = <&tegra_car 58>;
0901 reset-names = "usb";
0902 nvidia,phy = <&phy2>;
0903 power-domains = <&pd_core>;
0904 operating-points-v2 = <&usb2_dvfs_opp_table>;
0905 status = "disabled";
0906 };
0907
0908 phy2: usb-phy@c5004000 {
0909 compatible = "nvidia,tegra20-usb-phy";
0910 reg = <0xc5004000 0x4000>;
0911 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
0912 phy_type = "ulpi";
0913 clocks = <&tegra_car TEGRA20_CLK_USB2>,
0914 <&tegra_car TEGRA20_CLK_PLL_U>,
0915 <&tegra_car TEGRA20_CLK_CDEV2>;
0916 clock-names = "reg", "pll_u", "ulpi-link";
0917 resets = <&tegra_car 58>, <&tegra_car 22>;
0918 reset-names = "usb", "utmi-pads";
0919 #phy-cells = <0>;
0920 nvidia,pmc = <&tegra_pmc 1>;
0921 status = "disabled";
0922 };
0923
0924 usb@c5008000 {
0925 compatible = "nvidia,tegra20-ehci";
0926 reg = <0xc5008000 0x4000>;
0927 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0928 phy_type = "utmi";
0929 clocks = <&tegra_car TEGRA20_CLK_USB3>;
0930 resets = <&tegra_car 59>;
0931 reset-names = "usb";
0932 nvidia,phy = <&phy3>;
0933 power-domains = <&pd_core>;
0934 operating-points-v2 = <&usb3_dvfs_opp_table>;
0935 status = "disabled";
0936 };
0937
0938 phy3: usb-phy@c5008000 {
0939 compatible = "nvidia,tegra20-usb-phy";
0940 reg = <0xc5008000 0x4000>,
0941 <0xc5000000 0x4000>;
0942 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0943 phy_type = "utmi";
0944 clocks = <&tegra_car TEGRA20_CLK_USB3>,
0945 <&tegra_car TEGRA20_CLK_PLL_U>,
0946 <&tegra_car TEGRA20_CLK_CLK_M>,
0947 <&tegra_car TEGRA20_CLK_USBD>;
0948 clock-names = "reg", "pll_u", "timer", "utmi-pads";
0949 resets = <&tegra_car 59>, <&tegra_car 22>;
0950 reset-names = "usb", "utmi-pads";
0951 #phy-cells = <0>;
0952 nvidia,hssync-start-delay = <9>;
0953 nvidia,idle-wait-delay = <17>;
0954 nvidia,elastic-limit = <16>;
0955 nvidia,term-range-adj = <6>;
0956 nvidia,xcvr-setup = <9>;
0957 nvidia,xcvr-lsfslew = <2>;
0958 nvidia,xcvr-lsrslew = <2>;
0959 nvidia,pmc = <&tegra_pmc 2>;
0960 status = "disabled";
0961 };
0962
0963 mmc@c8000000 {
0964 compatible = "nvidia,tegra20-sdhci";
0965 reg = <0xc8000000 0x200>;
0966 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0967 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
0968 clock-names = "sdhci";
0969 resets = <&tegra_car 14>;
0970 reset-names = "sdhci";
0971 power-domains = <&pd_core>;
0972 operating-points-v2 = <&sdmmc1_dvfs_opp_table>;
0973 status = "disabled";
0974 };
0975
0976 mmc@c8000200 {
0977 compatible = "nvidia,tegra20-sdhci";
0978 reg = <0xc8000200 0x200>;
0979 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0980 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
0981 clock-names = "sdhci";
0982 resets = <&tegra_car 9>;
0983 reset-names = "sdhci";
0984 power-domains = <&pd_core>;
0985 operating-points-v2 = <&sdmmc2_dvfs_opp_table>;
0986 status = "disabled";
0987 };
0988
0989 mmc@c8000400 {
0990 compatible = "nvidia,tegra20-sdhci";
0991 reg = <0xc8000400 0x200>;
0992 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0993 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
0994 clock-names = "sdhci";
0995 resets = <&tegra_car 69>;
0996 reset-names = "sdhci";
0997 power-domains = <&pd_core>;
0998 operating-points-v2 = <&sdmmc3_dvfs_opp_table>;
0999 status = "disabled";
1000 };
1001
1002 mmc@c8000600 {
1003 compatible = "nvidia,tegra20-sdhci";
1004 reg = <0xc8000600 0x200>;
1005 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1006 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
1007 clock-names = "sdhci";
1008 resets = <&tegra_car 15>;
1009 reset-names = "sdhci";
1010 power-domains = <&pd_core>;
1011 operating-points-v2 = <&sdmmc4_dvfs_opp_table>;
1012 status = "disabled";
1013 };
1014
1015 cpus {
1016 #address-cells = <1>;
1017 #size-cells = <0>;
1018
1019 cpu@0 {
1020 device_type = "cpu";
1021 compatible = "arm,cortex-a9";
1022 reg = <0>;
1023 clocks = <&tegra_car TEGRA20_CLK_CCLK>;
1024 };
1025
1026 cpu@1 {
1027 device_type = "cpu";
1028 compatible = "arm,cortex-a9";
1029 reg = <1>;
1030 clocks = <&tegra_car TEGRA20_CLK_CCLK>;
1031 };
1032 };
1033
1034 pmu {
1035 compatible = "arm,cortex-a9-pmu";
1036 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1038 interrupt-affinity = <&{/cpus/cpu@0}>,
1039 <&{/cpus/cpu@1}>;
1040 };
1041
1042 sound-hdmi {
1043 compatible = "simple-audio-card";
1044 simple-audio-card,name = "NVIDIA Tegra20 HDMI";
1045
1046 #address-cells = <1>;
1047 #size-cells = <0>;
1048
1049 simple-audio-card,dai-link@0 {
1050 reg = <0>;
1051
1052 cpu {
1053 sound-dai = <&tegra_spdif>;
1054 };
1055
1056 codec {
1057 sound-dai = <&tegra_hdmi>;
1058 };
1059 };
1060 };
1061 };
