0001 // SPDX-License-Identifier: GPL-2.0
0002 #include "tegra20.dtsi"
0003
0004 /*
0005 * Toradex Colibri T20 Module Device Tree
0006 * Compatible for Revisions Colibri T20 256MB V1.1B, V1.2A;
0007 * Colibri T20 256MB IT V1.2A; Colibri T20 512MB V1.1C, V1.2A;
0008 * Colibri T20 512MB IT V1.2A
0009 */
0010 / {
0011 memory@0 {
0012 /*
0013 * Set memory to 256 MB to be safe as this could be used on
0014 * 256 or 512 MB module. It is expected from bootloader
0015 * to fix this up for 512 MB version.
0016 */
0017 reg = <0x00000000 0x10000000>;
0018 };
0019
0020 host1x@50000000 {
0021 hdmi@54280000 {
0022 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
0023 nvidia,hpd-gpio =
0024 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
0025 pll-supply = <®_1v8_avdd_hdmi_pll>;
0026 vdd-supply = <®_3v3_avdd_hdmi>;
0027 };
0028 };
0029
0030 pinmux@70000014 {
0031 pinctrl-names = "default";
0032 pinctrl-0 = <&state_default>;
0033
0034 state_default: pinmux {
0035 /* Analogue Audio AC97 to WM9712 (On-module) */
0036 audio-refclk {
0037 nvidia,pins = "cdev1";
0038 nvidia,function = "plla_out";
0039 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0040 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0041 };
0042 dap3 {
0043 nvidia,pins = "dap3";
0044 nvidia,function = "dap3";
0045 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0046 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0047 };
0048
0049 /*
0050 * AC97_RESET, ULPI_RESET, AC97_INT aka WM9712 GENIRQ
0051 * (All on-module), SODIMM Pin 45 Wakeup
0052 */
0053 gpio-uac {
0054 nvidia,pins = "uac";
0055 nvidia,function = "rsvd2";
0056 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0057 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0058 };
0059
0060 /*
0061 * Buffer Enables for nPWE and RDnWR (On-module,
0062 * see GPIO hogging further down below)
0063 */
0064 gpio-pta {
0065 nvidia,pins = "pta";
0066 nvidia,function = "rsvd4";
0067 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0068 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0069 };
0070
0071 /*
0072 * CLK_32K_OUT, CORE_PWR_REQ, CPU_PWR_REQ, PWR_INT_N,
0073 * SYS_CLK_REQ (All on-module)
0074 */
0075 pmc {
0076 nvidia,pins = "pmc";
0077 nvidia,function = "pwr_on";
0078 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0079 };
0080
0081 /*
0082 * Colibri Address/Data Bus (GMI)
0083 * Note: spid and spie optionally used for SPI1
0084 */
0085 gmi {
0086 nvidia,pins = "atc", "atd", "ate", "dap1",
0087 "dap2", "dap4", "gmd", "gpu",
0088 "irrx", "irtx", "spia", "spib",
0089 "spic", "spid", "spie", "uca",
0090 "ucb";
0091 nvidia,function = "gmi";
0092 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0093 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0094 };
0095 /* Further pins may be used as GPIOs */
0096 gmi-gpio1 {
0097 nvidia,pins = "lpw0", "lsc1", "lsck", "lsda";
0098 nvidia,function = "hdmi";
0099 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0100 };
0101 gmi-gpio2 {
0102 nvidia,pins = "lcsn", "ldc", "lm0", "lsdi";
0103 nvidia,function = "rsvd4";
0104 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0105 };
0106
0107 /* Colibri BL_ON */
0108 bl-on {
0109 nvidia,pins = "dta";
0110 nvidia,function = "rsvd1";
0111 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0112 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0113 };
0114
0115 /* Colibri Backlight PWM<A>, PWM<B> */
0116 sdc {
0117 nvidia,pins = "sdc";
0118 nvidia,function = "pwm";
0119 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0120 };
0121
0122 /* Colibri DDC */
0123 ddc {
0124 nvidia,pins = "ddc";
0125 nvidia,function = "i2c2";
0126 nvidia,pull = <TEGRA_PIN_PULL_UP>;
0127 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0128 };
0129
0130 /*
0131 * Colibri EXT_IO*
0132 * Note: dtf optionally used for I2C3
0133 */
0134 ext-io {
0135 nvidia,pins = "dtf", "spdi";
0136 nvidia,function = "rsvd2";
0137 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0138 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0139 };
0140
0141 /*
0142 * Colibri Ethernet (On-module)
0143 * ULPI EHCI instance 1 USB2_DP/N -> AX88772B
0144 */
0145 ulpi {
0146 nvidia,pins = "uaa", "uab", "uda";
0147 nvidia,function = "ulpi";
0148 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0149 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0150 };
0151 ulpi-refclk {
0152 nvidia,pins = "cdev2";
0153 nvidia,function = "pllp_out4";
0154 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0155 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0156 };
0157
0158 /* Colibri HOTPLUG_DETECT (HDMI) */
0159 hotplug-detect {
0160 nvidia,pins = "hdint";
0161 nvidia,function = "hdmi";
0162 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0163 };
0164
0165 /* Colibri I2C */
0166 i2c {
0167 nvidia,pins = "rm";
0168 nvidia,function = "i2c1";
0169 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0170 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0171 };
0172
0173 /*
0174 * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
0175 * today's display need DE, disable LCD_M1
0176 */
0177 lm1 {
0178 nvidia,pins = "lm1";
0179 nvidia,function = "rsvd3";
0180 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0181 };
0182
0183 /* Colibri LCD (L_* resp. LDD<*>) */
0184 lcd {
0185 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
0186 "ld4", "ld5", "ld6", "ld7",
0187 "ld8", "ld9", "ld10", "ld11",
0188 "ld12", "ld13", "ld14", "ld15",
0189 "ld16", "ld17", "lhs", "lsc0",
0190 "lspi", "lvs";
0191 nvidia,function = "displaya";
0192 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0193 };
0194 /* Colibri LCD (Optional 24 BPP Support) */
0195 lcd-24 {
0196 nvidia,pins = "ldi", "lhp0", "lhp1", "lhp2",
0197 "lpp", "lvp1";
0198 nvidia,function = "displaya";
0199 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0200 };
0201
0202 /* Colibri MMC */
0203 mmc {
0204 nvidia,pins = "atb", "gma";
0205 nvidia,function = "sdio4";
0206 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0207 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0208 };
0209
0210 /* Colibri MMCCD */
0211 mmccd {
0212 nvidia,pins = "gmb";
0213 nvidia,function = "gmi_int";
0214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0215 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0216 };
0217
0218 /* Colibri MMC (Optional 8-bit) */
0219 mmc-8bit {
0220 nvidia,pins = "gme";
0221 nvidia,function = "sdio4";
0222 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0223 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0224 };
0225
0226 /*
0227 * Colibri Parallel Camera (Optional)
0228 * pins multiplexed with others and therefore disabled
0229 * Note: dta used for BL_ON by default
0230 */
0231 cif-mclk {
0232 nvidia,pins = "csus";
0233 nvidia,function = "vi_sensor_clk";
0234 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0235 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0236 };
0237 cif {
0238 nvidia,pins = "dtb", "dtc", "dtd";
0239 nvidia,function = "vi";
0240 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0241 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0242 };
0243
0244 /* Colibri PWM<C>, PWM<D> */
0245 sdb_sdd {
0246 nvidia,pins = "sdb", "sdd";
0247 nvidia,function = "pwm";
0248 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0249 };
0250
0251 /* Colibri SSP */
0252 ssp {
0253 nvidia,pins = "slxa", "slxc", "slxd", "slxk";
0254 nvidia,function = "spi4";
0255 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0256 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0257 };
0258
0259 /* Colibri UART-A */
0260 uart-a {
0261 nvidia,pins = "sdio1";
0262 nvidia,function = "uarta";
0263 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0264 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0265 };
0266 uart-a-dsr {
0267 nvidia,pins = "lpw1";
0268 nvidia,function = "rsvd3";
0269 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0270 };
0271 uart-a-dcd {
0272 nvidia,pins = "lpw2";
0273 nvidia,function = "hdmi";
0274 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0275 };
0276
0277 /* Colibri UART-B */
0278 uart-b {
0279 nvidia,pins = "gmc";
0280 nvidia,function = "uartd";
0281 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0282 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0283 };
0284
0285 /* Colibri UART-C */
0286 uart-c {
0287 nvidia,pins = "uad";
0288 nvidia,function = "irda";
0289 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0290 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0291 };
0292
0293 /* Colibri USB_CDET */
0294 usb-cdet {
0295 nvidia,pins = "spdo";
0296 nvidia,function = "rsvd2";
0297 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0298 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0299 };
0300
0301 /* Colibri USBH_OC */
0302 usbh-oc {
0303 nvidia,pins = "spih";
0304 nvidia,function = "spi2_alt";
0305 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0306 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0307 };
0308
0309 /* Colibri USBH_PEN */
0310 usbh-pen {
0311 nvidia,pins = "spig";
0312 nvidia,function = "spi2_alt";
0313 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0314 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0315 };
0316
0317 /* Colibri VGA not supported */
0318 vga {
0319 nvidia,pins = "crtp";
0320 nvidia,function = "crt";
0321 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0322 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0323 };
0324
0325 /* I2C3 (Optional) */
0326 i2c3 {
0327 nvidia,pins = "dtf";
0328 nvidia,function = "i2c3";
0329 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0330 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0331 };
0332
0333 /* JTAG_RTCK */
0334 jtag-rtck {
0335 nvidia,pins = "gpu7";
0336 nvidia,function = "rtck";
0337 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0338 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0339 };
0340
0341 /*
0342 * LAN_RESET, LAN_EXT_WAKEUP and LAN_PME
0343 * (All On-module)
0344 */
0345 gpio-gpv {
0346 nvidia,pins = "gpv";
0347 nvidia,function = "rsvd2";
0348 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0349 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0350 };
0351
0352 /*
0353 * LAN_V_BUS, VDD_FAULT, BATT_FAULT, WM9712 PENDOWN
0354 * (All On-module); Colibri CAN_INT
0355 */
0356 gpio-dte {
0357 nvidia,pins = "dte";
0358 nvidia,function = "rsvd1";
0359 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0360 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0361 };
0362
0363 /* NAND (On-module) */
0364 nand {
0365 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
0366 "kbce", "kbcf";
0367 nvidia,function = "nand";
0368 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0369 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0370 };
0371
0372 /* Onewire (Optional) */
0373 owr {
0374 nvidia,pins = "owc";
0375 nvidia,function = "owr";
0376 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0377 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0378 };
0379
0380 /* Power I2C (On-module) */
0381 i2cp {
0382 nvidia,pins = "i2cp";
0383 nvidia,function = "i2cp";
0384 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0385 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0386 };
0387
0388 /* RESET_OUT */
0389 reset-out {
0390 nvidia,pins = "ata";
0391 nvidia,function = "gmi";
0392 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0393 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0394 };
0395
0396 /*
0397 * SPI1 (Optional)
0398 * Note: spid and spie used for Colibri Address/Data
0399 * Bus (GMI)
0400 */
0401 spi1 {
0402 nvidia,pins = "spid", "spie", "spif";
0403 nvidia,function = "spi1";
0404 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0405 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0406 };
0407
0408 /*
0409 * THERMD_ALERT# (On-module), unlatched I2C address pin
0410 * of LM95245 temperature sensor therefore requires
0411 * disabling for now
0412 */
0413 lvp0 {
0414 nvidia,pins = "lvp0";
0415 nvidia,function = "rsvd3";
0416 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0417 };
0418 };
0419 };
0420
0421 tegra_ac97: ac97@70002000 {
0422 status = "okay";
0423 nvidia,codec-reset-gpio =
0424 <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
0425 nvidia,codec-sync-gpio =
0426 <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
0427 };
0428
0429 serial@70006040 {
0430 compatible = "nvidia,tegra20-hsuart";
0431 /delete-property/ reg-shift;
0432 };
0433
0434 serial@70006300 {
0435 compatible = "nvidia,tegra20-hsuart";
0436 /delete-property/ reg-shift;
0437 };
0438
0439 nand-controller@70008000 {
0440 status = "okay";
0441
0442 nand@0 {
0443 reg = <0>;
0444 #address-cells = <1>;
0445 #size-cells = <1>;
0446 nand-bus-width = <8>;
0447 nand-on-flash-bbt;
0448 nand-ecc-algo = "bch";
0449 nand-is-boot-medium;
0450 nand-ecc-maximize;
0451 wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
0452 };
0453 };
0454
0455 /*
0456 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
0457 * board)
0458 */
0459 i2c@7000c000 {
0460 clock-frequency = <400000>;
0461 };
0462
0463 /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */
0464 hdmi_ddc: i2c@7000c400 {
0465 clock-frequency = <10000>;
0466 };
0467
0468 /* GEN2_I2C: unused */
0469
0470 /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */
0471
0472 /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */
0473 i2c@7000d000 {
0474 status = "okay";
0475 clock-frequency = <100000>;
0476
0477 pmic@34 {
0478 compatible = "ti,tps6586x";
0479 reg = <0x34>;
0480 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0481 ti,system-power-controller;
0482 #gpio-cells = <2>;
0483 gpio-controller;
0484 sys-supply = <®_module_3v3>;
0485 vin-sm0-supply = <®_3v3_vsys>;
0486 vin-sm1-supply = <®_3v3_vsys>;
0487 vin-sm2-supply = <®_3v3_vsys>;
0488 vinldo01-supply = <®_1v8_vdd_ddr2>;
0489 vinldo23-supply = <®_module_3v3>;
0490 vinldo4-supply = <®_module_3v3>;
0491 vinldo678-supply = <®_module_3v3>;
0492 vinldo9-supply = <®_module_3v3>;
0493
0494 regulators {
0495 reg_3v3_vsys: sys {
0496 regulator-name = "VSYS_3.3V";
0497 regulator-always-on;
0498 };
0499
0500 vdd_core: sm0 {
0501 regulator-name = "VDD_CORE_1.2V";
0502 regulator-min-microvolt = <1200000>;
0503 regulator-max-microvolt = <1200000>;
0504 regulator-always-on;
0505 };
0506
0507 sm1 {
0508 regulator-name = "VDD_CPU_1.0V";
0509 regulator-min-microvolt = <1000000>;
0510 regulator-max-microvolt = <1000000>;
0511 regulator-always-on;
0512 };
0513
0514 reg_1v8_vdd_ddr2: sm2 {
0515 regulator-name = "VDD_DDR2_1.8V";
0516 regulator-min-microvolt = <1800000>;
0517 regulator-max-microvolt = <1800000>;
0518 regulator-always-on;
0519 };
0520
0521 /* LDO0 is not connected to anything */
0522
0523 /*
0524 * +3.3V_ENABLE_N switching via FET:
0525 * AVDD_AUDIO_S and +3.3V
0526 * see also +3.3V fixed supply
0527 */
0528 ldo1 {
0529 regulator-name = "AVDD_PLL_1.1V";
0530 regulator-min-microvolt = <1100000>;
0531 regulator-max-microvolt = <1100000>;
0532 regulator-always-on;
0533 };
0534
0535 ldo2 {
0536 regulator-name = "VDD_RTC_1.2V";
0537 regulator-min-microvolt = <1200000>;
0538 regulator-max-microvolt = <1200000>;
0539 };
0540
0541 /* LDO3 is not connected to anything */
0542
0543 ldo4 {
0544 regulator-name = "VDDIO_SYS_1.8V";
0545 regulator-min-microvolt = <1800000>;
0546 regulator-max-microvolt = <1800000>;
0547 regulator-always-on;
0548 };
0549
0550 /* Switched via FET from regular +3.3V */
0551 ldo5 {
0552 regulator-name = "+3.3V_USB";
0553 regulator-min-microvolt = <3300000>;
0554 regulator-max-microvolt = <3300000>;
0555 regulator-always-on;
0556 };
0557
0558 ldo6 {
0559 regulator-name = "AVDD_VDAC_2.85V";
0560 regulator-min-microvolt = <2850000>;
0561 regulator-max-microvolt = <2850000>;
0562 };
0563
0564 reg_3v3_avdd_hdmi: ldo7 {
0565 regulator-name = "AVDD_HDMI_3.3V";
0566 regulator-min-microvolt = <3300000>;
0567 regulator-max-microvolt = <3300000>;
0568 };
0569
0570 reg_1v8_avdd_hdmi_pll: ldo8 {
0571 regulator-name = "AVDD_HDMI_PLL_1.8V";
0572 regulator-min-microvolt = <1800000>;
0573 regulator-max-microvolt = <1800000>;
0574 };
0575
0576 ldo9 {
0577 regulator-name = "VDDIO_RX_DDR_2.85V";
0578 regulator-min-microvolt = <2850000>;
0579 regulator-max-microvolt = <2850000>;
0580 regulator-always-on;
0581 };
0582
0583 ldo_rtc {
0584 regulator-name = "VCC_BATT";
0585 regulator-min-microvolt = <3300000>;
0586 regulator-max-microvolt = <3300000>;
0587 regulator-always-on;
0588 };
0589 };
0590 };
0591
0592 /* LM95245 temperature sensor */
0593 temp-sensor@4c {
0594 compatible = "national,lm95245";
0595 reg = <0x4c>;
0596 };
0597 };
0598
0599 pmc@7000e400 {
0600 nvidia,suspend-mode = <1>;
0601 nvidia,cpu-pwr-good-time = <5000>;
0602 nvidia,cpu-pwr-off-time = <5000>;
0603 nvidia,core-pwr-good-time = <3845 3845>;
0604 nvidia,core-pwr-off-time = <3875>;
0605 nvidia,sys-clock-req-active-high;
0606 core-supply = <&vdd_core>;
0607
0608 /* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */
0609 i2c-thermtrip {
0610 nvidia,i2c-controller-id = <3>;
0611 nvidia,bus-addr = <0x34>;
0612 nvidia,reg-addr = <0x14>;
0613 nvidia,reg-data = <0x8>;
0614 };
0615 };
0616
0617 memory-controller@7000f400 {
0618 emc-table@83250 {
0619 reg = <83250>;
0620 compatible = "nvidia,tegra20-emc-table";
0621 clock-frequency = <83250>;
0622 nvidia,emc-registers = <0x00000005 0x00000011
0623 0x00000004 0x00000002 0x00000004 0x00000004
0624 0x00000001 0x0000000a 0x00000002 0x00000002
0625 0x00000001 0x00000001 0x00000003 0x00000004
0626 0x00000003 0x00000009 0x0000000c 0x0000025f
0627 0x00000000 0x00000003 0x00000003 0x00000002
0628 0x00000002 0x00000001 0x00000008 0x000000c8
0629 0x00000003 0x00000005 0x00000003 0x0000000c
0630 0x00000002 0x00000000 0x00000000 0x00000002
0631 0x00000000 0x00000000 0x00000083 0x00520006
0632 0x00000010 0x00000008 0x00000000 0x00000000
0633 0x00000000 0x00000000 0x00000000 0x00000000>;
0634 };
0635 emc-table@133200 {
0636 reg = <133200>;
0637 compatible = "nvidia,tegra20-emc-table";
0638 clock-frequency = <133200>;
0639 nvidia,emc-registers = <0x00000008 0x00000019
0640 0x00000006 0x00000002 0x00000004 0x00000004
0641 0x00000001 0x0000000a 0x00000002 0x00000002
0642 0x00000002 0x00000001 0x00000003 0x00000004
0643 0x00000003 0x00000009 0x0000000c 0x0000039f
0644 0x00000000 0x00000003 0x00000003 0x00000002
0645 0x00000002 0x00000001 0x00000008 0x000000c8
0646 0x00000003 0x00000007 0x00000003 0x0000000c
0647 0x00000002 0x00000000 0x00000000 0x00000002
0648 0x00000000 0x00000000 0x00000083 0x00510006
0649 0x00000010 0x00000008 0x00000000 0x00000000
0650 0x00000000 0x00000000 0x00000000 0x00000000>;
0651 };
0652 emc-table@166500 {
0653 reg = <166500>;
0654 compatible = "nvidia,tegra20-emc-table";
0655 clock-frequency = <166500>;
0656 nvidia,emc-registers = <0x0000000a 0x00000021
0657 0x00000008 0x00000003 0x00000004 0x00000004
0658 0x00000002 0x0000000a 0x00000003 0x00000003
0659 0x00000002 0x00000001 0x00000003 0x00000004
0660 0x00000003 0x00000009 0x0000000c 0x000004df
0661 0x00000000 0x00000003 0x00000003 0x00000003
0662 0x00000003 0x00000001 0x00000009 0x000000c8
0663 0x00000003 0x00000009 0x00000004 0x0000000c
0664 0x00000002 0x00000000 0x00000000 0x00000002
0665 0x00000000 0x00000000 0x00000083 0x004f0006
0666 0x00000010 0x00000008 0x00000000 0x00000000
0667 0x00000000 0x00000000 0x00000000 0x00000000>;
0668 };
0669 emc-table@333000 {
0670 reg = <333000>;
0671 compatible = "nvidia,tegra20-emc-table";
0672 clock-frequency = <333000>;
0673 nvidia,emc-registers = <0x00000014 0x00000041
0674 0x0000000f 0x00000005 0x00000004 0x00000005
0675 0x00000003 0x0000000a 0x00000005 0x00000005
0676 0x00000004 0x00000001 0x00000003 0x00000004
0677 0x00000003 0x00000009 0x0000000c 0x000009ff
0678 0x00000000 0x00000003 0x00000003 0x00000005
0679 0x00000005 0x00000001 0x0000000e 0x000000c8
0680 0x00000003 0x00000011 0x00000006 0x0000000c
0681 0x00000002 0x00000000 0x00000000 0x00000002
0682 0x00000000 0x00000000 0x00000083 0x00380006
0683 0x00000010 0x00000008 0x00000000 0x00000000
0684 0x00000000 0x00000000 0x00000000 0x00000000>;
0685 };
0686 };
0687
0688 /* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */
0689 usb@c5004000 {
0690 status = "okay";
0691 #address-cells = <1>;
0692 #size-cells = <0>;
0693
0694 ethernet@1 {
0695 compatible = "usbb95,772b";
0696 reg = <1>;
0697 local-mac-address = [00 00 00 00 00 00];
0698 };
0699 };
0700
0701 usb-phy@c5004000 {
0702 status = "okay";
0703 nvidia,phy-reset-gpio =
0704 <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
0705 vbus-supply = <®_lan_v_bus>;
0706 };
0707
0708 clk32k_in: xtal3 {
0709 compatible = "fixed-clock";
0710 #clock-cells = <0>;
0711 clock-frequency = <32768>;
0712 };
0713
0714 reg_lan_v_bus: regulator-lan-v-bus {
0715 compatible = "regulator-fixed";
0716 regulator-name = "LAN_V_BUS";
0717 regulator-min-microvolt = <5000000>;
0718 regulator-max-microvolt = <5000000>;
0719 enable-active-high;
0720 gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
0721 };
0722
0723 reg_module_3v3: regulator-module-3v3 {
0724 compatible = "regulator-fixed";
0725 regulator-name = "+V3.3";
0726 regulator-min-microvolt = <3300000>;
0727 regulator-max-microvolt = <3300000>;
0728 regulator-always-on;
0729 };
0730
0731 sound {
0732 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
0733 "nvidia,tegra-audio-wm9712";
0734 nvidia,model = "Toradex Colibri T20";
0735 nvidia,audio-routing =
0736 "Headphone", "HPOUTL",
0737 "Headphone", "HPOUTR",
0738 "LineIn", "LINEINL",
0739 "LineIn", "LINEINR",
0740 "Mic", "MIC1";
0741 nvidia,ac97-controller = <&tegra_ac97>;
0742 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
0743 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
0744 <&tegra_car TEGRA20_CLK_CDEV1>;
0745 clock-names = "pll_a", "pll_a_out0", "mclk";
0746 };
0747 };
0748
0749 &emc_icc_dvfs_opp_table {
0750 /delete-node/ opp-760000000;
0751 };
0752
0753 &gpio {
0754 lan-reset-n-hog {
0755 gpio-hog;
0756 gpios = <TEGRA_GPIO(V, 4) GPIO_ACTIVE_HIGH>;
0757 output-high;
0758 line-name = "LAN_RESET#";
0759 };
0760
0761 /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */
0762 npwe-hog {
0763 gpio-hog;
0764 gpios = <TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
0765 output-high;
0766 line-name = "Tri-state nPWE";
0767 };
0768
0769 /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */
0770 rdnwr-hog {
0771 gpio-hog;
0772 gpios = <TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>;
0773 output-low;
0774 line-name = "Not tri-state RDnWR";
0775 };
0776 };
