0001 // SPDX-License-Identifier: GPL-2.0
0002 /dts-v1/;
0003
0004 #include <dt-bindings/input/atmel-maxtouch.h>
0005 #include <dt-bindings/input/gpio-keys.h>
0006 #include <dt-bindings/input/input.h>
0007 #include <dt-bindings/thermal/thermal.h>
0008
0009 #include "tegra20.dtsi"
0010 #include "tegra20-cpu-opp.dtsi"
0011 #include "tegra20-cpu-opp-microvolt.dtsi"
0012
0013 / {
0014 model = "Acer Iconia Tab A500";
0015 compatible = "acer,picasso", "nvidia,tegra20";
0016
0017 aliases {
0018 mmc0 = &sdmmc4; /* eMMC */
0019 mmc1 = &sdmmc3; /* MicroSD */
0020 mmc2 = &sdmmc1; /* WiFi */
0021
0022 rtc0 = &pmic;
0023 rtc1 = "/rtc@7000e000";
0024
0025 serial0 = &uartd; /* Docking station */
0026 serial1 = &uartc; /* Bluetooth */
0027 serial2 = &uartb; /* GPS */
0028 };
0029
0030 /*
0031 * The decompressor and also some bootloaders rely on a
0032 * pre-existing /chosen node to be available to insert the
0033 * command line and merge other ATAGS info.
0034 */
0035 chosen {};
0036
0037 memory@0 {
0038 reg = <0x00000000 0x40000000>;
0039 };
0040
0041 reserved-memory {
0042 #address-cells = <1>;
0043 #size-cells = <1>;
0044 ranges;
0045
0046 ramoops@2ffe0000 {
0047 compatible = "ramoops";
0048 reg = <0x2ffe0000 0x10000>; /* 64kB */
0049 console-size = <0x8000>; /* 32kB */
0050 record-size = <0x400>; /* 1kB */
0051 ecc-size = <16>;
0052 };
0053
0054 linux,cma@30000000 {
0055 compatible = "shared-dma-pool";
0056 alloc-ranges = <0x30000000 0x10000000>;
0057 size = <0x10000000>; /* 256MiB */
0058 linux,cma-default;
0059 reusable;
0060 };
0061 };
0062
0063 host1x@50000000 {
0064 dc@54200000 {
0065 rgb {
0066 status = "okay";
0067
0068 port@0 {
0069 lcd_output: endpoint {
0070 remote-endpoint = <&lvds_encoder_input>;
0071 bus-width = <18>;
0072 };
0073 };
0074 };
0075 };
0076
0077 hdmi@54280000 {
0078 status = "okay";
0079
0080 vdd-supply = <&hdmi_vdd_reg>;
0081 pll-supply = <&hdmi_pll_reg>;
0082 hdmi-supply = <&vdd_5v0_sys>;
0083
0084 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
0085 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
0086 GPIO_ACTIVE_HIGH>;
0087 };
0088 };
0089
0090 pinmux@70000014 {
0091 pinctrl-names = "default";
0092 pinctrl-0 = <&state_default>;
0093
0094 state_default: pinmux {
0095 ata {
0096 nvidia,pins = "ata";
0097 nvidia,function = "ide";
0098 };
0099 atb {
0100 nvidia,pins = "atb", "gma", "gme";
0101 nvidia,function = "sdio4";
0102 };
0103 atc {
0104 nvidia,pins = "atc";
0105 nvidia,function = "nand";
0106 };
0107 atd {
0108 nvidia,pins = "atd", "ate", "gmb", "spia",
0109 "spib", "spic";
0110 nvidia,function = "gmi";
0111 };
0112 cdev1 {
0113 nvidia,pins = "cdev1";
0114 nvidia,function = "plla_out";
0115 };
0116 cdev2 {
0117 nvidia,pins = "cdev2";
0118 nvidia,function = "pllp_out4";
0119 };
0120 crtp {
0121 nvidia,pins = "crtp", "lm1";
0122 nvidia,function = "crt";
0123 };
0124 csus {
0125 nvidia,pins = "csus";
0126 nvidia,function = "vi_sensor_clk";
0127 };
0128 dap1 {
0129 nvidia,pins = "dap1";
0130 nvidia,function = "dap1";
0131 };
0132 dap2 {
0133 nvidia,pins = "dap2";
0134 nvidia,function = "dap2";
0135 };
0136 dap3 {
0137 nvidia,pins = "dap3";
0138 nvidia,function = "dap3";
0139 };
0140 dap4 {
0141 nvidia,pins = "dap4";
0142 nvidia,function = "dap4";
0143 };
0144 dta {
0145 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
0146 nvidia,function = "vi";
0147 };
0148 dtf {
0149 nvidia,pins = "dtf";
0150 nvidia,function = "i2c3";
0151 };
0152 gmc {
0153 nvidia,pins = "gmc";
0154 nvidia,function = "uartd";
0155 };
0156 gmd {
0157 nvidia,pins = "gmd";
0158 nvidia,function = "sflash";
0159 };
0160 gpu {
0161 nvidia,pins = "gpu";
0162 nvidia,function = "pwm";
0163 };
0164 gpu7 {
0165 nvidia,pins = "gpu7";
0166 nvidia,function = "rtck";
0167 };
0168 gpv {
0169 nvidia,pins = "gpv", "slxa";
0170 nvidia,function = "pcie";
0171 };
0172 hdint {
0173 nvidia,pins = "hdint";
0174 nvidia,function = "hdmi";
0175 };
0176 i2cp {
0177 nvidia,pins = "i2cp";
0178 nvidia,function = "i2cp";
0179 };
0180 irrx {
0181 nvidia,pins = "irrx", "irtx";
0182 nvidia,function = "uartb";
0183 };
0184 kbca {
0185 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
0186 "kbce", "kbcf";
0187 nvidia,function = "kbc";
0188 };
0189 lcsn {
0190 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
0191 "lsdi", "lvp0";
0192 nvidia,function = "rsvd4";
0193 };
0194 ld0 {
0195 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
0196 "ld5", "ld6", "ld7", "ld8", "ld9",
0197 "ld10", "ld11", "ld12", "ld13", "ld14",
0198 "ld15", "ld16", "ld17", "ldi", "lhp0",
0199 "lhp1", "lhp2", "lhs", "lpp", "lsc0",
0200 "lsc1", "lsck", "lsda", "lspi", "lvp1",
0201 "lvs";
0202 nvidia,function = "displaya";
0203 };
0204 owc {
0205 nvidia,pins = "owc", "spdi", "spdo", "uac";
0206 nvidia,function = "rsvd2";
0207 };
0208 pmc {
0209 nvidia,pins = "pmc";
0210 nvidia,function = "pwr_on";
0211 };
0212 rm {
0213 nvidia,pins = "rm";
0214 nvidia,function = "i2c1";
0215 };
0216 sdb {
0217 nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk";
0218 nvidia,function = "sdio3";
0219 };
0220 sdio1 {
0221 nvidia,pins = "sdio1";
0222 nvidia,function = "sdio1";
0223 };
0224 slxd {
0225 nvidia,pins = "slxd";
0226 nvidia,function = "spdif";
0227 };
0228 spid {
0229 nvidia,pins = "spid", "spie", "spif";
0230 nvidia,function = "spi1";
0231 };
0232 spig {
0233 nvidia,pins = "spig", "spih";
0234 nvidia,function = "spi2_alt";
0235 };
0236 uaa {
0237 nvidia,pins = "uaa", "uab", "uda";
0238 nvidia,function = "ulpi";
0239 };
0240 uad {
0241 nvidia,pins = "uad";
0242 nvidia,function = "irda";
0243 };
0244 uca {
0245 nvidia,pins = "uca", "ucb";
0246 nvidia,function = "uartc";
0247 };
0248 conf_ata {
0249 nvidia,pins = "ata", "atb", "atc", "atd",
0250 "cdev1", "cdev2", "csus", "dap1",
0251 "dap4", "dte", "dtf", "gma", "gmc",
0252 "gme", "gpu", "gpu7", "gpv", "i2cp",
0253 "irrx", "irtx", "pta", "rm",
0254 "sdc", "sdd", "slxc", "slxd", "slxk",
0255 "spdi", "spdo", "uac", "uad", "uda";
0256 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0257 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0258 };
0259 conf_ate {
0260 nvidia,pins = "ate", "dap2", "dap3",
0261 "gmd", "owc", "spia", "spib", "spic",
0262 "spid", "spie";
0263 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0264 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0265 };
0266 conf_ck32 {
0267 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
0268 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
0269 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0270 };
0271 conf_crtp {
0272 nvidia,pins = "crtp", "gmb", "slxa", "spig",
0273 "spih";
0274 nvidia,pull = <TEGRA_PIN_PULL_UP>;
0275 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0276 };
0277 conf_dta {
0278 nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb";
0279 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0280 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0281 };
0282 conf_dte {
0283 nvidia,pins = "spif";
0284 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
0285 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0286 };
0287 conf_hdint {
0288 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
0289 "lpw1", "lsck", "lsda", "lsdi",
0290 "lvp0";
0291 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0292 };
0293 conf_kbca {
0294 nvidia,pins = "kbca", "kbcc", "kbcd",
0295 "kbce", "kbcf", "sdio1", "uaa",
0296 "uab", "uca", "ucb";
0297 nvidia,pull = <TEGRA_PIN_PULL_UP>;
0298 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0299 };
0300 conf_lc {
0301 nvidia,pins = "lc", "ls";
0302 nvidia,pull = <TEGRA_PIN_PULL_UP>;
0303 };
0304 conf_ld0 {
0305 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
0306 "ld5", "ld6", "ld7", "ld8", "ld9",
0307 "ld10", "ld11", "ld12", "ld13", "ld14",
0308 "ld15", "ld16", "ld17", "ldi", "lhp0",
0309 "lhp1", "lhp2", "lhs", "lm0", "lpp",
0310 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
0311 "lvp1", "lvs", "pmc", "sdb";
0312 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0313 };
0314 conf_ld17_0 {
0315 nvidia,pins = "ld17_0";
0316 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
0317 };
0318 drive_ddc {
0319 nvidia,pins = "drive_ddc",
0320 "drive_vi1",
0321 "drive_sdio1";
0322 nvidia,pull-up-strength = <31>;
0323 nvidia,pull-down-strength = <31>;
0324 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
0325 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
0326 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
0327 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
0328 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
0329 };
0330 drive_dbg {
0331 nvidia,pins = "drive_dbg",
0332 "drive_vi2",
0333 "drive_at1",
0334 "drive_ao1";
0335 nvidia,pull-up-strength = <31>;
0336 nvidia,pull-down-strength = <31>;
0337 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
0338 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
0339 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
0340 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
0341 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
0342 };
0343 };
0344
0345 state_i2cmux_ddc: pinmux_i2cmux_ddc {
0346 ddc {
0347 nvidia,pins = "ddc";
0348 nvidia,function = "i2c2";
0349 };
0350 pta {
0351 nvidia,pins = "pta";
0352 nvidia,function = "rsvd4";
0353 };
0354 };
0355
0356 state_i2cmux_pta: pinmux_i2cmux_pta {
0357 ddc {
0358 nvidia,pins = "ddc";
0359 nvidia,function = "rsvd4";
0360 };
0361 pta {
0362 nvidia,pins = "pta";
0363 nvidia,function = "i2c2";
0364 };
0365 };
0366
0367 state_i2cmux_idle: pinmux_i2cmux_idle {
0368 ddc {
0369 nvidia,pins = "ddc";
0370 nvidia,function = "rsvd4";
0371 };
0372 pta {
0373 nvidia,pins = "pta";
0374 nvidia,function = "rsvd4";
0375 };
0376 };
0377 };
0378
0379 tegra_spdif: spdif@70002400 {
0380 status = "okay";
0381
0382 nvidia,fixed-parent-rate;
0383 };
0384
0385 tegra_i2s1: i2s@70002800 {
0386 status = "okay";
0387
0388 nvidia,fixed-parent-rate;
0389 };
0390
0391 uartb: serial@70006040 {
0392 compatible = "nvidia,tegra20-hsuart";
0393 /delete-property/ reg-shift;
0394 /* GPS BCM4751 */
0395 };
0396
0397 uartc: serial@70006200 {
0398 compatible = "nvidia,tegra20-hsuart";
0399 /delete-property/ reg-shift;
0400 status = "okay";
0401
0402 /* Azurewave AW-NH665 BCM4329B1 */
0403 bluetooth {
0404 compatible = "brcm,bcm4329-bt";
0405
0406 interrupt-parent = <&gpio>;
0407 interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
0408 interrupt-names = "host-wakeup";
0409
0410 /* PLLP 216MHz / 16 / 4 */
0411 max-speed = <3375000>;
0412
0413 clocks = <&rtc_32k_wifi>;
0414 clock-names = "txco";
0415
0416 vbat-supply = <&vdd_3v3_sys>;
0417 vddio-supply = <&vdd_1v8_sys>;
0418
0419 device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
0420 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
0421 };
0422 };
0423
0424 uartd: serial@70006300 {
0425 /* Docking station */
0426 };
0427
0428 i2c@7000c000 {
0429 clock-frequency = <400000>;
0430 status = "okay";
0431
0432 wm8903: audio-codec@1a {
0433 compatible = "wlf,wm8903";
0434 reg = <0x1a>;
0435
0436 interrupt-parent = <&gpio>;
0437 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_EDGE_BOTH>;
0438
0439 gpio-controller;
0440 #gpio-cells = <2>;
0441
0442 micdet-cfg = <0>;
0443 micdet-delay = <100>;
0444
0445 gpio-cfg = <
0446 0x0000 /* MIC_LR_OUT# GPIO, output, low */
0447 0x0000 /* FM2018-enable GPIO, output, low */
0448 0x0000 /* Speaker-enable GPIO, output, low */
0449 0x0200 /* Interrupt, output */
0450 0x01a0 /* BCLK, input, active high */
0451 >;
0452
0453 AVDD-supply = <&vdd_1v8_sys>;
0454 CPVDD-supply = <&vdd_1v8_sys>;
0455 DBVDD-supply = <&vdd_1v8_sys>;
0456 DCVDD-supply = <&vdd_1v8_sys>;
0457 };
0458
0459 touchscreen@4c {
0460 compatible = "atmel,maxtouch";
0461 reg = <0x4c>;
0462
0463 interrupt-parent = <&gpio>;
0464 interrupts = <TEGRA_GPIO(V, 6) IRQ_TYPE_LEVEL_LOW>;
0465
0466 reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>;
0467
0468 vdda-supply = <&vdd_3v3_sys>;
0469 vdd-supply = <&vdd_3v3_sys>;
0470
0471 atmel,wakeup-method = <ATMEL_MXT_WAKEUP_I2C_SCL>;
0472 };
0473
0474 gyroscope@68 {
0475 compatible = "invensense,mpu3050";
0476 reg = <0x68>;
0477
0478 interrupt-parent = <&gpio>;
0479 interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_EDGE_RISING>;
0480
0481 vdd-supply = <&vdd_3v3_sys>;
0482 vlogic-supply = <&vdd_1v8_sys>;
0483
0484 mount-matrix = "0", "1", "0",
0485 "1", "0", "0",
0486 "0", "0", "-1";
0487
0488 i2c-gate {
0489 #address-cells = <1>;
0490 #size-cells = <0>;
0491
0492 accelerometer@f {
0493 compatible = "kionix,kxtf9";
0494 reg = <0x0f>;
0495
0496 interrupt-parent = <&gpio>;
0497 interrupts = <TEGRA_GPIO(S, 7) IRQ_TYPE_EDGE_RISING>;
0498
0499 vdd-supply = <&vdd_1v8_sys>;
0500 vddio-supply = <&vdd_1v8_sys>;
0501
0502 mount-matrix = "0", "1", "0",
0503 "1", "0", "0",
0504 "0", "0", "-1";
0505 };
0506 };
0507 };
0508 };
0509
0510 i2c@7000c400 {
0511 clock-frequency = <10000>;
0512 status = "okay";
0513 };
0514
0515 i2cmux {
0516 compatible = "i2c-mux-pinctrl";
0517 #address-cells = <1>;
0518 #size-cells = <0>;
0519
0520 i2c-parent = <&{/i2c@7000c400}>;
0521
0522 pinctrl-names = "ddc", "pta", "idle";
0523 pinctrl-0 = <&state_i2cmux_ddc>;
0524 pinctrl-1 = <&state_i2cmux_pta>;
0525 pinctrl-2 = <&state_i2cmux_idle>;
0526
0527 hdmi_ddc: i2c@0 {
0528 reg = <0>;
0529 #address-cells = <1>;
0530 #size-cells = <0>;
0531 };
0532
0533 panel_ddc: i2c@1 {
0534 reg = <1>;
0535 #address-cells = <1>;
0536 #size-cells = <0>;
0537
0538 embedded-controller@58 {
0539 compatible = "acer,a500-iconia-ec", "ene,kb930";
0540 reg = <0x58>;
0541
0542 system-power-controller;
0543
0544 monitored-battery = <&bat1010>;
0545 power-supplies = <&mains>;
0546 };
0547 };
0548 };
0549
0550 pwm: pwm@7000a000 {
0551 status = "okay";
0552 };
0553
0554 i2c@7000d000 {
0555 clock-frequency = <100000>;
0556 status = "okay";
0557
0558 magnetometer@c {
0559 compatible = "asahi-kasei,ak8975";
0560 reg = <0x0c>;
0561
0562 interrupt-parent = <&gpio>;
0563 interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_EDGE_RISING>;
0564
0565 vdd-supply = <&vdd_3v3_sys>;
0566 vid-supply = <&vdd_1v8_sys>;
0567
0568 mount-matrix = "1", "0", "0",
0569 "0", "-1", "0",
0570 "0", "0", "-1";
0571 };
0572
0573 pmic: pmic@34 {
0574 compatible = "ti,tps6586x";
0575 reg = <0x34>;
0576
0577 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0578
0579 #gpio-cells = <2>;
0580 gpio-controller;
0581
0582 sys-supply = <&vdd_5v0_sys>;
0583 vin-sm0-supply = <&sys_reg>;
0584 vin-sm1-supply = <&sys_reg>;
0585 vin-sm2-supply = <&sys_reg>;
0586 vinldo01-supply = <&sm2_reg>;
0587 vinldo23-supply = <&sm2_reg>;
0588 vinldo4-supply = <&sm2_reg>;
0589 vinldo678-supply = <&sm2_reg>;
0590 vinldo9-supply = <&sm2_reg>;
0591
0592 regulators {
0593 sys_reg: sys {
0594 regulator-name = "vdd_sys";
0595 regulator-always-on;
0596 };
0597
0598 vdd_core: sm0 {
0599 regulator-name = "vdd_sm0,vdd_core";
0600 regulator-min-microvolt = <950000>;
0601 regulator-max-microvolt = <1300000>;
0602 regulator-coupled-with = <&rtc_vdd &vdd_cpu>;
0603 regulator-coupled-max-spread = <170000 550000>;
0604 regulator-always-on;
0605 regulator-boot-on;
0606
0607 nvidia,tegra-core-regulator;
0608 };
0609
0610 vdd_cpu: sm1 {
0611 regulator-name = "vdd_sm1,vdd_cpu";
0612 regulator-min-microvolt = <750000>;
0613 regulator-max-microvolt = <1125000>;
0614 regulator-coupled-with = <&vdd_core &rtc_vdd>;
0615 regulator-coupled-max-spread = <550000 550000>;
0616 regulator-always-on;
0617 regulator-boot-on;
0618
0619 nvidia,tegra-cpu-regulator;
0620 };
0621
0622 sm2_reg: sm2 {
0623 regulator-name = "vdd_sm2,vin_ldo*";
0624 regulator-min-microvolt = <3700000>;
0625 regulator-max-microvolt = <3700000>;
0626 regulator-always-on;
0627 };
0628
0629 /* LDO0 is not connected to anything */
0630
0631 ldo1 {
0632 regulator-name = "vdd_ldo1,avdd_pll*";
0633 regulator-min-microvolt = <1100000>;
0634 regulator-max-microvolt = <1100000>;
0635 regulator-always-on;
0636 regulator-boot-on;
0637 };
0638
0639 rtc_vdd: ldo2 {
0640 regulator-name = "vdd_ldo2,vdd_rtc";
0641 regulator-min-microvolt = <950000>;
0642 regulator-max-microvolt = <1300000>;
0643 regulator-coupled-with = <&vdd_core &vdd_cpu>;
0644 regulator-coupled-max-spread = <170000 550000>;
0645 regulator-always-on;
0646 regulator-boot-on;
0647
0648 nvidia,tegra-rtc-regulator;
0649 };
0650
0651 ldo3 {
0652 regulator-name = "vdd_ldo3,avdd_usb*";
0653 regulator-min-microvolt = <3300000>;
0654 regulator-max-microvolt = <3300000>;
0655 regulator-always-on;
0656 };
0657
0658 ldo4 {
0659 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
0660 regulator-min-microvolt = <1800000>;
0661 regulator-max-microvolt = <1800000>;
0662 regulator-always-on;
0663 regulator-boot-on;
0664 };
0665
0666 vcore_emmc: ldo5 {
0667 regulator-name = "vdd_ldo5,vcore_mmc";
0668 regulator-min-microvolt = <2850000>;
0669 regulator-max-microvolt = <2850000>;
0670 regulator-always-on;
0671 };
0672
0673 avdd_vdac_reg: ldo6 {
0674 regulator-name = "vdd_ldo6,avdd_vdac";
0675 regulator-min-microvolt = <2850000>;
0676 regulator-max-microvolt = <2850000>;
0677 };
0678
0679 hdmi_vdd_reg: ldo7 {
0680 regulator-name = "vdd_ldo7,avdd_hdmi";
0681 regulator-min-microvolt = <3300000>;
0682 regulator-max-microvolt = <3300000>;
0683 };
0684
0685 hdmi_pll_reg: ldo8 {
0686 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
0687 regulator-min-microvolt = <1800000>;
0688 regulator-max-microvolt = <1800000>;
0689 };
0690
0691 ldo9 {
0692 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
0693 regulator-min-microvolt = <2850000>;
0694 regulator-max-microvolt = <2850000>;
0695 regulator-always-on;
0696 regulator-boot-on;
0697 };
0698
0699 ldo_rtc {
0700 regulator-name = "vdd_rtc_out,vdd_cell";
0701 regulator-min-microvolt = <3300000>;
0702 regulator-max-microvolt = <3300000>;
0703 regulator-always-on;
0704 regulator-boot-on;
0705 };
0706 };
0707 };
0708
0709 nct1008: temperature-sensor@4c {
0710 compatible = "onnn,nct1008";
0711 reg = <0x4c>;
0712 vcc-supply = <&vdd_3v3_sys>;
0713
0714 interrupt-parent = <&gpio>;
0715 interrupts = <TEGRA_GPIO(N, 6) IRQ_TYPE_EDGE_FALLING>;
0716
0717 #thermal-sensor-cells = <1>;
0718 };
0719 };
0720
0721 pmc@7000e400 {
0722 nvidia,invert-interrupt;
0723 nvidia,suspend-mode = <1>;
0724 nvidia,cpu-pwr-good-time = <2000>;
0725 nvidia,cpu-pwr-off-time = <100>;
0726 nvidia,core-pwr-good-time = <3845 3845>;
0727 nvidia,core-pwr-off-time = <458>;
0728 nvidia,sys-clock-req-active-high;
0729 core-supply = <&vdd_core>;
0730 };
0731
0732 usb@c5000000 {
0733 compatible = "nvidia,tegra20-udc";
0734 status = "okay";
0735 dr_mode = "peripheral";
0736 };
0737
0738 usb-phy@c5000000 {
0739 status = "okay";
0740 dr_mode = "peripheral";
0741 nvidia,xcvr-setup-use-fuses;
0742 nvidia,xcvr-lsfslew = <2>;
0743 nvidia,xcvr-lsrslew = <2>;
0744 };
0745
0746 usb@c5008000 {
0747 status = "okay";
0748 };
0749
0750 usb-phy@c5008000 {
0751 status = "okay";
0752 nvidia,xcvr-setup-use-fuses;
0753 nvidia,xcvr-lsfslew = <2>;
0754 nvidia,xcvr-lsrslew = <2>;
0755 vbus-supply = <&vdd_5v0_sys>;
0756 };
0757
0758 brcm_wifi_pwrseq: wifi-pwrseq {
0759 compatible = "mmc-pwrseq-simple";
0760
0761 clocks = <&rtc_32k_wifi>;
0762 clock-names = "ext_clock";
0763
0764 reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>;
0765 post-power-on-delay-ms = <300>;
0766 power-off-delay-us = <300>;
0767 };
0768
0769 sdmmc1: mmc@c8000000 {
0770 status = "okay";
0771
0772 #address-cells = <1>;
0773 #size-cells = <0>;
0774
0775 assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
0776 assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
0777 assigned-clock-rates = <50000000>;
0778
0779 max-frequency = <50000000>;
0780 keep-power-in-suspend;
0781 bus-width = <4>;
0782 non-removable;
0783
0784 mmc-pwrseq = <&brcm_wifi_pwrseq>;
0785 vmmc-supply = <&vdd_3v3_sys>;
0786 vqmmc-supply = <&vdd_1v8_sys>;
0787
0788 /* Azurewave AW-NH611 BCM4329 */
0789 wifi@1 {
0790 reg = <1>;
0791 compatible = "brcm,bcm4329-fmac";
0792 interrupt-parent = <&gpio>;
0793 interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>;
0794 interrupt-names = "host-wake";
0795 };
0796 };
0797
0798 sdmmc3: mmc@c8000400 {
0799 status = "okay";
0800 bus-width = <4>;
0801 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
0802 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
0803 vmmc-supply = <&vdd_3v3_sys>;
0804 vqmmc-supply = <&vdd_3v3_sys>;
0805 };
0806
0807 sdmmc4: mmc@c8000600 {
0808 status = "okay";
0809 bus-width = <8>;
0810 vmmc-supply = <&vcore_emmc>;
0811 vqmmc-supply = <&vdd_3v3_sys>;
0812 non-removable;
0813 };
0814
0815 mains: ac-adapter-detect {
0816 compatible = "gpio-charger";
0817 charger-type = "mains";
0818 gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
0819 };
0820
0821 backlight: backlight {
0822 compatible = "pwm-backlight";
0823
0824 enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
0825 power-supply = <&vdd_3v3_sys>;
0826 pwms = <&pwm 2 41667>;
0827
0828 brightness-levels = <7 255>;
0829 num-interpolated-steps = <248>;
0830 default-brightness-level = <20>;
0831 };
0832
0833 bat1010: battery-2s1p {
0834 compatible = "simple-battery";
0835 charge-full-design-microamp-hours = <3260000>;
0836 energy-full-design-microwatt-hours = <24000000>;
0837 operating-range-celsius = <0 40>;
0838 };
0839
0840 /* PMIC has a built-in 32KHz oscillator which is used by PMC */
0841 clk32k_in: clock-32k-in {
0842 compatible = "fixed-clock";
0843 #clock-cells = <0>;
0844 clock-frequency = <32768>;
0845 clock-output-names = "tps658621-out32k";
0846 };
0847
0848 /*
0849 * This standalone onboard fixed-clock always-ON 32KHz
0850 * oscillator is used as a reference clock-source by the
0851 * Azurewave WiFi/BT module.
0852 */
0853 rtc_32k_wifi: clock-32k-wifi {
0854 compatible = "fixed-clock";
0855 #clock-cells = <0>;
0856 clock-frequency = <32768>;
0857 clock-output-names = "kk3270032";
0858 };
0859
0860 cpus {
0861 cpu0: cpu@0 {
0862 cpu-supply = <&vdd_cpu>;
0863 operating-points-v2 = <&cpu0_opp_table>;
0864 #cooling-cells = <2>;
0865 };
0866
0867 cpu1: cpu@1 {
0868 cpu-supply = <&vdd_cpu>;
0869 operating-points-v2 = <&cpu0_opp_table>;
0870 #cooling-cells = <2>;
0871 };
0872 };
0873
0874 display-panel {
0875 compatible = "auo,b101ew05", "panel-lvds";
0876
0877 ddc-i2c-bus = <&panel_ddc>;
0878 power-supply = <&vdd_pnl>;
0879 backlight = <&backlight>;
0880
0881 width-mm = <218>;
0882 height-mm = <135>;
0883
0884 data-mapping = "jeida-18";
0885
0886 panel-timing {
0887 clock-frequency = <71200000>;
0888 hactive = <1280>;
0889 vactive = <800>;
0890 hfront-porch = <8>;
0891 hback-porch = <18>;
0892 hsync-len = <184>;
0893 vsync-len = <3>;
0894 vfront-porch = <4>;
0895 vback-porch = <8>;
0896 };
0897
0898 port {
0899 panel_input: endpoint {
0900 remote-endpoint = <&lvds_encoder_output>;
0901 };
0902 };
0903 };
0904
0905 gpio-keys {
0906 compatible = "gpio-keys";
0907
0908 key-power {
0909 label = "Power";
0910 gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
0911 linux,code = <KEY_POWER>;
0912 debounce-interval = <10>;
0913 wakeup-event-action = <EV_ACT_ASSERTED>;
0914 wakeup-source;
0915 };
0916
0917 key-rotation-lock {
0918 label = "Rotate-lock";
0919 gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>;
0920 linux,code = <SW_ROTATE_LOCK>;
0921 linux,input-type = <EV_SW>;
0922 debounce-interval = <10>;
0923 };
0924
0925 key-volume-up {
0926 label = "Volume Up";
0927 gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
0928 linux,code = <KEY_VOLUMEUP>;
0929 debounce-interval = <10>;
0930 wakeup-event-action = <EV_ACT_ASSERTED>;
0931 wakeup-source;
0932 };
0933
0934 key-volume-down {
0935 label = "Volume Down";
0936 gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
0937 linux,code = <KEY_VOLUMEDOWN>;
0938 debounce-interval = <10>;
0939 wakeup-event-action = <EV_ACT_ASSERTED>;
0940 wakeup-source;
0941 };
0942 };
0943
0944 haptic-feedback {
0945 compatible = "gpio-vibrator";
0946 enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
0947 vcc-supply = <&vdd_3v3_sys>;
0948 };
0949
0950 lvds-encoder {
0951 compatible = "ti,sn75lvds83", "lvds-encoder";
0952
0953 powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>;
0954 power-supply = <&vdd_3v3_sys>;
0955
0956 ports {
0957 #address-cells = <1>;
0958 #size-cells = <0>;
0959
0960 port@0 {
0961 reg = <0>;
0962
0963 lvds_encoder_input: endpoint {
0964 remote-endpoint = <&lcd_output>;
0965 };
0966 };
0967
0968 port@1 {
0969 reg = <1>;
0970
0971 lvds_encoder_output: endpoint {
0972 remote-endpoint = <&panel_input>;
0973 };
0974 };
0975 };
0976 };
0977
0978 vdd_5v0_sys: regulator-5v0 {
0979 compatible = "regulator-fixed";
0980 regulator-name = "vdd_5v0";
0981 regulator-min-microvolt = <5000000>;
0982 regulator-max-microvolt = <5000000>;
0983 regulator-always-on;
0984 };
0985
0986 vdd_3v3_sys: regulator-3v3 {
0987 compatible = "regulator-fixed";
0988 regulator-name = "vdd_3v3_vs";
0989 regulator-min-microvolt = <3300000>;
0990 regulator-max-microvolt = <3300000>;
0991 regulator-always-on;
0992 vin-supply = <&vdd_5v0_sys>;
0993 };
0994
0995 vdd_1v8_sys: regulator-1v8 {
0996 compatible = "regulator-fixed";
0997 regulator-name = "vdd_1v8_vs";
0998 regulator-min-microvolt = <1800000>;
0999 regulator-max-microvolt = <1800000>;
1000 regulator-always-on;
1001 vin-supply = <&vdd_5v0_sys>;
1002 };
1003
1004 vdd_pnl: regulator-panel {
1005 compatible = "regulator-fixed";
1006 regulator-name = "vdd_panel";
1007 regulator-min-microvolt = <3300000>;
1008 regulator-max-microvolt = <3300000>;
1009 regulator-enable-ramp-delay = <300000>;
1010 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
1011 enable-active-high;
1012 vin-supply = <&vdd_5v0_sys>;
1013 };
1014
1015 sound {
1016 compatible = "nvidia,tegra-audio-wm8903-picasso",
1017 "nvidia,tegra-audio-wm8903";
1018 nvidia,model = "Acer Iconia Tab A500 WM8903";
1019
1020 nvidia,audio-routing =
1021 "Headphone Jack", "HPOUTR",
1022 "Headphone Jack", "HPOUTL",
1023 "Int Spk", "LINEOUTL",
1024 "Int Spk", "LINEOUTR",
1025 "Mic Jack", "MICBIAS",
1026 "IN2L", "Mic Jack",
1027 "IN2R", "Mic Jack",
1028 "IN1L", "Int Mic",
1029 "IN1R", "Int Mic";
1030
1031 nvidia,i2s-controller = <&tegra_i2s1>;
1032 nvidia,audio-codec = <&wm8903>;
1033
1034 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
1035 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
1036 nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>;
1037 nvidia,headset;
1038
1039 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
1040 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
1041 <&tegra_car TEGRA20_CLK_CDEV1>;
1042 clock-names = "pll_a", "pll_a_out0", "mclk";
1043 };
1044
1045 thermal-zones {
1046 /*
1047 * NCT1008 has two sensors:
1048 *
1049 * 0: internal that monitors ambient/skin temperature
1050 * 1: external that is connected to the CPU's diode
1051 *
1052 * Ideally we should use userspace thermal governor,
1053 * but it's a much more complex solution. The "skin"
1054 * zone is a simpler solution which prevents A500 from
1055 * getting too hot from a user's tactile perspective.
1056 * The CPU zone is intended to protect silicon from damage.
1057 */
1058
1059 skin-thermal {
1060 polling-delay-passive = <1000>; /* milliseconds */
1061 polling-delay = <5000>; /* milliseconds */
1062
1063 thermal-sensors = <&nct1008 0>;
1064
1065 trips {
1066 trip0: skin-alert {
1067 /* start throttling at 60C */
1068 temperature = <60000>;
1069 hysteresis = <200>;
1070 type = "passive";
1071 };
1072
1073 trip1: skin-crit {
1074 /* shut down at 70C */
1075 temperature = <70000>;
1076 hysteresis = <2000>;
1077 type = "critical";
1078 };
1079 };
1080
1081 cooling-maps {
1082 map0 {
1083 trip = <&trip0>;
1084 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1085 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1086 };
1087 };
1088 };
1089
1090 cpu-thermal {
1091 polling-delay-passive = <1000>; /* milliseconds */
1092 polling-delay = <5000>; /* milliseconds */
1093
1094 thermal-sensors = <&nct1008 1>;
1095
1096 trips {
1097 trip2: cpu-alert {
1098 /* throttle at 85C until temperature drops to 84.8C */
1099 temperature = <85000>;
1100 hysteresis = <200>;
1101 type = "passive";
1102 };
1103
1104 trip3: cpu-crit {
1105 /* shut down at 90C */
1106 temperature = <90000>;
1107 hysteresis = <2000>;
1108 type = "critical";
1109 };
1110 };
1111
1112 cooling-maps {
1113 map1 {
1114 trip = <&trip2>;
1115 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1116 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1117 };
1118 };
1119 };
1120 };
1121
1122 memory-controller@7000f400 {
1123 nvidia,use-ram-code;
1124
1125 emc-tables@0 {
1126 nvidia,ram-code = <0>; /* elpida-8gb */
1127 reg = <0>;
1128
1129 #address-cells = <1>;
1130 #size-cells = <0>;
1131
1132 emc-table@25000 {
1133 reg = <25000>;
1134 compatible = "nvidia,tegra20-emc-table";
1135 clock-frequency = <25000>;
1136 nvidia,emc-registers = <0x00000002 0x00000006
1137 0x00000003 0x00000003 0x00000006 0x00000004
1138 0x00000002 0x00000009 0x00000003 0x00000003
1139 0x00000002 0x00000002 0x00000002 0x00000004
1140 0x00000003 0x00000008 0x0000000b 0x0000004d
1141 0x00000000 0x00000003 0x00000003 0x00000003
1142 0x00000008 0x00000001 0x0000000a 0x00000004
1143 0x00000003 0x00000008 0x00000004 0x00000006
1144 0x00000002 0x00000068 0x00000000 0x00000003
1145 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1146 0x00070000 0x00000000 0x00000000 0x00000003
1147 0x00000000 0x00000000 0x00000000 0x00000000>;
1148 };
1149
1150 emc-table@50000 {
1151 reg = <50000>;
1152 compatible = "nvidia,tegra20-emc-table";
1153 clock-frequency = <50000>;
1154 nvidia,emc-registers = <0x00000003 0x00000007
1155 0x00000003 0x00000003 0x00000006 0x00000004
1156 0x00000002 0x00000009 0x00000003 0x00000003
1157 0x00000002 0x00000002 0x00000002 0x00000005
1158 0x00000003 0x00000008 0x0000000b 0x0000009f
1159 0x00000000 0x00000003 0x00000003 0x00000003
1160 0x00000008 0x00000001 0x0000000a 0x00000007
1161 0x00000003 0x00000008 0x00000004 0x00000006
1162 0x00000002 0x000000d0 0x00000000 0x00000000
1163 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1164 0x00070000 0x00000000 0x00000000 0x00000005
1165 0x00000000 0x00000000 0x00000000 0x00000000>;
1166 };
1167
1168 emc-table@75000 {
1169 reg = <75000>;
1170 compatible = "nvidia,tegra20-emc-table";
1171 clock-frequency = <75000>;
1172 nvidia,emc-registers = <0x00000005 0x0000000a
1173 0x00000004 0x00000003 0x00000006 0x00000004
1174 0x00000002 0x00000009 0x00000003 0x00000003
1175 0x00000002 0x00000002 0x00000002 0x00000005
1176 0x00000003 0x00000008 0x0000000b 0x000000ff
1177 0x00000000 0x00000003 0x00000003 0x00000003
1178 0x00000008 0x00000001 0x0000000a 0x0000000b
1179 0x00000003 0x00000008 0x00000004 0x00000006
1180 0x00000002 0x00000138 0x00000000 0x00000000
1181 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1182 0x00070000 0x00000000 0x00000000 0x00000007
1183 0x00000000 0x00000000 0x00000000 0x00000000>;
1184 };
1185
1186 emc-table@150000 {
1187 reg = <150000>;
1188 compatible = "nvidia,tegra20-emc-table";
1189 clock-frequency = <150000>;
1190 nvidia,emc-registers = <0x00000009 0x00000014
1191 0x00000007 0x00000003 0x00000006 0x00000004
1192 0x00000002 0x00000009 0x00000003 0x00000003
1193 0x00000002 0x00000002 0x00000002 0x00000005
1194 0x00000003 0x00000008 0x0000000b 0x0000021f
1195 0x00000000 0x00000003 0x00000003 0x00000003
1196 0x00000008 0x00000001 0x0000000a 0x00000015
1197 0x00000003 0x00000008 0x00000004 0x00000006
1198 0x00000002 0x00000270 0x00000000 0x00000001
1199 0x00000000 0x00000000 0x00000282 0xa07c04ae
1200 0x007dd510 0x00000000 0x00000000 0x0000000e
1201 0x00000000 0x00000000 0x00000000 0x00000000>;
1202 };
1203
1204 emc-table@300000 {
1205 reg = <300000>;
1206 compatible = "nvidia,tegra20-emc-table";
1207 clock-frequency = <300000>;
1208 nvidia,emc-registers = <0x00000012 0x00000027
1209 0x0000000d 0x00000006 0x00000007 0x00000005
1210 0x00000003 0x00000009 0x00000006 0x00000006
1211 0x00000003 0x00000003 0x00000002 0x00000006
1212 0x00000003 0x00000009 0x0000000c 0x0000045f
1213 0x00000000 0x00000004 0x00000004 0x00000006
1214 0x00000008 0x00000001 0x0000000e 0x0000002a
1215 0x00000003 0x0000000f 0x00000007 0x00000005
1216 0x00000002 0x000004e1 0x00000005 0x00000002
1217 0x00000000 0x00000000 0x00000282 0xe059048b
1218 0x007e1510 0x00000000 0x00000000 0x0000001b
1219 0x00000000 0x00000000 0x00000000 0x00000000>;
1220 };
1221 };
1222
1223 emc-tables@1 {
1224 nvidia,ram-code = <1>; /* elpida-4gb */
1225 reg = <1>;
1226
1227 #address-cells = <1>;
1228 #size-cells = <0>;
1229
1230 emc-table@25000 {
1231 reg = <25000>;
1232 compatible = "nvidia,tegra20-emc-table";
1233 clock-frequency = <25000>;
1234 nvidia,emc-registers = <0x00000002 0x00000006
1235 0x00000003 0x00000003 0x00000006 0x00000004
1236 0x00000002 0x00000009 0x00000003 0x00000003
1237 0x00000002 0x00000002 0x00000002 0x00000004
1238 0x00000003 0x00000008 0x0000000b 0x0000004d
1239 0x00000000 0x00000003 0x00000003 0x00000003
1240 0x00000008 0x00000001 0x0000000a 0x00000004
1241 0x00000003 0x00000008 0x00000004 0x00000006
1242 0x00000002 0x00000068 0x00000000 0x00000003
1243 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1244 0x0007c000 0x00000000 0x00000000 0x00000003
1245 0x00000000 0x00000000 0x00000000 0x00000000>;
1246 };
1247
1248 emc-table@50000 {
1249 reg = <50000>;
1250 compatible = "nvidia,tegra20-emc-table";
1251 clock-frequency = <50000>;
1252 nvidia,emc-registers = <0x00000003 0x00000007
1253 0x00000003 0x00000003 0x00000006 0x00000004
1254 0x00000002 0x00000009 0x00000003 0x00000003
1255 0x00000002 0x00000002 0x00000002 0x00000005
1256 0x00000003 0x00000008 0x0000000b 0x0000009f
1257 0x00000000 0x00000003 0x00000003 0x00000003
1258 0x00000008 0x00000001 0x0000000a 0x00000007
1259 0x00000003 0x00000008 0x00000004 0x00000006
1260 0x00000002 0x000000d0 0x00000000 0x00000000
1261 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1262 0x0007c000 0x00000000 0x00000000 0x00000005
1263 0x00000000 0x00000000 0x00000000 0x00000000>;
1264 };
1265
1266 emc-table@75000 {
1267 reg = <75000>;
1268 compatible = "nvidia,tegra20-emc-table";
1269 clock-frequency = <75000>;
1270 nvidia,emc-registers = <0x00000005 0x0000000a
1271 0x00000004 0x00000003 0x00000006 0x00000004
1272 0x00000002 0x00000009 0x00000003 0x00000003
1273 0x00000002 0x00000002 0x00000002 0x00000005
1274 0x00000003 0x00000008 0x0000000b 0x000000ff
1275 0x00000000 0x00000003 0x00000003 0x00000003
1276 0x00000008 0x00000001 0x0000000a 0x0000000b
1277 0x00000003 0x00000008 0x00000004 0x00000006
1278 0x00000002 0x00000138 0x00000000 0x00000000
1279 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1280 0x0007c000 0x00000000 0x00000000 0x00000007
1281 0x00000000 0x00000000 0x00000000 0x00000000>;
1282 };
1283
1284 emc-table@150000 {
1285 reg = <150000>;
1286 compatible = "nvidia,tegra20-emc-table";
1287 clock-frequency = <150000>;
1288 nvidia,emc-registers = <0x00000009 0x00000014
1289 0x00000007 0x00000003 0x00000006 0x00000004
1290 0x00000002 0x00000009 0x00000003 0x00000003
1291 0x00000002 0x00000002 0x00000002 0x00000005
1292 0x00000003 0x00000008 0x0000000b 0x0000021f
1293 0x00000000 0x00000003 0x00000003 0x00000003
1294 0x00000008 0x00000001 0x0000000a 0x00000015
1295 0x00000003 0x00000008 0x00000004 0x00000006
1296 0x00000002 0x00000270 0x00000000 0x00000001
1297 0x00000000 0x00000000 0x00000282 0xa07c04ae
1298 0x007e4010 0x00000000 0x00000000 0x0000000e
1299 0x00000000 0x00000000 0x00000000 0x00000000>;
1300 };
1301
1302 emc-table@300000 {
1303 reg = <300000>;
1304 compatible = "nvidia,tegra20-emc-table";
1305 clock-frequency = <300000>;
1306 nvidia,emc-registers = <0x00000012 0x00000027
1307 0x0000000d 0x00000006 0x00000007 0x00000005
1308 0x00000003 0x00000009 0x00000006 0x00000006
1309 0x00000003 0x00000003 0x00000002 0x00000006
1310 0x00000003 0x00000009 0x0000000c 0x0000045f
1311 0x00000000 0x00000004 0x00000004 0x00000006
1312 0x00000008 0x00000001 0x0000000e 0x0000002a
1313 0x00000003 0x0000000f 0x00000007 0x00000005
1314 0x00000002 0x000004e1 0x00000005 0x00000002
1315 0x00000000 0x00000000 0x00000282 0xe059048b
1316 0x007e0010 0x00000000 0x00000000 0x0000001b
1317 0x00000000 0x00000000 0x00000000 0x00000000>;
1318 };
1319 };
1320
1321 emc-tables@2 {
1322 nvidia,ram-code = <2>; /* hynix-8gb */
1323 reg = <2>;
1324
1325 #address-cells = <1>;
1326 #size-cells = <0>;
1327
1328 emc-table@25000 {
1329 reg = <25000>;
1330 compatible = "nvidia,tegra20-emc-table";
1331 clock-frequency = <25000>;
1332 nvidia,emc-registers = <0x00000002 0x00000006
1333 0x00000003 0x00000003 0x00000006 0x00000004
1334 0x00000002 0x00000009 0x00000003 0x00000003
1335 0x00000002 0x00000002 0x00000002 0x00000004
1336 0x00000003 0x00000008 0x0000000b 0x0000004d
1337 0x00000000 0x00000003 0x00000003 0x00000003
1338 0x00000008 0x00000001 0x0000000a 0x00000004
1339 0x00000003 0x00000008 0x00000004 0x00000006
1340 0x00000002 0x00000068 0x00000000 0x00000003
1341 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1342 0x00070000 0x00000000 0x00000000 0x00000003
1343 0x00000000 0x00000000 0x00000000 0x00000000>;
1344 };
1345
1346 emc-table@50000 {
1347 reg = <50000>;
1348 compatible = "nvidia,tegra20-emc-table";
1349 clock-frequency = <50000>;
1350 nvidia,emc-registers = <0x00000003 0x00000007
1351 0x00000003 0x00000003 0x00000006 0x00000004
1352 0x00000002 0x00000009 0x00000003 0x00000003
1353 0x00000002 0x00000002 0x00000002 0x00000005
1354 0x00000003 0x00000008 0x0000000b 0x0000009f
1355 0x00000000 0x00000003 0x00000003 0x00000003
1356 0x00000008 0x00000001 0x0000000a 0x00000007
1357 0x00000003 0x00000008 0x00000004 0x00000006
1358 0x00000002 0x000000d0 0x00000000 0x00000000
1359 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1360 0x00070000 0x00000000 0x00000000 0x00000005
1361 0x00000000 0x00000000 0x00000000 0x00000000>;
1362 };
1363
1364 emc-table@75000 {
1365 reg = <75000>;
1366 compatible = "nvidia,tegra20-emc-table";
1367 clock-frequency = <75000>;
1368 nvidia,emc-registers = <0x00000005 0x0000000a
1369 0x00000004 0x00000003 0x00000006 0x00000004
1370 0x00000002 0x00000009 0x00000003 0x00000003
1371 0x00000002 0x00000002 0x00000002 0x00000005
1372 0x00000003 0x00000008 0x0000000b 0x000000ff
1373 0x00000000 0x00000003 0x00000003 0x00000003
1374 0x00000008 0x00000001 0x0000000a 0x0000000b
1375 0x00000003 0x00000008 0x00000004 0x00000006
1376 0x00000002 0x00000138 0x00000000 0x00000000
1377 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1378 0x00070000 0x00000000 0x00000000 0x00000007
1379 0x00000000 0x00000000 0x00000000 0x00000000>;
1380 };
1381
1382 emc-table@150000 {
1383 reg = <150000>;
1384 compatible = "nvidia,tegra20-emc-table";
1385 clock-frequency = <150000>;
1386 nvidia,emc-registers = <0x00000009 0x00000014
1387 0x00000007 0x00000003 0x00000006 0x00000004
1388 0x00000002 0x00000009 0x00000003 0x00000003
1389 0x00000002 0x00000002 0x00000002 0x00000005
1390 0x00000003 0x00000008 0x0000000b 0x0000021f
1391 0x00000000 0x00000003 0x00000003 0x00000003
1392 0x00000008 0x00000001 0x0000000a 0x00000015
1393 0x00000003 0x00000008 0x00000004 0x00000006
1394 0x00000002 0x00000270 0x00000000 0x00000001
1395 0x00000000 0x00000000 0x00000282 0xa07c04ae
1396 0x007dd010 0x00000000 0x00000000 0x0000000e
1397 0x00000000 0x00000000 0x00000000 0x00000000>;
1398 };
1399
1400 emc-table@300000 {
1401 reg = <300000>;
1402 compatible = "nvidia,tegra20-emc-table";
1403 clock-frequency = <300000>;
1404 nvidia,emc-registers = <0x00000012 0x00000027
1405 0x0000000d 0x00000006 0x00000007 0x00000005
1406 0x00000003 0x00000009 0x00000006 0x00000006
1407 0x00000003 0x00000003 0x00000002 0x00000006
1408 0x00000003 0x00000009 0x0000000c 0x0000045f
1409 0x00000000 0x00000004 0x00000004 0x00000006
1410 0x00000008 0x00000001 0x0000000e 0x0000002a
1411 0x00000003 0x0000000f 0x00000007 0x00000005
1412 0x00000002 0x000004e1 0x00000005 0x00000002
1413 0x00000000 0x00000000 0x00000282 0xe059048b
1414 0x007e2010 0x00000000 0x00000000 0x0000001b
1415 0x00000000 0x00000000 0x00000000 0x00000000>;
1416 };
1417 };
1418
1419 emc-tables@3 {
1420 nvidia,ram-code = <3>; /* hynix-4gb */
1421 reg = <3>;
1422
1423 #address-cells = <1>;
1424 #size-cells = <0>;
1425
1426 emc-table@25000 {
1427 reg = <25000>;
1428 compatible = "nvidia,tegra20-emc-table";
1429 clock-frequency = <25000>;
1430 nvidia,emc-registers = <0x00000002 0x00000006
1431 0x00000003 0x00000003 0x00000006 0x00000004
1432 0x00000002 0x00000009 0x00000003 0x00000003
1433 0x00000002 0x00000002 0x00000002 0x00000004
1434 0x00000003 0x00000008 0x0000000b 0x0000004d
1435 0x00000000 0x00000003 0x00000003 0x00000003
1436 0x00000008 0x00000001 0x0000000a 0x00000004
1437 0x00000003 0x00000008 0x00000004 0x00000006
1438 0x00000002 0x00000068 0x00000000 0x00000003
1439 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1440 0x0007c000 0x00000000 0x00000000 0x00000003
1441 0x00000000 0x00000000 0x00000000 0x00000000>;
1442 };
1443
1444 emc-table@50000 {
1445 reg = <50000>;
1446 compatible = "nvidia,tegra20-emc-table";
1447 clock-frequency = <50000>;
1448 nvidia,emc-registers = <0x00000003 0x00000007
1449 0x00000003 0x00000003 0x00000006 0x00000004
1450 0x00000002 0x00000009 0x00000003 0x00000003
1451 0x00000002 0x00000002 0x00000002 0x00000005
1452 0x00000003 0x00000008 0x0000000b 0x0000009f
1453 0x00000000 0x00000003 0x00000003 0x00000003
1454 0x00000008 0x00000001 0x0000000a 0x00000007
1455 0x00000003 0x00000008 0x00000004 0x00000006
1456 0x00000002 0x000000d0 0x00000000 0x00000000
1457 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1458 0x0007c000 0x00078000 0x00000000 0x00000005
1459 0x00000000 0x00000000 0x00000000 0x00000000>;
1460 };
1461
1462 emc-table@75000 {
1463 reg = <75000>;
1464 compatible = "nvidia,tegra20-emc-table";
1465 clock-frequency = <75000>;
1466 nvidia,emc-registers = <0x00000005 0x0000000a
1467 0x00000004 0x00000003 0x00000006 0x00000004
1468 0x00000002 0x00000009 0x00000003 0x00000003
1469 0x00000002 0x00000002 0x00000002 0x00000005
1470 0x00000003 0x00000008 0x0000000b 0x000000ff
1471 0x00000000 0x00000003 0x00000003 0x00000003
1472 0x00000008 0x00000001 0x0000000a 0x0000000b
1473 0x00000003 0x00000008 0x00000004 0x00000006
1474 0x00000002 0x00000138 0x00000000 0x00000000
1475 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1476 0x0007c000 0x00000000 0x00000000 0x00000007
1477 0x00000000 0x00000000 0x00000000 0x00000000>;
1478 };
1479
1480 emc-table@150000 {
1481 reg = <150000>;
1482 compatible = "nvidia,tegra20-emc-table";
1483 clock-frequency = <150000>;
1484 nvidia,emc-registers = <0x00000009 0x00000014
1485 0x00000007 0x00000003 0x00000006 0x00000004
1486 0x00000002 0x00000009 0x00000003 0x00000003
1487 0x00000002 0x00000002 0x00000002 0x00000005
1488 0x00000003 0x00000008 0x0000000b 0x0000021f
1489 0x00000000 0x00000003 0x00000003 0x00000003
1490 0x00000008 0x00000001 0x0000000a 0x00000015
1491 0x00000003 0x00000008 0x00000004 0x00000006
1492 0x00000002 0x00000270 0x00000000 0x00000001
1493 0x00000000 0x00000000 0x00000282 0xa07c04ae
1494 0x007e4010 0x00000000 0x00000000 0x0000000e
1495 0x00000000 0x00000000 0x00000000 0x00000000>;
1496 };
1497
1498 emc-table@300000 {
1499 reg = <300000>;
1500 compatible = "nvidia,tegra20-emc-table";
1501 clock-frequency = <300000>;
1502 nvidia,emc-registers = <0x00000012 0x00000027
1503 0x0000000d 0x00000006 0x00000007 0x00000005
1504 0x00000003 0x00000009 0x00000006 0x00000006
1505 0x00000003 0x00000003 0x00000002 0x00000006
1506 0x00000003 0x00000009 0x0000000c 0x0000045f
1507 0x00000000 0x00000004 0x00000004 0x00000006
1508 0x00000008 0x00000001 0x0000000e 0x0000002a
1509 0x00000003 0x0000000f 0x00000007 0x00000005
1510 0x00000002 0x000004e1 0x00000005 0x00000002
1511 0x00000000 0x00000000 0x00000282 0xe059048b
1512 0x007e0010 0x00000000 0x00000000 0x0000001b
1513 0x00000000 0x00000000 0x00000000 0x00000000>;
1514 };
1515 };
1516 };
1517 };
1518
1519 &emc_icc_dvfs_opp_table {
1520 /delete-node/ opp-666000000;
1521 /delete-node/ opp-760000000;
1522 };
