0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <dt-bindings/clock/tegra124-car.h>
0003 #include <dt-bindings/gpio/tegra-gpio.h>
0004 #include <dt-bindings/memory/tegra124-mc.h>
0005 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
0006 #include <dt-bindings/interrupt-controller/arm-gic.h>
0007 #include <dt-bindings/reset/tegra124-car.h>
0008 #include <dt-bindings/thermal/tegra124-soctherm.h>
0009 #include <dt-bindings/soc/tegra-pmc.h>
0010
0011 #include "tegra124-peripherals-opp.dtsi"
0012
0013 / {
0014 compatible = "nvidia,tegra124";
0015 interrupt-parent = <&lic>;
0016 #address-cells = <2>;
0017 #size-cells = <2>;
0018
0019 memory@80000000 {
0020 device_type = "memory";
0021 reg = <0x0 0x80000000 0x0 0x0>;
0022 };
0023
0024 pcie@1003000 {
0025 compatible = "nvidia,tegra124-pcie";
0026 device_type = "pci";
0027 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
0028 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
0029 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
0030 reg-names = "pads", "afi", "cs";
0031 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
0032 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
0033 interrupt-names = "intr", "msi";
0034
0035 #interrupt-cells = <1>;
0036 interrupt-map-mask = <0 0 0 0>;
0037 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
0038
0039 bus-range = <0x00 0xff>;
0040 #address-cells = <3>;
0041 #size-cells = <2>;
0042
0043 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
0044 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
0045 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
0046 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
0047 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
0048
0049 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
0050 <&tegra_car TEGRA124_CLK_AFI>,
0051 <&tegra_car TEGRA124_CLK_PLL_E>,
0052 <&tegra_car TEGRA124_CLK_CML0>;
0053 clock-names = "pex", "afi", "pll_e", "cml";
0054 resets = <&tegra_car 70>,
0055 <&tegra_car 72>,
0056 <&tegra_car 74>;
0057 reset-names = "pex", "afi", "pcie_x";
0058 status = "disabled";
0059
0060 pci@1,0 {
0061 device_type = "pci";
0062 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
0063 reg = <0x000800 0 0 0 0>;
0064 bus-range = <0x00 0xff>;
0065 status = "disabled";
0066
0067 #address-cells = <3>;
0068 #size-cells = <2>;
0069 ranges;
0070
0071 nvidia,num-lanes = <2>;
0072 };
0073
0074 pci@2,0 {
0075 device_type = "pci";
0076 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
0077 reg = <0x001000 0 0 0 0>;
0078 bus-range = <0x00 0xff>;
0079 status = "disabled";
0080
0081 #address-cells = <3>;
0082 #size-cells = <2>;
0083 ranges;
0084
0085 nvidia,num-lanes = <1>;
0086 };
0087 };
0088
0089 host1x@50000000 {
0090 compatible = "nvidia,tegra124-host1x";
0091 reg = <0x0 0x50000000 0x0 0x00034000>;
0092 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
0093 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
0094 interrupt-names = "syncpt", "host1x";
0095 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
0096 clock-names = "host1x";
0097 resets = <&tegra_car 28>, <&mc TEGRA124_MC_RESET_HC>;
0098 reset-names = "host1x", "mc";
0099 iommus = <&mc TEGRA_SWGROUP_HC>;
0100
0101 #address-cells = <2>;
0102 #size-cells = <2>;
0103
0104 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
0105
0106 dc@54200000 {
0107 compatible = "nvidia,tegra124-dc";
0108 reg = <0x0 0x54200000 0x0 0x00040000>;
0109 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0110 clocks = <&tegra_car TEGRA124_CLK_DISP1>;
0111 clock-names = "dc";
0112 resets = <&tegra_car 27>;
0113 reset-names = "dc";
0114
0115 iommus = <&mc TEGRA_SWGROUP_DC>;
0116
0117 nvidia,head = <0>;
0118
0119 interconnects = <&mc TEGRA124_MC_DISPLAY0A &emc>,
0120 <&mc TEGRA124_MC_DISPLAY0B &emc>,
0121 <&mc TEGRA124_MC_DISPLAY0C &emc>,
0122 <&mc TEGRA124_MC_DISPLAYHC &emc>,
0123 <&mc TEGRA124_MC_DISPLAYD &emc>,
0124 <&mc TEGRA124_MC_DISPLAYT &emc>;
0125 interconnect-names = "wina",
0126 "winb",
0127 "winc",
0128 "cursor",
0129 "wind",
0130 "wint";
0131 };
0132
0133 dc@54240000 {
0134 compatible = "nvidia,tegra124-dc";
0135 reg = <0x0 0x54240000 0x0 0x00040000>;
0136 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0137 clocks = <&tegra_car TEGRA124_CLK_DISP2>;
0138 clock-names = "dc";
0139 resets = <&tegra_car 26>;
0140 reset-names = "dc";
0141
0142 iommus = <&mc TEGRA_SWGROUP_DCB>;
0143
0144 nvidia,head = <1>;
0145
0146 interconnects = <&mc TEGRA124_MC_DISPLAY0AB &emc>,
0147 <&mc TEGRA124_MC_DISPLAY0BB &emc>,
0148 <&mc TEGRA124_MC_DISPLAY0CB &emc>,
0149 <&mc TEGRA124_MC_DISPLAYHCB &emc>;
0150 interconnect-names = "wina",
0151 "winb",
0152 "winc",
0153 "cursor";
0154 };
0155
0156 hdmi: hdmi@54280000 {
0157 compatible = "nvidia,tegra124-hdmi";
0158 reg = <0x0 0x54280000 0x0 0x00040000>;
0159 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0160 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
0161 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
0162 clock-names = "hdmi", "parent";
0163 resets = <&tegra_car 51>;
0164 reset-names = "hdmi";
0165 status = "disabled";
0166 };
0167
0168 vic@54340000 {
0169 compatible = "nvidia,tegra124-vic";
0170 reg = <0x0 0x54340000 0x0 0x00040000>;
0171 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0172 clocks = <&tegra_car TEGRA124_CLK_VIC03>;
0173 clock-names = "vic";
0174 resets = <&tegra_car 178>;
0175 reset-names = "vic";
0176
0177 iommus = <&mc TEGRA_SWGROUP_VIC>;
0178 };
0179
0180 sor@54540000 {
0181 compatible = "nvidia,tegra124-sor";
0182 reg = <0x0 0x54540000 0x0 0x00040000>;
0183 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0184 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
0185 <&tegra_car TEGRA124_CLK_SOR0_OUT>,
0186 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
0187 <&tegra_car TEGRA124_CLK_PLL_DP>,
0188 <&tegra_car TEGRA124_CLK_CLK_M>;
0189 clock-names = "sor", "out", "parent", "dp", "safe";
0190 resets = <&tegra_car 182>;
0191 reset-names = "sor";
0192 status = "disabled";
0193 };
0194
0195 dpaux: dpaux@545c0000 {
0196 compatible = "nvidia,tegra124-dpaux";
0197 reg = <0x0 0x545c0000 0x0 0x00040000>;
0198 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
0199 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
0200 <&tegra_car TEGRA124_CLK_PLL_DP>;
0201 clock-names = "dpaux", "parent";
0202 resets = <&tegra_car 181>;
0203 reset-names = "dpaux";
0204 status = "disabled";
0205
0206 i2c-bus {
0207 #address-cells = <1>;
0208 #size-cells = <0>;
0209 };
0210 };
0211 };
0212
0213 gic: interrupt-controller@50041000 {
0214 compatible = "arm,cortex-a15-gic";
0215 #interrupt-cells = <3>;
0216 interrupt-controller;
0217 reg = <0x0 0x50041000 0x0 0x1000>,
0218 <0x0 0x50042000 0x0 0x1000>,
0219 <0x0 0x50044000 0x0 0x2000>,
0220 <0x0 0x50046000 0x0 0x2000>;
0221 interrupts = <GIC_PPI 9
0222 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0223 interrupt-parent = <&gic>;
0224 };
0225
0226 gpu@57000000 {
0227 compatible = "nvidia,gk20a";
0228 reg = <0x0 0x57000000 0x0 0x01000000>,
0229 <0x0 0x58000000 0x0 0x01000000>;
0230 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
0231 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
0232 interrupt-names = "stall", "nonstall";
0233 clocks = <&tegra_car TEGRA124_CLK_GPU>,
0234 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
0235 clock-names = "gpu", "pwr";
0236 resets = <&tegra_car 184>;
0237 reset-names = "gpu";
0238
0239 iommus = <&mc TEGRA_SWGROUP_GPU>;
0240
0241 status = "disabled";
0242 };
0243
0244 lic: interrupt-controller@60004000 {
0245 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
0246 reg = <0x0 0x60004000 0x0 0x100>,
0247 <0x0 0x60004100 0x0 0x100>,
0248 <0x0 0x60004200 0x0 0x100>,
0249 <0x0 0x60004300 0x0 0x100>,
0250 <0x0 0x60004400 0x0 0x100>;
0251 interrupt-controller;
0252 #interrupt-cells = <3>;
0253 interrupt-parent = <&gic>;
0254 };
0255
0256 timer@60005000 {
0257 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer";
0258 reg = <0x0 0x60005000 0x0 0x400>;
0259 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0260 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0261 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
0262 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
0263 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
0264 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
0265 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
0266 };
0267
0268 tegra_car: clock@60006000 {
0269 compatible = "nvidia,tegra124-car";
0270 reg = <0x0 0x60006000 0x0 0x1000>;
0271 #clock-cells = <1>;
0272 #reset-cells = <1>;
0273 nvidia,external-memory-controller = <&emc>;
0274 };
0275
0276 flow-controller@60007000 {
0277 compatible = "nvidia,tegra124-flowctrl";
0278 reg = <0x0 0x60007000 0x0 0x1000>;
0279 };
0280
0281 actmon: actmon@6000c800 {
0282 compatible = "nvidia,tegra124-actmon";
0283 reg = <0x0 0x6000c800 0x0 0x400>;
0284 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0285 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
0286 <&tegra_car TEGRA124_CLK_EMC>;
0287 clock-names = "actmon", "emc";
0288 resets = <&tegra_car 119>;
0289 reset-names = "actmon";
0290 operating-points-v2 = <&emc_bw_dfs_opp_table>;
0291 interconnects = <&mc TEGRA124_MC_MPCORER &emc>;
0292 interconnect-names = "cpu-read";
0293 #cooling-cells = <2>;
0294 };
0295
0296 gpio: gpio@6000d000 {
0297 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
0298 reg = <0x0 0x6000d000 0x0 0x1000>;
0299 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
0300 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
0301 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
0302 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
0303 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
0304 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0305 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
0306 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
0307 #gpio-cells = <2>;
0308 gpio-controller;
0309 #interrupt-cells = <2>;
0310 interrupt-controller;
0311 gpio-ranges = <&pinmux 0 0 251>;
0312 };
0313
0314 apbdma: dma@60020000 {
0315 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
0316 reg = <0x0 0x60020000 0x0 0x1400>;
0317 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0318 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
0319 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
0320 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
0321 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
0322 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
0323 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
0324 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
0325 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
0326 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
0327 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
0328 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
0329 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
0330 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
0331 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
0332 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
0333 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
0334 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
0335 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
0336 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
0337 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
0338 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
0339 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
0340 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
0341 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
0342 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
0343 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
0344 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
0345 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
0346 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
0347 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
0348 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0349 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
0350 resets = <&tegra_car 34>;
0351 reset-names = "dma";
0352 #dma-cells = <1>;
0353 };
0354
0355 apbmisc@70000800 {
0356 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
0357 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
0358 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
0359 };
0360
0361 pinmux: pinmux@70000868 {
0362 compatible = "nvidia,tegra124-pinmux";
0363 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
0364 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
0365 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
0366 };
0367
0368 /*
0369 * There are two serial driver i.e. 8250 based simple serial
0370 * driver and APB DMA based serial driver for higher baudrate
0371 * and performace. To enable the 8250 based driver, the compatible
0372 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
0373 * the APB DMA based serial driver, the compatible is
0374 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
0375 */
0376 uarta: serial@70006000 {
0377 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
0378 reg = <0x0 0x70006000 0x0 0x40>;
0379 reg-shift = <2>;
0380 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0381 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
0382 resets = <&tegra_car 6>;
0383 reset-names = "serial";
0384 dmas = <&apbdma 8>, <&apbdma 8>;
0385 dma-names = "rx", "tx";
0386 status = "disabled";
0387 };
0388
0389 uartb: serial@70006040 {
0390 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
0391 reg = <0x0 0x70006040 0x0 0x40>;
0392 reg-shift = <2>;
0393 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0394 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
0395 resets = <&tegra_car 7>;
0396 reset-names = "serial";
0397 dmas = <&apbdma 9>, <&apbdma 9>;
0398 dma-names = "rx", "tx";
0399 status = "disabled";
0400 };
0401
0402 uartc: serial@70006200 {
0403 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
0404 reg = <0x0 0x70006200 0x0 0x40>;
0405 reg-shift = <2>;
0406 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0407 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
0408 resets = <&tegra_car 55>;
0409 reset-names = "serial";
0410 dmas = <&apbdma 10>, <&apbdma 10>;
0411 dma-names = "rx", "tx";
0412 status = "disabled";
0413 };
0414
0415 uartd: serial@70006300 {
0416 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
0417 reg = <0x0 0x70006300 0x0 0x40>;
0418 reg-shift = <2>;
0419 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0420 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
0421 resets = <&tegra_car 65>;
0422 reset-names = "serial";
0423 dmas = <&apbdma 19>, <&apbdma 19>;
0424 dma-names = "rx", "tx";
0425 status = "disabled";
0426 };
0427
0428 pwm: pwm@7000a000 {
0429 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
0430 reg = <0x0 0x7000a000 0x0 0x100>;
0431 #pwm-cells = <2>;
0432 clocks = <&tegra_car TEGRA124_CLK_PWM>;
0433 resets = <&tegra_car 17>;
0434 reset-names = "pwm";
0435 status = "disabled";
0436 };
0437
0438 i2c@7000c000 {
0439 compatible = "nvidia,tegra124-i2c";
0440 reg = <0x0 0x7000c000 0x0 0x100>;
0441 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0442 #address-cells = <1>;
0443 #size-cells = <0>;
0444 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
0445 clock-names = "div-clk";
0446 resets = <&tegra_car 12>;
0447 reset-names = "i2c";
0448 dmas = <&apbdma 21>, <&apbdma 21>;
0449 dma-names = "rx", "tx";
0450 status = "disabled";
0451 };
0452
0453 i2c@7000c400 {
0454 compatible = "nvidia,tegra124-i2c";
0455 reg = <0x0 0x7000c400 0x0 0x100>;
0456 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0457 #address-cells = <1>;
0458 #size-cells = <0>;
0459 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
0460 clock-names = "div-clk";
0461 resets = <&tegra_car 54>;
0462 reset-names = "i2c";
0463 dmas = <&apbdma 22>, <&apbdma 22>;
0464 dma-names = "rx", "tx";
0465 status = "disabled";
0466 };
0467
0468 i2c@7000c500 {
0469 compatible = "nvidia,tegra124-i2c";
0470 reg = <0x0 0x7000c500 0x0 0x100>;
0471 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0472 #address-cells = <1>;
0473 #size-cells = <0>;
0474 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
0475 clock-names = "div-clk";
0476 resets = <&tegra_car 67>;
0477 reset-names = "i2c";
0478 dmas = <&apbdma 23>, <&apbdma 23>;
0479 dma-names = "rx", "tx";
0480 status = "disabled";
0481 };
0482
0483 i2c@7000c700 {
0484 compatible = "nvidia,tegra124-i2c";
0485 reg = <0x0 0x7000c700 0x0 0x100>;
0486 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
0487 #address-cells = <1>;
0488 #size-cells = <0>;
0489 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
0490 clock-names = "div-clk";
0491 resets = <&tegra_car 103>;
0492 reset-names = "i2c";
0493 dmas = <&apbdma 26>, <&apbdma 26>;
0494 dma-names = "rx", "tx";
0495 status = "disabled";
0496 };
0497
0498 i2c@7000d000 {
0499 compatible = "nvidia,tegra124-i2c";
0500 reg = <0x0 0x7000d000 0x0 0x100>;
0501 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
0502 #address-cells = <1>;
0503 #size-cells = <0>;
0504 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
0505 clock-names = "div-clk";
0506 resets = <&tegra_car 47>;
0507 reset-names = "i2c";
0508 dmas = <&apbdma 24>, <&apbdma 24>;
0509 dma-names = "rx", "tx";
0510 status = "disabled";
0511 };
0512
0513 i2c@7000d100 {
0514 compatible = "nvidia,tegra124-i2c";
0515 reg = <0x0 0x7000d100 0x0 0x100>;
0516 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0517 #address-cells = <1>;
0518 #size-cells = <0>;
0519 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
0520 clock-names = "div-clk";
0521 resets = <&tegra_car 166>;
0522 reset-names = "i2c";
0523 dmas = <&apbdma 30>, <&apbdma 30>;
0524 dma-names = "rx", "tx";
0525 status = "disabled";
0526 };
0527
0528 spi@7000d400 {
0529 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
0530 reg = <0x0 0x7000d400 0x0 0x200>;
0531 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
0532 #address-cells = <1>;
0533 #size-cells = <0>;
0534 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
0535 clock-names = "spi";
0536 resets = <&tegra_car 41>;
0537 reset-names = "spi";
0538 dmas = <&apbdma 15>, <&apbdma 15>;
0539 dma-names = "rx", "tx";
0540 status = "disabled";
0541 };
0542
0543 spi@7000d600 {
0544 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
0545 reg = <0x0 0x7000d600 0x0 0x200>;
0546 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0547 #address-cells = <1>;
0548 #size-cells = <0>;
0549 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
0550 clock-names = "spi";
0551 resets = <&tegra_car 44>;
0552 reset-names = "spi";
0553 dmas = <&apbdma 16>, <&apbdma 16>;
0554 dma-names = "rx", "tx";
0555 status = "disabled";
0556 };
0557
0558 spi@7000d800 {
0559 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
0560 reg = <0x0 0x7000d800 0x0 0x200>;
0561 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0562 #address-cells = <1>;
0563 #size-cells = <0>;
0564 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
0565 clock-names = "spi";
0566 resets = <&tegra_car 46>;
0567 reset-names = "spi";
0568 dmas = <&apbdma 17>, <&apbdma 17>;
0569 dma-names = "rx", "tx";
0570 status = "disabled";
0571 };
0572
0573 spi@7000da00 {
0574 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
0575 reg = <0x0 0x7000da00 0x0 0x200>;
0576 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
0577 #address-cells = <1>;
0578 #size-cells = <0>;
0579 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
0580 clock-names = "spi";
0581 resets = <&tegra_car 68>;
0582 reset-names = "spi";
0583 dmas = <&apbdma 18>, <&apbdma 18>;
0584 dma-names = "rx", "tx";
0585 status = "disabled";
0586 };
0587
0588 spi@7000dc00 {
0589 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
0590 reg = <0x0 0x7000dc00 0x0 0x200>;
0591 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0592 #address-cells = <1>;
0593 #size-cells = <0>;
0594 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
0595 clock-names = "spi";
0596 resets = <&tegra_car 104>;
0597 reset-names = "spi";
0598 dmas = <&apbdma 27>, <&apbdma 27>;
0599 dma-names = "rx", "tx";
0600 status = "disabled";
0601 };
0602
0603 spi@7000de00 {
0604 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
0605 reg = <0x0 0x7000de00 0x0 0x200>;
0606 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0607 #address-cells = <1>;
0608 #size-cells = <0>;
0609 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
0610 clock-names = "spi";
0611 resets = <&tegra_car 105>;
0612 reset-names = "spi";
0613 dmas = <&apbdma 28>, <&apbdma 28>;
0614 dma-names = "rx", "tx";
0615 status = "disabled";
0616 };
0617
0618 rtc@7000e000 {
0619 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
0620 reg = <0x0 0x7000e000 0x0 0x100>;
0621 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0622 clocks = <&tegra_car TEGRA124_CLK_RTC>;
0623 };
0624
0625 tegra_pmc: pmc@7000e400 {
0626 compatible = "nvidia,tegra124-pmc";
0627 reg = <0x0 0x7000e400 0x0 0x400>;
0628 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
0629 clock-names = "pclk", "clk32k_in";
0630 #clock-cells = <1>;
0631 };
0632
0633 fuse@7000f800 {
0634 compatible = "nvidia,tegra124-efuse";
0635 reg = <0x0 0x7000f800 0x0 0x400>;
0636 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
0637 clock-names = "fuse";
0638 resets = <&tegra_car 39>;
0639 reset-names = "fuse";
0640 };
0641
0642 mc: memory-controller@70019000 {
0643 compatible = "nvidia,tegra124-mc";
0644 reg = <0x0 0x70019000 0x0 0x1000>;
0645 clocks = <&tegra_car TEGRA124_CLK_MC>;
0646 clock-names = "mc";
0647
0648 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0649
0650 #iommu-cells = <1>;
0651 #reset-cells = <1>;
0652 #interconnect-cells = <1>;
0653 };
0654
0655 emc: external-memory-controller@7001b000 {
0656 compatible = "nvidia,tegra124-emc";
0657 reg = <0x0 0x7001b000 0x0 0x1000>;
0658 clocks = <&tegra_car TEGRA124_CLK_EMC>;
0659 clock-names = "emc";
0660
0661 nvidia,memory-controller = <&mc>;
0662 operating-points-v2 = <&emc_icc_dvfs_opp_table>;
0663
0664 #interconnect-cells = <0>;
0665 };
0666
0667 sata@70020000 {
0668 compatible = "nvidia,tegra124-ahci";
0669 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
0670 <0x0 0x70020000 0x0 0x7000>; /* SATA */
0671 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0672 clocks = <&tegra_car TEGRA124_CLK_SATA>,
0673 <&tegra_car TEGRA124_CLK_SATA_OOB>;
0674 clock-names = "sata", "sata-oob";
0675 resets = <&tegra_car 124>,
0676 <&tegra_car 129>,
0677 <&tegra_car 123>;
0678 reset-names = "sata", "sata-cold", "sata-oob";
0679 status = "disabled";
0680 };
0681
0682 hda@70030000 {
0683 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
0684 reg = <0x0 0x70030000 0x0 0x10000>;
0685 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
0686 clocks = <&tegra_car TEGRA124_CLK_HDA>,
0687 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
0688 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
0689 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
0690 resets = <&tegra_car 125>, /* hda */
0691 <&tegra_car 128>, /* hda2hdmi */
0692 <&tegra_car 111>; /* hda2codec_2x */
0693 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
0694 status = "disabled";
0695 };
0696
0697 usb@70090000 {
0698 compatible = "nvidia,tegra124-xusb";
0699 reg = <0x0 0x70090000 0x0 0x8000>,
0700 <0x0 0x70098000 0x0 0x1000>,
0701 <0x0 0x70099000 0x0 0x1000>;
0702 reg-names = "hcd", "fpci", "ipfs";
0703
0704 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
0705 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
0706
0707 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
0708 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
0709 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
0710 <&tegra_car TEGRA124_CLK_XUSB_SS>,
0711 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
0712 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
0713 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
0714 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
0715 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
0716 <&tegra_car TEGRA124_CLK_CLK_M>,
0717 <&tegra_car TEGRA124_CLK_PLL_E>;
0718 clock-names = "xusb_host", "xusb_host_src",
0719 "xusb_falcon_src", "xusb_ss",
0720 "xusb_ss_div2", "xusb_ss_src",
0721 "xusb_hs_src", "xusb_fs_src",
0722 "pll_u_480m", "clk_m", "pll_e";
0723 resets = <&tegra_car 89>, <&tegra_car 156>,
0724 <&tegra_car 143>;
0725 reset-names = "xusb_host", "xusb_ss", "xusb_src";
0726
0727 nvidia,xusb-padctl = <&padctl>;
0728
0729 status = "disabled";
0730 };
0731
0732 padctl: padctl@7009f000 {
0733 compatible = "nvidia,tegra124-xusb-padctl";
0734 reg = <0x0 0x7009f000 0x0 0x1000>;
0735 resets = <&tegra_car 142>;
0736 reset-names = "padctl";
0737
0738 pads {
0739 usb2 {
0740 status = "disabled";
0741
0742 lanes {
0743 usb2-0 {
0744 status = "disabled";
0745 #phy-cells = <0>;
0746 };
0747
0748 usb2-1 {
0749 status = "disabled";
0750 #phy-cells = <0>;
0751 };
0752
0753 usb2-2 {
0754 status = "disabled";
0755 #phy-cells = <0>;
0756 };
0757 };
0758 };
0759
0760 ulpi {
0761 status = "disabled";
0762
0763 lanes {
0764 ulpi-0 {
0765 status = "disabled";
0766 #phy-cells = <0>;
0767 };
0768 };
0769 };
0770
0771 hsic {
0772 status = "disabled";
0773
0774 lanes {
0775 hsic-0 {
0776 status = "disabled";
0777 #phy-cells = <0>;
0778 };
0779
0780 hsic-1 {
0781 status = "disabled";
0782 #phy-cells = <0>;
0783 };
0784 };
0785 };
0786
0787 pcie {
0788 status = "disabled";
0789
0790 lanes {
0791 pcie-0 {
0792 status = "disabled";
0793 #phy-cells = <0>;
0794 };
0795
0796 pcie-1 {
0797 status = "disabled";
0798 #phy-cells = <0>;
0799 };
0800
0801 pcie-2 {
0802 status = "disabled";
0803 #phy-cells = <0>;
0804 };
0805
0806 pcie-3 {
0807 status = "disabled";
0808 #phy-cells = <0>;
0809 };
0810
0811 pcie-4 {
0812 status = "disabled";
0813 #phy-cells = <0>;
0814 };
0815 };
0816 };
0817
0818 sata {
0819 status = "disabled";
0820
0821 lanes {
0822 sata-0 {
0823 status = "disabled";
0824 #phy-cells = <0>;
0825 };
0826 };
0827 };
0828 };
0829
0830 ports {
0831 usb2-0 {
0832 status = "disabled";
0833 };
0834
0835 usb2-1 {
0836 status = "disabled";
0837 };
0838
0839 usb2-2 {
0840 status = "disabled";
0841 };
0842
0843 ulpi-0 {
0844 status = "disabled";
0845 };
0846
0847 hsic-0 {
0848 status = "disabled";
0849 };
0850
0851 hsic-1 {
0852 status = "disabled";
0853 };
0854
0855 usb3-0 {
0856 status = "disabled";
0857 };
0858
0859 usb3-1 {
0860 status = "disabled";
0861 };
0862 };
0863 };
0864
0865 mmc@700b0000 {
0866 compatible = "nvidia,tegra124-sdhci";
0867 reg = <0x0 0x700b0000 0x0 0x200>;
0868 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0869 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
0870 clock-names = "sdhci";
0871 resets = <&tegra_car 14>;
0872 reset-names = "sdhci";
0873 status = "disabled";
0874 };
0875
0876 mmc@700b0200 {
0877 compatible = "nvidia,tegra124-sdhci";
0878 reg = <0x0 0x700b0200 0x0 0x200>;
0879 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0880 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
0881 clock-names = "sdhci";
0882 resets = <&tegra_car 9>;
0883 reset-names = "sdhci";
0884 status = "disabled";
0885 };
0886
0887 mmc@700b0400 {
0888 compatible = "nvidia,tegra124-sdhci";
0889 reg = <0x0 0x700b0400 0x0 0x200>;
0890 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0891 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
0892 clock-names = "sdhci";
0893 resets = <&tegra_car 69>;
0894 reset-names = "sdhci";
0895 status = "disabled";
0896 };
0897
0898 mmc@700b0600 {
0899 compatible = "nvidia,tegra124-sdhci";
0900 reg = <0x0 0x700b0600 0x0 0x200>;
0901 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0902 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
0903 clock-names = "sdhci";
0904 resets = <&tegra_car 15>;
0905 reset-names = "sdhci";
0906 status = "disabled";
0907 };
0908
0909 cec@70015000 {
0910 compatible = "nvidia,tegra124-cec";
0911 reg = <0x0 0x70015000 0x0 0x00001000>;
0912 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0913 clocks = <&tegra_car TEGRA124_CLK_CEC>;
0914 clock-names = "cec";
0915 status = "disabled";
0916 hdmi-phandle = <&hdmi>;
0917 };
0918
0919 soctherm: thermal-sensor@700e2000 {
0920 compatible = "nvidia,tegra124-soctherm";
0921 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
0922 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
0923 reg-names = "soctherm-reg", "car-reg";
0924 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
0925 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
0926 interrupt-names = "thermal", "edp";
0927 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
0928 <&tegra_car TEGRA124_CLK_SOC_THERM>;
0929 clock-names = "tsensor", "soctherm";
0930 resets = <&tegra_car 78>;
0931 reset-names = "soctherm";
0932 #thermal-sensor-cells = <1>;
0933
0934 throttle-cfgs {
0935 throttle_heavy: heavy {
0936 nvidia,priority = <100>;
0937 nvidia,cpu-throt-percent = <85>;
0938 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
0939
0940 #cooling-cells = <2>;
0941 };
0942 };
0943 };
0944
0945 dfll: clock@70110000 {
0946 compatible = "nvidia,tegra124-dfll";
0947 reg = <0 0x70110000 0 0x100>, /* DFLL control */
0948 <0 0x70110000 0 0x100>, /* I2C output control */
0949 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
0950 <0 0x70110200 0 0x100>; /* Look-up table RAM */
0951 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0952 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
0953 <&tegra_car TEGRA124_CLK_DFLL_REF>,
0954 <&tegra_car TEGRA124_CLK_I2C5>;
0955 clock-names = "soc", "ref", "i2c";
0956 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
0957 reset-names = "dvco";
0958 #clock-cells = <0>;
0959 clock-output-names = "dfllCPU_out";
0960 nvidia,sample-rate = <12500>;
0961 nvidia,droop-ctrl = <0x00000f00>;
0962 nvidia,force-mode = <1>;
0963 nvidia,cf = <10>;
0964 nvidia,ci = <0>;
0965 nvidia,cg = <2>;
0966 status = "disabled";
0967 };
0968
0969 ahub@70300000 {
0970 compatible = "nvidia,tegra124-ahub";
0971 reg = <0x0 0x70300000 0x0 0x200>,
0972 <0x0 0x70300800 0x0 0x800>,
0973 <0x0 0x70300200 0x0 0x600>;
0974 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0975 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
0976 <&tegra_car TEGRA124_CLK_APBIF>;
0977 clock-names = "d_audio", "apbif";
0978 resets = <&tegra_car 106>, /* d_audio */
0979 <&tegra_car 107>, /* apbif */
0980 <&tegra_car 30>, /* i2s0 */
0981 <&tegra_car 11>, /* i2s1 */
0982 <&tegra_car 18>, /* i2s2 */
0983 <&tegra_car 101>, /* i2s3 */
0984 <&tegra_car 102>, /* i2s4 */
0985 <&tegra_car 108>, /* dam0 */
0986 <&tegra_car 109>, /* dam1 */
0987 <&tegra_car 110>, /* dam2 */
0988 <&tegra_car 10>, /* spdif */
0989 <&tegra_car 153>, /* amx */
0990 <&tegra_car 185>, /* amx1 */
0991 <&tegra_car 154>, /* adx */
0992 <&tegra_car 180>, /* adx1 */
0993 <&tegra_car 186>, /* afc0 */
0994 <&tegra_car 187>, /* afc1 */
0995 <&tegra_car 188>, /* afc2 */
0996 <&tegra_car 189>, /* afc3 */
0997 <&tegra_car 190>, /* afc4 */
0998 <&tegra_car 191>; /* afc5 */
0999 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
1000 "i2s3", "i2s4", "dam0", "dam1", "dam2",
1001 "spdif", "amx", "amx1", "adx", "adx1",
1002 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
1003 dmas = <&apbdma 1>, <&apbdma 1>,
1004 <&apbdma 2>, <&apbdma 2>,
1005 <&apbdma 3>, <&apbdma 3>,
1006 <&apbdma 4>, <&apbdma 4>,
1007 <&apbdma 6>, <&apbdma 6>,
1008 <&apbdma 7>, <&apbdma 7>,
1009 <&apbdma 12>, <&apbdma 12>,
1010 <&apbdma 13>, <&apbdma 13>,
1011 <&apbdma 14>, <&apbdma 14>,
1012 <&apbdma 29>, <&apbdma 29>;
1013 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
1014 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
1015 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
1016 "rx9", "tx9";
1017 ranges;
1018 #address-cells = <2>;
1019 #size-cells = <2>;
1020
1021 tegra_i2s0: i2s@70301000 {
1022 compatible = "nvidia,tegra124-i2s";
1023 reg = <0x0 0x70301000 0x0 0x100>;
1024 nvidia,ahub-cif-ids = <4 4>;
1025 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
1026 resets = <&tegra_car 30>;
1027 reset-names = "i2s";
1028 status = "disabled";
1029 };
1030
1031 tegra_i2s1: i2s@70301100 {
1032 compatible = "nvidia,tegra124-i2s";
1033 reg = <0x0 0x70301100 0x0 0x100>;
1034 nvidia,ahub-cif-ids = <5 5>;
1035 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
1036 resets = <&tegra_car 11>;
1037 reset-names = "i2s";
1038 status = "disabled";
1039 };
1040
1041 tegra_i2s2: i2s@70301200 {
1042 compatible = "nvidia,tegra124-i2s";
1043 reg = <0x0 0x70301200 0x0 0x100>;
1044 nvidia,ahub-cif-ids = <6 6>;
1045 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
1046 resets = <&tegra_car 18>;
1047 reset-names = "i2s";
1048 status = "disabled";
1049 };
1050
1051 tegra_i2s3: i2s@70301300 {
1052 compatible = "nvidia,tegra124-i2s";
1053 reg = <0x0 0x70301300 0x0 0x100>;
1054 nvidia,ahub-cif-ids = <7 7>;
1055 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
1056 resets = <&tegra_car 101>;
1057 reset-names = "i2s";
1058 status = "disabled";
1059 };
1060
1061 tegra_i2s4: i2s@70301400 {
1062 compatible = "nvidia,tegra124-i2s";
1063 reg = <0x0 0x70301400 0x0 0x100>;
1064 nvidia,ahub-cif-ids = <8 8>;
1065 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
1066 resets = <&tegra_car 102>;
1067 reset-names = "i2s";
1068 status = "disabled";
1069 };
1070 };
1071
1072 usb@7d000000 {
1073 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
1074 reg = <0x0 0x7d000000 0x0 0x4000>;
1075 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1076 phy_type = "utmi";
1077 clocks = <&tegra_car TEGRA124_CLK_USBD>;
1078 resets = <&tegra_car 22>;
1079 reset-names = "usb";
1080 nvidia,phy = <&phy1>;
1081 status = "disabled";
1082 };
1083
1084 phy1: usb-phy@7d000000 {
1085 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1086 reg = <0x0 0x7d000000 0x0 0x4000>,
1087 <0x0 0x7d000000 0x0 0x4000>;
1088 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1089 phy_type = "utmi";
1090 clocks = <&tegra_car TEGRA124_CLK_USBD>,
1091 <&tegra_car TEGRA124_CLK_PLL_U>,
1092 <&tegra_car TEGRA124_CLK_USBD>;
1093 clock-names = "reg", "pll_u", "utmi-pads";
1094 resets = <&tegra_car 22>, <&tegra_car 22>;
1095 reset-names = "usb", "utmi-pads";
1096 #phy-cells = <0>;
1097 nvidia,hssync-start-delay = <0>;
1098 nvidia,idle-wait-delay = <17>;
1099 nvidia,elastic-limit = <16>;
1100 nvidia,term-range-adj = <6>;
1101 nvidia,xcvr-setup = <9>;
1102 nvidia,xcvr-lsfslew = <0>;
1103 nvidia,xcvr-lsrslew = <3>;
1104 nvidia,hssquelch-level = <2>;
1105 nvidia,hsdiscon-level = <5>;
1106 nvidia,xcvr-hsslew = <12>;
1107 nvidia,has-utmi-pad-registers;
1108 nvidia,pmc = <&tegra_pmc 0>;
1109 status = "disabled";
1110 };
1111
1112 usb@7d004000 {
1113 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
1114 reg = <0x0 0x7d004000 0x0 0x4000>;
1115 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1116 phy_type = "utmi";
1117 clocks = <&tegra_car TEGRA124_CLK_USB2>;
1118 resets = <&tegra_car 58>;
1119 reset-names = "usb";
1120 nvidia,phy = <&phy2>;
1121 status = "disabled";
1122 };
1123
1124 phy2: usb-phy@7d004000 {
1125 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1126 reg = <0x0 0x7d004000 0x0 0x4000>,
1127 <0x0 0x7d000000 0x0 0x4000>;
1128 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1129 phy_type = "utmi";
1130 clocks = <&tegra_car TEGRA124_CLK_USB2>,
1131 <&tegra_car TEGRA124_CLK_PLL_U>,
1132 <&tegra_car TEGRA124_CLK_USBD>;
1133 clock-names = "reg", "pll_u", "utmi-pads";
1134 resets = <&tegra_car 58>, <&tegra_car 22>;
1135 reset-names = "usb", "utmi-pads";
1136 #phy-cells = <0>;
1137 nvidia,hssync-start-delay = <0>;
1138 nvidia,idle-wait-delay = <17>;
1139 nvidia,elastic-limit = <16>;
1140 nvidia,term-range-adj = <6>;
1141 nvidia,xcvr-setup = <9>;
1142 nvidia,xcvr-lsfslew = <0>;
1143 nvidia,xcvr-lsrslew = <3>;
1144 nvidia,hssquelch-level = <2>;
1145 nvidia,hsdiscon-level = <5>;
1146 nvidia,xcvr-hsslew = <12>;
1147 nvidia,pmc = <&tegra_pmc 1>;
1148 status = "disabled";
1149 };
1150
1151 usb@7d008000 {
1152 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
1153 reg = <0x0 0x7d008000 0x0 0x4000>;
1154 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1155 phy_type = "utmi";
1156 clocks = <&tegra_car TEGRA124_CLK_USB3>;
1157 resets = <&tegra_car 59>;
1158 reset-names = "usb";
1159 nvidia,phy = <&phy3>;
1160 status = "disabled";
1161 };
1162
1163 phy3: usb-phy@7d008000 {
1164 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1165 reg = <0x0 0x7d008000 0x0 0x4000>,
1166 <0x0 0x7d000000 0x0 0x4000>;
1167 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1168 phy_type = "utmi";
1169 clocks = <&tegra_car TEGRA124_CLK_USB3>,
1170 <&tegra_car TEGRA124_CLK_PLL_U>,
1171 <&tegra_car TEGRA124_CLK_USBD>;
1172 clock-names = "reg", "pll_u", "utmi-pads";
1173 resets = <&tegra_car 59>, <&tegra_car 22>;
1174 reset-names = "usb", "utmi-pads";
1175 #phy-cells = <0>;
1176 nvidia,hssync-start-delay = <0>;
1177 nvidia,idle-wait-delay = <17>;
1178 nvidia,elastic-limit = <16>;
1179 nvidia,term-range-adj = <6>;
1180 nvidia,xcvr-setup = <9>;
1181 nvidia,xcvr-lsfslew = <0>;
1182 nvidia,xcvr-lsrslew = <3>;
1183 nvidia,hssquelch-level = <2>;
1184 nvidia,hsdiscon-level = <5>;
1185 nvidia,xcvr-hsslew = <12>;
1186 nvidia,pmc = <&tegra_pmc 2>;
1187 status = "disabled";
1188 };
1189
1190 cpus {
1191 #address-cells = <1>;
1192 #size-cells = <0>;
1193
1194 cpu@0 {
1195 device_type = "cpu";
1196 compatible = "arm,cortex-a15";
1197 reg = <0>;
1198
1199 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
1200 <&tegra_car TEGRA124_CLK_CCLK_LP>,
1201 <&tegra_car TEGRA124_CLK_PLL_X>,
1202 <&tegra_car TEGRA124_CLK_PLL_P>,
1203 <&dfll>;
1204 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
1205 /* FIXME: what's the actual transition time? */
1206 clock-latency = <300000>;
1207 };
1208
1209 cpu@1 {
1210 device_type = "cpu";
1211 compatible = "arm,cortex-a15";
1212 reg = <1>;
1213 };
1214
1215 cpu@2 {
1216 device_type = "cpu";
1217 compatible = "arm,cortex-a15";
1218 reg = <2>;
1219 };
1220
1221 cpu@3 {
1222 device_type = "cpu";
1223 compatible = "arm,cortex-a15";
1224 reg = <3>;
1225 };
1226 };
1227
1228 pmu {
1229 compatible = "arm,cortex-a15-pmu";
1230 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1231 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1232 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1234 interrupt-affinity = <&{/cpus/cpu@0}>,
1235 <&{/cpus/cpu@1}>,
1236 <&{/cpus/cpu@2}>,
1237 <&{/cpus/cpu@3}>;
1238 };
1239
1240 thermal-zones {
1241 cpu-thermal {
1242 polling-delay-passive = <1000>;
1243 polling-delay = <1000>;
1244
1245 thermal-sensors =
1246 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1247
1248 trips {
1249 cpu-shutdown-trip {
1250 temperature = <103000>;
1251 hysteresis = <0>;
1252 type = "critical";
1253 };
1254 cpu_throttle_trip: throttle-trip {
1255 temperature = <100000>;
1256 hysteresis = <1000>;
1257 type = "hot";
1258 };
1259 };
1260
1261 cooling-maps {
1262 map0 {
1263 trip = <&cpu_throttle_trip>;
1264 cooling-device = <&throttle_heavy 1 1>;
1265 };
1266 };
1267 };
1268
1269 mem-thermal {
1270 polling-delay-passive = <1000>;
1271 polling-delay = <1000>;
1272
1273 thermal-sensors =
1274 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1275
1276 trips {
1277 mem-shutdown-trip {
1278 temperature = <103000>;
1279 hysteresis = <0>;
1280 type = "critical";
1281 };
1282 mem-throttle-trip {
1283 temperature = <99000>;
1284 hysteresis = <1000>;
1285 type = "hot";
1286 };
1287 };
1288
1289 cooling-maps {
1290 /*
1291 * There are currently no cooling maps,
1292 * because there are no cooling devices.
1293 */
1294 };
1295 };
1296
1297 gpu-thermal {
1298 polling-delay-passive = <1000>;
1299 polling-delay = <1000>;
1300
1301 thermal-sensors =
1302 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1303
1304 trips {
1305 gpu-shutdown-trip {
1306 temperature = <101000>;
1307 hysteresis = <0>;
1308 type = "critical";
1309 };
1310 gpu_throttle_trip: throttle-trip {
1311 temperature = <99000>;
1312 hysteresis = <1000>;
1313 type = "hot";
1314 };
1315 };
1316
1317 cooling-maps {
1318 map0 {
1319 trip = <&gpu_throttle_trip>;
1320 cooling-device = <&throttle_heavy 1 1>;
1321 };
1322 };
1323 };
1324
1325 pllx-thermal {
1326 polling-delay-passive = <1000>;
1327 polling-delay = <1000>;
1328
1329 thermal-sensors =
1330 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1331
1332 trips {
1333 pllx-shutdown-trip {
1334 temperature = <103000>;
1335 hysteresis = <0>;
1336 type = "critical";
1337 };
1338 pllx-throttle-trip {
1339 temperature = <99000>;
1340 hysteresis = <1000>;
1341 type = "hot";
1342 };
1343 };
1344
1345 cooling-maps {
1346 /*
1347 * There are currently no cooling maps,
1348 * because there are no cooling devices.
1349 */
1350 };
1351 };
1352 };
1353
1354 timer {
1355 compatible = "arm,armv7-timer";
1356 interrupts = <GIC_PPI 13
1357 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1358 <GIC_PPI 14
1359 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1360 <GIC_PPI 11
1361 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1362 <GIC_PPI 10
1363 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1364 interrupt-parent = <&gic>;
1365 };
1366 };
