0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <dt-bindings/clock/tegra114-car.h>
0003 #include <dt-bindings/gpio/tegra-gpio.h>
0004 #include <dt-bindings/memory/tegra114-mc.h>
0005 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
0006 #include <dt-bindings/interrupt-controller/arm-gic.h>
0007 #include <dt-bindings/soc/tegra-pmc.h>
0008
0009 / {
0010 compatible = "nvidia,tegra114";
0011 interrupt-parent = <&lic>;
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014
0015 memory@80000000 {
0016 device_type = "memory";
0017 reg = <0x80000000 0x0>;
0018 };
0019
0020 sram@40000000 {
0021 compatible = "mmio-sram";
0022 reg = <0x40000000 0x40000>;
0023 #address-cells = <1>;
0024 #size-cells = <1>;
0025 ranges = <0 0x40000000 0x40000>;
0026
0027 vde_pool: sram@400 {
0028 reg = <0x400 0x3fc00>;
0029 pool;
0030 };
0031 };
0032
0033 host1x@50000000 {
0034 compatible = "nvidia,tegra114-host1x";
0035 reg = <0x50000000 0x00028000>;
0036 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
0037 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
0038 interrupt-names = "syncpt", "host1x";
0039 clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
0040 clock-names = "host1x";
0041 resets = <&tegra_car 28>, <&mc TEGRA114_MC_RESET_HC>;
0042 reset-names = "host1x", "mc";
0043 iommus = <&mc TEGRA_SWGROUP_HC>;
0044
0045 #address-cells = <1>;
0046 #size-cells = <1>;
0047
0048 ranges = <0x54000000 0x54000000 0x01000000>;
0049
0050 gr2d@54140000 {
0051 compatible = "nvidia,tegra114-gr2d";
0052 reg = <0x54140000 0x00040000>;
0053 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0054 clocks = <&tegra_car TEGRA114_CLK_GR2D>;
0055 resets = <&tegra_car 21>, <&mc TEGRA114_MC_RESET_2D>;
0056 reset-names = "2d", "mc";
0057
0058 iommus = <&mc TEGRA_SWGROUP_G2>;
0059 };
0060
0061 gr3d@54180000 {
0062 compatible = "nvidia,tegra114-gr3d";
0063 reg = <0x54180000 0x00040000>;
0064 clocks = <&tegra_car TEGRA114_CLK_GR3D>;
0065 resets = <&tegra_car 24>, <&mc TEGRA114_MC_RESET_3D>;
0066 reset-names = "3d", "mc";
0067
0068 iommus = <&mc TEGRA_SWGROUP_NV>;
0069 };
0070
0071 dc@54200000 {
0072 compatible = "nvidia,tegra114-dc";
0073 reg = <0x54200000 0x00040000>;
0074 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0075 clocks = <&tegra_car TEGRA114_CLK_DISP1>,
0076 <&tegra_car TEGRA114_CLK_PLL_P>;
0077 clock-names = "dc", "parent";
0078 resets = <&tegra_car 27>;
0079 reset-names = "dc";
0080
0081 iommus = <&mc TEGRA_SWGROUP_DC>;
0082
0083 nvidia,head = <0>;
0084
0085 rgb {
0086 status = "disabled";
0087 };
0088 };
0089
0090 dc@54240000 {
0091 compatible = "nvidia,tegra114-dc";
0092 reg = <0x54240000 0x00040000>;
0093 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0094 clocks = <&tegra_car TEGRA114_CLK_DISP2>,
0095 <&tegra_car TEGRA114_CLK_PLL_P>;
0096 clock-names = "dc", "parent";
0097 resets = <&tegra_car 26>;
0098 reset-names = "dc";
0099
0100 iommus = <&mc TEGRA_SWGROUP_DCB>;
0101
0102 nvidia,head = <1>;
0103
0104 rgb {
0105 status = "disabled";
0106 };
0107 };
0108
0109 hdmi@54280000 {
0110 compatible = "nvidia,tegra114-hdmi";
0111 reg = <0x54280000 0x00040000>;
0112 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0113 clocks = <&tegra_car TEGRA114_CLK_HDMI>,
0114 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
0115 clock-names = "hdmi", "parent";
0116 resets = <&tegra_car 51>;
0117 reset-names = "hdmi";
0118 status = "disabled";
0119 };
0120
0121 dsia: dsi@54300000 {
0122 compatible = "nvidia,tegra114-dsi";
0123 reg = <0x54300000 0x00040000>;
0124 clocks = <&tegra_car TEGRA114_CLK_DSIA>,
0125 <&tegra_car TEGRA114_CLK_DSIALP>,
0126 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
0127 clock-names = "dsi", "lp", "parent";
0128 resets = <&tegra_car 48>;
0129 reset-names = "dsi";
0130 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
0131 status = "disabled";
0132
0133 #address-cells = <1>;
0134 #size-cells = <0>;
0135 };
0136
0137 dsib: dsi@54400000 {
0138 compatible = "nvidia,tegra114-dsi";
0139 reg = <0x54400000 0x00040000>;
0140 clocks = <&tegra_car TEGRA114_CLK_DSIB>,
0141 <&tegra_car TEGRA114_CLK_DSIBLP>,
0142 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
0143 clock-names = "dsi", "lp", "parent";
0144 resets = <&tegra_car 82>;
0145 reset-names = "dsi";
0146 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
0147 status = "disabled";
0148
0149 #address-cells = <1>;
0150 #size-cells = <0>;
0151 };
0152 };
0153
0154 gic: interrupt-controller@50041000 {
0155 compatible = "arm,cortex-a15-gic";
0156 #interrupt-cells = <3>;
0157 interrupt-controller;
0158 reg = <0x50041000 0x1000>,
0159 <0x50042000 0x1000>,
0160 <0x50044000 0x2000>,
0161 <0x50046000 0x2000>;
0162 interrupts = <GIC_PPI 9
0163 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0164 interrupt-parent = <&gic>;
0165 };
0166
0167 lic: interrupt-controller@60004000 {
0168 compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
0169 reg = <0x60004000 0x100>,
0170 <0x60004100 0x50>,
0171 <0x60004200 0x50>,
0172 <0x60004300 0x50>,
0173 <0x60004400 0x50>;
0174 interrupt-controller;
0175 #interrupt-cells = <3>;
0176 interrupt-parent = <&gic>;
0177 };
0178
0179 timer@60005000 {
0180 compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer";
0181 reg = <0x60005000 0x400>;
0182 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
0183 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0184 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
0185 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
0186 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
0187 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
0188 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
0189 };
0190
0191 tegra_car: clock@60006000 {
0192 compatible = "nvidia,tegra114-car";
0193 reg = <0x60006000 0x1000>;
0194 #clock-cells = <1>;
0195 #reset-cells = <1>;
0196 };
0197
0198 flow-controller@60007000 {
0199 compatible = "nvidia,tegra114-flowctrl";
0200 reg = <0x60007000 0x1000>;
0201 };
0202
0203 apbdma: dma@6000a000 {
0204 compatible = "nvidia,tegra114-apbdma";
0205 reg = <0x6000a000 0x1400>;
0206 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0207 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
0208 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
0209 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
0210 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
0211 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
0212 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
0213 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
0214 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
0215 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
0216 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
0217 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
0218 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
0219 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
0220 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
0221 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
0222 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
0223 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
0224 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
0225 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
0226 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
0227 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
0228 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
0229 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
0230 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
0231 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
0232 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
0233 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
0234 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
0235 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
0236 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
0237 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0238 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
0239 resets = <&tegra_car 34>;
0240 reset-names = "dma";
0241 #dma-cells = <1>;
0242 };
0243
0244 ahb: ahb@6000c000 {
0245 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
0246 reg = <0x6000c000 0x150>;
0247 };
0248
0249 gpio: gpio@6000d000 {
0250 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
0251 reg = <0x6000d000 0x1000>;
0252 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
0253 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
0254 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
0255 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
0256 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
0257 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
0258 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
0259 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
0260 #gpio-cells = <2>;
0261 gpio-controller;
0262 #interrupt-cells = <2>;
0263 interrupt-controller;
0264 gpio-ranges = <&pinmux 0 0 246>;
0265 };
0266
0267 vde@6001a000 {
0268 compatible = "nvidia,tegra114-vde";
0269 reg = <0x6001a000 0x1000>, /* Syntax Engine */
0270 <0x6001b000 0x1000>, /* Video Bitstream Engine */
0271 <0x6001c000 0x100>, /* Macroblock Engine */
0272 <0x6001c200 0x100>, /* Post-processing Engine */
0273 <0x6001c400 0x100>, /* Motion Compensation Engine */
0274 <0x6001c600 0x100>, /* Transform Engine */
0275 <0x6001c800 0x100>, /* Pixel prediction block */
0276 <0x6001ca00 0x100>, /* Video DMA */
0277 <0x6001d800 0x400>; /* Video frame controls */
0278 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
0279 "tfe", "ppb", "vdma", "frameid";
0280 iram = <&vde_pool>; /* IRAM region */
0281 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
0282 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
0283 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
0284 interrupt-names = "sync-token", "bsev", "sxe";
0285 clocks = <&tegra_car TEGRA114_CLK_VDE>;
0286 reset-names = "vde", "mc";
0287 resets = <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>;
0288 iommus = <&mc TEGRA_SWGROUP_VDE>;
0289 };
0290
0291 apbmisc@70000800 {
0292 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
0293 reg = <0x70000800 0x64>, /* Chip revision */
0294 <0x70000008 0x04>; /* Strapping options */
0295 };
0296
0297 pinmux: pinmux@70000868 {
0298 compatible = "nvidia,tegra114-pinmux";
0299 reg = <0x70000868 0x148>, /* Pad control registers */
0300 <0x70003000 0x40c>; /* Mux registers */
0301 };
0302
0303 /*
0304 * There are two serial driver i.e. 8250 based simple serial
0305 * driver and APB DMA based serial driver for higher baudrate
0306 * and performace. To enable the 8250 based driver, the compatible
0307 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
0308 * the APB DMA based serial driver, the compatible is
0309 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
0310 */
0311 uarta: serial@70006000 {
0312 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
0313 reg = <0x70006000 0x40>;
0314 reg-shift = <2>;
0315 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0316 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
0317 resets = <&tegra_car 6>;
0318 reset-names = "serial";
0319 dmas = <&apbdma 8>, <&apbdma 8>;
0320 dma-names = "rx", "tx";
0321 status = "disabled";
0322 };
0323
0324 uartb: serial@70006040 {
0325 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
0326 reg = <0x70006040 0x40>;
0327 reg-shift = <2>;
0328 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0329 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
0330 resets = <&tegra_car 7>;
0331 reset-names = "serial";
0332 dmas = <&apbdma 9>, <&apbdma 9>;
0333 dma-names = "rx", "tx";
0334 status = "disabled";
0335 };
0336
0337 uartc: serial@70006200 {
0338 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
0339 reg = <0x70006200 0x100>;
0340 reg-shift = <2>;
0341 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0342 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
0343 resets = <&tegra_car 55>;
0344 reset-names = "serial";
0345 dmas = <&apbdma 10>, <&apbdma 10>;
0346 dma-names = "rx", "tx";
0347 status = "disabled";
0348 };
0349
0350 uartd: serial@70006300 {
0351 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
0352 reg = <0x70006300 0x100>;
0353 reg-shift = <2>;
0354 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0355 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
0356 resets = <&tegra_car 65>;
0357 reset-names = "serial";
0358 dmas = <&apbdma 19>, <&apbdma 19>;
0359 dma-names = "rx", "tx";
0360 status = "disabled";
0361 };
0362
0363 pwm: pwm@7000a000 {
0364 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
0365 reg = <0x7000a000 0x100>;
0366 #pwm-cells = <2>;
0367 clocks = <&tegra_car TEGRA114_CLK_PWM>;
0368 resets = <&tegra_car 17>;
0369 reset-names = "pwm";
0370 status = "disabled";
0371 };
0372
0373 i2c@7000c000 {
0374 compatible = "nvidia,tegra114-i2c";
0375 reg = <0x7000c000 0x100>;
0376 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0377 #address-cells = <1>;
0378 #size-cells = <0>;
0379 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
0380 clock-names = "div-clk";
0381 resets = <&tegra_car 12>;
0382 reset-names = "i2c";
0383 dmas = <&apbdma 21>, <&apbdma 21>;
0384 dma-names = "rx", "tx";
0385 status = "disabled";
0386 };
0387
0388 i2c@7000c400 {
0389 compatible = "nvidia,tegra114-i2c";
0390 reg = <0x7000c400 0x100>;
0391 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0392 #address-cells = <1>;
0393 #size-cells = <0>;
0394 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
0395 clock-names = "div-clk";
0396 resets = <&tegra_car 54>;
0397 reset-names = "i2c";
0398 dmas = <&apbdma 22>, <&apbdma 22>;
0399 dma-names = "rx", "tx";
0400 status = "disabled";
0401 };
0402
0403 i2c@7000c500 {
0404 compatible = "nvidia,tegra114-i2c";
0405 reg = <0x7000c500 0x100>;
0406 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0407 #address-cells = <1>;
0408 #size-cells = <0>;
0409 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
0410 clock-names = "div-clk";
0411 resets = <&tegra_car 67>;
0412 reset-names = "i2c";
0413 dmas = <&apbdma 23>, <&apbdma 23>;
0414 dma-names = "rx", "tx";
0415 status = "disabled";
0416 };
0417
0418 i2c@7000c700 {
0419 compatible = "nvidia,tegra114-i2c";
0420 reg = <0x7000c700 0x100>;
0421 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
0422 #address-cells = <1>;
0423 #size-cells = <0>;
0424 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
0425 clock-names = "div-clk";
0426 resets = <&tegra_car 103>;
0427 reset-names = "i2c";
0428 dmas = <&apbdma 26>, <&apbdma 26>;
0429 dma-names = "rx", "tx";
0430 status = "disabled";
0431 };
0432
0433 i2c@7000d000 {
0434 compatible = "nvidia,tegra114-i2c";
0435 reg = <0x7000d000 0x100>;
0436 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
0437 #address-cells = <1>;
0438 #size-cells = <0>;
0439 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
0440 clock-names = "div-clk";
0441 resets = <&tegra_car 47>;
0442 reset-names = "i2c";
0443 dmas = <&apbdma 24>, <&apbdma 24>;
0444 dma-names = "rx", "tx";
0445 status = "disabled";
0446 };
0447
0448 spi@7000d400 {
0449 compatible = "nvidia,tegra114-spi";
0450 reg = <0x7000d400 0x200>;
0451 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
0452 #address-cells = <1>;
0453 #size-cells = <0>;
0454 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
0455 clock-names = "spi";
0456 resets = <&tegra_car 41>;
0457 reset-names = "spi";
0458 dmas = <&apbdma 15>, <&apbdma 15>;
0459 dma-names = "rx", "tx";
0460 status = "disabled";
0461 };
0462
0463 spi@7000d600 {
0464 compatible = "nvidia,tegra114-spi";
0465 reg = <0x7000d600 0x200>;
0466 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0467 #address-cells = <1>;
0468 #size-cells = <0>;
0469 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
0470 clock-names = "spi";
0471 resets = <&tegra_car 44>;
0472 reset-names = "spi";
0473 dmas = <&apbdma 16>, <&apbdma 16>;
0474 dma-names = "rx", "tx";
0475 status = "disabled";
0476 };
0477
0478 spi@7000d800 {
0479 compatible = "nvidia,tegra114-spi";
0480 reg = <0x7000d800 0x200>;
0481 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0482 #address-cells = <1>;
0483 #size-cells = <0>;
0484 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
0485 clock-names = "spi";
0486 resets = <&tegra_car 46>;
0487 reset-names = "spi";
0488 dmas = <&apbdma 17>, <&apbdma 17>;
0489 dma-names = "rx", "tx";
0490 status = "disabled";
0491 };
0492
0493 spi@7000da00 {
0494 compatible = "nvidia,tegra114-spi";
0495 reg = <0x7000da00 0x200>;
0496 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
0497 #address-cells = <1>;
0498 #size-cells = <0>;
0499 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
0500 clock-names = "spi";
0501 resets = <&tegra_car 68>;
0502 reset-names = "spi";
0503 dmas = <&apbdma 18>, <&apbdma 18>;
0504 dma-names = "rx", "tx";
0505 status = "disabled";
0506 };
0507
0508 spi@7000dc00 {
0509 compatible = "nvidia,tegra114-spi";
0510 reg = <0x7000dc00 0x200>;
0511 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0512 #address-cells = <1>;
0513 #size-cells = <0>;
0514 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
0515 clock-names = "spi";
0516 resets = <&tegra_car 104>;
0517 reset-names = "spi";
0518 dmas = <&apbdma 27>, <&apbdma 27>;
0519 dma-names = "rx", "tx";
0520 status = "disabled";
0521 };
0522
0523 spi@7000de00 {
0524 compatible = "nvidia,tegra114-spi";
0525 reg = <0x7000de00 0x200>;
0526 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0527 #address-cells = <1>;
0528 #size-cells = <0>;
0529 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
0530 clock-names = "spi";
0531 resets = <&tegra_car 105>;
0532 reset-names = "spi";
0533 dmas = <&apbdma 28>, <&apbdma 28>;
0534 dma-names = "rx", "tx";
0535 status = "disabled";
0536 };
0537
0538 rtc@7000e000 {
0539 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
0540 reg = <0x7000e000 0x100>;
0541 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0542 clocks = <&tegra_car TEGRA114_CLK_RTC>;
0543 };
0544
0545 kbc@7000e200 {
0546 compatible = "nvidia,tegra114-kbc";
0547 reg = <0x7000e200 0x100>;
0548 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
0549 clocks = <&tegra_car TEGRA114_CLK_KBC>;
0550 resets = <&tegra_car 36>;
0551 reset-names = "kbc";
0552 status = "disabled";
0553 };
0554
0555 tegra_pmc: pmc@7000e400 {
0556 compatible = "nvidia,tegra114-pmc";
0557 reg = <0x7000e400 0x400>;
0558 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
0559 clock-names = "pclk", "clk32k_in";
0560 #clock-cells = <1>;
0561 };
0562
0563 fuse@7000f800 {
0564 compatible = "nvidia,tegra114-efuse";
0565 reg = <0x7000f800 0x400>;
0566 clocks = <&tegra_car TEGRA114_CLK_FUSE>;
0567 clock-names = "fuse";
0568 resets = <&tegra_car 39>;
0569 reset-names = "fuse";
0570 };
0571
0572 mc: memory-controller@70019000 {
0573 compatible = "nvidia,tegra114-mc";
0574 reg = <0x70019000 0x1000>;
0575 clocks = <&tegra_car TEGRA114_CLK_MC>;
0576 clock-names = "mc";
0577
0578 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0579
0580 #reset-cells = <1>;
0581 #iommu-cells = <1>;
0582 };
0583
0584 ahub@70080000 {
0585 compatible = "nvidia,tegra114-ahub";
0586 reg = <0x70080000 0x200>,
0587 <0x70080200 0x100>,
0588 <0x70081000 0x200>;
0589 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
0590 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
0591 <&tegra_car TEGRA114_CLK_APBIF>;
0592 clock-names = "d_audio", "apbif";
0593 resets = <&tegra_car 106>, /* d_audio */
0594 <&tegra_car 107>, /* apbif */
0595 <&tegra_car 30>, /* i2s0 */
0596 <&tegra_car 11>, /* i2s1 */
0597 <&tegra_car 18>, /* i2s2 */
0598 <&tegra_car 101>, /* i2s3 */
0599 <&tegra_car 102>, /* i2s4 */
0600 <&tegra_car 108>, /* dam0 */
0601 <&tegra_car 109>, /* dam1 */
0602 <&tegra_car 110>, /* dam2 */
0603 <&tegra_car 10>, /* spdif */
0604 <&tegra_car 153>, /* amx */
0605 <&tegra_car 154>; /* adx */
0606 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
0607 "i2s3", "i2s4", "dam0", "dam1", "dam2",
0608 "spdif", "amx", "adx";
0609 dmas = <&apbdma 1>, <&apbdma 1>,
0610 <&apbdma 2>, <&apbdma 2>,
0611 <&apbdma 3>, <&apbdma 3>,
0612 <&apbdma 4>, <&apbdma 4>,
0613 <&apbdma 6>, <&apbdma 6>,
0614 <&apbdma 7>, <&apbdma 7>,
0615 <&apbdma 12>, <&apbdma 12>,
0616 <&apbdma 13>, <&apbdma 13>,
0617 <&apbdma 14>, <&apbdma 14>,
0618 <&apbdma 29>, <&apbdma 29>;
0619 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
0620 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
0621 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
0622 "rx9", "tx9";
0623 ranges;
0624 #address-cells = <1>;
0625 #size-cells = <1>;
0626
0627 tegra_i2s0: i2s@70080300 {
0628 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
0629 reg = <0x70080300 0x100>;
0630 nvidia,ahub-cif-ids = <4 4>;
0631 clocks = <&tegra_car TEGRA114_CLK_I2S0>;
0632 resets = <&tegra_car 30>;
0633 reset-names = "i2s";
0634 status = "disabled";
0635 };
0636
0637 tegra_i2s1: i2s@70080400 {
0638 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
0639 reg = <0x70080400 0x100>;
0640 nvidia,ahub-cif-ids = <5 5>;
0641 clocks = <&tegra_car TEGRA114_CLK_I2S1>;
0642 resets = <&tegra_car 11>;
0643 reset-names = "i2s";
0644 status = "disabled";
0645 };
0646
0647 tegra_i2s2: i2s@70080500 {
0648 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
0649 reg = <0x70080500 0x100>;
0650 nvidia,ahub-cif-ids = <6 6>;
0651 clocks = <&tegra_car TEGRA114_CLK_I2S2>;
0652 resets = <&tegra_car 18>;
0653 reset-names = "i2s";
0654 status = "disabled";
0655 };
0656
0657 tegra_i2s3: i2s@70080600 {
0658 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
0659 reg = <0x70080600 0x100>;
0660 nvidia,ahub-cif-ids = <7 7>;
0661 clocks = <&tegra_car TEGRA114_CLK_I2S3>;
0662 resets = <&tegra_car 101>;
0663 reset-names = "i2s";
0664 status = "disabled";
0665 };
0666
0667 tegra_i2s4: i2s@70080700 {
0668 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
0669 reg = <0x70080700 0x100>;
0670 nvidia,ahub-cif-ids = <8 8>;
0671 clocks = <&tegra_car TEGRA114_CLK_I2S4>;
0672 resets = <&tegra_car 102>;
0673 reset-names = "i2s";
0674 status = "disabled";
0675 };
0676 };
0677
0678 mipi: mipi@700e3000 {
0679 compatible = "nvidia,tegra114-mipi";
0680 reg = <0x700e3000 0x100>;
0681 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
0682 #nvidia,mipi-calibrate-cells = <1>;
0683 };
0684
0685 mmc@78000000 {
0686 compatible = "nvidia,tegra114-sdhci";
0687 reg = <0x78000000 0x200>;
0688 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0689 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
0690 clock-names = "sdhci";
0691 resets = <&tegra_car 14>;
0692 reset-names = "sdhci";
0693 status = "disabled";
0694 };
0695
0696 mmc@78000200 {
0697 compatible = "nvidia,tegra114-sdhci";
0698 reg = <0x78000200 0x200>;
0699 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0700 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
0701 clock-names = "sdhci";
0702 resets = <&tegra_car 9>;
0703 reset-names = "sdhci";
0704 status = "disabled";
0705 };
0706
0707 mmc@78000400 {
0708 compatible = "nvidia,tegra114-sdhci";
0709 reg = <0x78000400 0x200>;
0710 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0711 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
0712 clock-names = "sdhci";
0713 resets = <&tegra_car 69>;
0714 reset-names = "sdhci";
0715 status = "disabled";
0716 };
0717
0718 mmc@78000600 {
0719 compatible = "nvidia,tegra114-sdhci";
0720 reg = <0x78000600 0x200>;
0721 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0722 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
0723 clock-names = "sdhci";
0724 resets = <&tegra_car 15>;
0725 reset-names = "sdhci";
0726 status = "disabled";
0727 };
0728
0729 usb@7d000000 {
0730 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci";
0731 reg = <0x7d000000 0x4000>;
0732 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0733 phy_type = "utmi";
0734 clocks = <&tegra_car TEGRA114_CLK_USBD>;
0735 resets = <&tegra_car 22>;
0736 reset-names = "usb";
0737 nvidia,phy = <&phy1>;
0738 status = "disabled";
0739 };
0740
0741 phy1: usb-phy@7d000000 {
0742 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
0743 reg = <0x7d000000 0x4000>,
0744 <0x7d000000 0x4000>;
0745 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0746 phy_type = "utmi";
0747 clocks = <&tegra_car TEGRA114_CLK_USBD>,
0748 <&tegra_car TEGRA114_CLK_PLL_U>,
0749 <&tegra_car TEGRA114_CLK_USBD>;
0750 clock-names = "reg", "pll_u", "utmi-pads";
0751 resets = <&tegra_car 22>, <&tegra_car 22>;
0752 reset-names = "usb", "utmi-pads";
0753 #phy-cells = <0>;
0754 nvidia,hssync-start-delay = <0>;
0755 nvidia,idle-wait-delay = <17>;
0756 nvidia,elastic-limit = <16>;
0757 nvidia,term-range-adj = <6>;
0758 nvidia,xcvr-setup = <9>;
0759 nvidia,xcvr-lsfslew = <0>;
0760 nvidia,xcvr-lsrslew = <3>;
0761 nvidia,hssquelch-level = <2>;
0762 nvidia,hsdiscon-level = <5>;
0763 nvidia,xcvr-hsslew = <12>;
0764 nvidia,has-utmi-pad-registers;
0765 nvidia,pmc = <&tegra_pmc 0>;
0766 status = "disabled";
0767 };
0768
0769 usb@7d008000 {
0770 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci";
0771 reg = <0x7d008000 0x4000>;
0772 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0773 phy_type = "utmi";
0774 clocks = <&tegra_car TEGRA114_CLK_USB3>;
0775 resets = <&tegra_car 59>;
0776 reset-names = "usb";
0777 nvidia,phy = <&phy3>;
0778 status = "disabled";
0779 };
0780
0781 phy3: usb-phy@7d008000 {
0782 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
0783 reg = <0x7d008000 0x4000>,
0784 <0x7d000000 0x4000>;
0785 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0786 phy_type = "utmi";
0787 clocks = <&tegra_car TEGRA114_CLK_USB3>,
0788 <&tegra_car TEGRA114_CLK_PLL_U>,
0789 <&tegra_car TEGRA114_CLK_USBD>;
0790 clock-names = "reg", "pll_u", "utmi-pads";
0791 resets = <&tegra_car 59>, <&tegra_car 22>;
0792 reset-names = "usb", "utmi-pads";
0793 #phy-cells = <0>;
0794 nvidia,hssync-start-delay = <0>;
0795 nvidia,idle-wait-delay = <17>;
0796 nvidia,elastic-limit = <16>;
0797 nvidia,term-range-adj = <6>;
0798 nvidia,xcvr-setup = <9>;
0799 nvidia,xcvr-lsfslew = <0>;
0800 nvidia,xcvr-lsrslew = <3>;
0801 nvidia,hssquelch-level = <2>;
0802 nvidia,hsdiscon-level = <5>;
0803 nvidia,xcvr-hsslew = <12>;
0804 nvidia,pmc = <&tegra_pmc 2>;
0805 status = "disabled";
0806 };
0807
0808 cpus {
0809 #address-cells = <1>;
0810 #size-cells = <0>;
0811
0812 cpu@0 {
0813 device_type = "cpu";
0814 compatible = "arm,cortex-a15";
0815 reg = <0>;
0816 };
0817
0818 cpu@1 {
0819 device_type = "cpu";
0820 compatible = "arm,cortex-a15";
0821 reg = <1>;
0822 };
0823
0824 cpu@2 {
0825 device_type = "cpu";
0826 compatible = "arm,cortex-a15";
0827 reg = <2>;
0828 };
0829
0830 cpu@3 {
0831 device_type = "cpu";
0832 compatible = "arm,cortex-a15";
0833 reg = <3>;
0834 };
0835 };
0836
0837 timer {
0838 compatible = "arm,armv7-timer";
0839 interrupts =
0840 <GIC_PPI 13
0841 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0842 <GIC_PPI 14
0843 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0844 <GIC_PPI 11
0845 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0846 <GIC_PPI 10
0847 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0848 interrupt-parent = <&gic>;
0849 };
0850 };
