0001 /*
0002 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
0003 *
0004 * This file is dual-licensed: you can use it either under the terms
0005 * of the GPL or the X11 license, at your option. Note that this dual
0006 * licensing only applies to this file, and not this project as a
0007 * whole.
0008 *
0009 * a) This file is free software; you can redistribute it and/or
0010 * modify it under the terms of the GNU General Public License as
0011 * published by the Free Software Foundation; either version 2 of the
0012 * License, or (at your option) any later version.
0013 *
0014 * This file is distributed in the hope that it will be useful,
0015 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0017 * GNU General Public License for more details.
0018 *
0019 * Or, alternatively,
0020 *
0021 * b) Permission is hereby granted, free of charge, to any person
0022 * obtaining a copy of this software and associated documentation
0023 * files (the "Software"), to deal in the Software without
0024 * restriction, including without limitation the rights to use,
0025 * copy, modify, merge, publish, distribute, sublicense, and/or
0026 * sell copies of the Software, and to permit persons to whom the
0027 * Software is furnished to do so, subject to the following
0028 * conditions:
0029 *
0030 * The above copyright notice and this permission notice shall be
0031 * included in all copies or substantial portions of the Software.
0032 *
0033 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0034 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0035 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0036 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0037 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0038 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0039 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0040 * OTHER DEALINGS IN THE SOFTWARE.
0041 */
0042
0043 #include <dt-bindings/clock/sun6i-rtc.h>
0044 #include <dt-bindings/clock/sun8i-de2.h>
0045 #include <dt-bindings/clock/sun8i-h3-ccu.h>
0046 #include <dt-bindings/clock/sun8i-r-ccu.h>
0047 #include <dt-bindings/interrupt-controller/arm-gic.h>
0048 #include <dt-bindings/reset/sun8i-de2.h>
0049 #include <dt-bindings/reset/sun8i-h3-ccu.h>
0050 #include <dt-bindings/reset/sun8i-r-ccu.h>
0051
0052 / {
0053 interrupt-parent = <&gic>;
0054 #address-cells = <1>;
0055 #size-cells = <1>;
0056
0057 chosen {
0058 #address-cells = <1>;
0059 #size-cells = <1>;
0060 ranges;
0061
0062 framebuffer-hdmi {
0063 compatible = "allwinner,simple-framebuffer",
0064 "simple-framebuffer";
0065 allwinner,pipeline = "mixer0-lcd0-hdmi";
0066 clocks = <&display_clocks CLK_MIXER0>,
0067 <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
0068 status = "disabled";
0069 };
0070
0071 framebuffer-tve {
0072 compatible = "allwinner,simple-framebuffer",
0073 "simple-framebuffer";
0074 allwinner,pipeline = "mixer1-lcd1-tve";
0075 clocks = <&display_clocks CLK_MIXER1>,
0076 <&ccu CLK_TVE>;
0077 status = "disabled";
0078 };
0079 };
0080
0081 clocks {
0082 #address-cells = <1>;
0083 #size-cells = <1>;
0084 ranges;
0085
0086 osc24M: osc24M_clk {
0087 #clock-cells = <0>;
0088 compatible = "fixed-clock";
0089 clock-frequency = <24000000>;
0090 clock-accuracy = <50000>;
0091 clock-output-names = "osc24M";
0092 };
0093
0094 osc32k: osc32k_clk {
0095 #clock-cells = <0>;
0096 compatible = "fixed-clock";
0097 clock-frequency = <32768>;
0098 clock-accuracy = <50000>;
0099 clock-output-names = "ext_osc32k";
0100 };
0101 };
0102
0103 de: display-engine {
0104 compatible = "allwinner,sun8i-h3-display-engine";
0105 allwinner,pipelines = <&mixer0>;
0106 status = "disabled";
0107 };
0108
0109 soc {
0110 compatible = "simple-bus";
0111 #address-cells = <1>;
0112 #size-cells = <1>;
0113 dma-ranges;
0114 ranges;
0115
0116 display_clocks: clock@1000000 {
0117 /* compatible is in per SoC .dtsi file */
0118 reg = <0x01000000 0x10000>;
0119 clocks = <&ccu CLK_BUS_DE>,
0120 <&ccu CLK_DE>;
0121 clock-names = "bus",
0122 "mod";
0123 resets = <&ccu RST_BUS_DE>;
0124 #clock-cells = <1>;
0125 #reset-cells = <1>;
0126 };
0127
0128 mixer0: mixer@1100000 {
0129 compatible = "allwinner,sun8i-h3-de2-mixer-0";
0130 reg = <0x01100000 0x100000>;
0131 clocks = <&display_clocks CLK_BUS_MIXER0>,
0132 <&display_clocks CLK_MIXER0>;
0133 clock-names = "bus",
0134 "mod";
0135 resets = <&display_clocks RST_MIXER0>;
0136
0137 ports {
0138 #address-cells = <1>;
0139 #size-cells = <0>;
0140
0141 mixer0_out: port@1 {
0142 reg = <1>;
0143
0144 mixer0_out_tcon0: endpoint {
0145 remote-endpoint = <&tcon0_in_mixer0>;
0146 };
0147 };
0148 };
0149 };
0150
0151 dma: dma-controller@1c02000 {
0152 compatible = "allwinner,sun8i-h3-dma";
0153 reg = <0x01c02000 0x1000>;
0154 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0155 clocks = <&ccu CLK_BUS_DMA>;
0156 resets = <&ccu RST_BUS_DMA>;
0157 #dma-cells = <1>;
0158 };
0159
0160 tcon0: lcd-controller@1c0c000 {
0161 compatible = "allwinner,sun8i-h3-tcon-tv",
0162 "allwinner,sun8i-a83t-tcon-tv";
0163 reg = <0x01c0c000 0x1000>;
0164 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0165 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
0166 clock-names = "ahb", "tcon-ch1";
0167 resets = <&ccu RST_BUS_TCON0>;
0168 reset-names = "lcd";
0169
0170 ports {
0171 #address-cells = <1>;
0172 #size-cells = <0>;
0173
0174 tcon0_in: port@0 {
0175 reg = <0>;
0176
0177 tcon0_in_mixer0: endpoint {
0178 remote-endpoint = <&mixer0_out_tcon0>;
0179 };
0180 };
0181
0182 tcon0_out: port@1 {
0183 #address-cells = <1>;
0184 #size-cells = <0>;
0185 reg = <1>;
0186
0187 tcon0_out_hdmi: endpoint@1 {
0188 reg = <1>;
0189 remote-endpoint = <&hdmi_in_tcon0>;
0190 };
0191 };
0192 };
0193 };
0194
0195 mmc0: mmc@1c0f000 {
0196 /* compatible and clocks are in per SoC .dtsi file */
0197 reg = <0x01c0f000 0x1000>;
0198 pinctrl-names = "default";
0199 pinctrl-0 = <&mmc0_pins>;
0200 resets = <&ccu RST_BUS_MMC0>;
0201 reset-names = "ahb";
0202 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0203 status = "disabled";
0204 #address-cells = <1>;
0205 #size-cells = <0>;
0206 };
0207
0208 mmc1: mmc@1c10000 {
0209 /* compatible and clocks are in per SoC .dtsi file */
0210 reg = <0x01c10000 0x1000>;
0211 pinctrl-names = "default";
0212 pinctrl-0 = <&mmc1_pins>;
0213 resets = <&ccu RST_BUS_MMC1>;
0214 reset-names = "ahb";
0215 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0216 status = "disabled";
0217 #address-cells = <1>;
0218 #size-cells = <0>;
0219 };
0220
0221 mmc2: mmc@1c11000 {
0222 /* compatible and clocks are in per SoC .dtsi file */
0223 reg = <0x01c11000 0x1000>;
0224 resets = <&ccu RST_BUS_MMC2>;
0225 reset-names = "ahb";
0226 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0227 status = "disabled";
0228 #address-cells = <1>;
0229 #size-cells = <0>;
0230 };
0231
0232 sid: eeprom@1c14000 {
0233 /* compatible is in per SoC .dtsi file */
0234 reg = <0x1c14000 0x400>;
0235 #address-cells = <1>;
0236 #size-cells = <1>;
0237
0238 ths_calibration: thermal-sensor-calibration@34 {
0239 reg = <0x34 4>;
0240 };
0241 };
0242
0243 msgbox: mailbox@1c17000 {
0244 compatible = "allwinner,sun8i-h3-msgbox",
0245 "allwinner,sun6i-a31-msgbox";
0246 reg = <0x01c17000 0x1000>;
0247 clocks = <&ccu CLK_BUS_MSGBOX>;
0248 resets = <&ccu RST_BUS_MSGBOX>;
0249 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0250 #mbox-cells = <1>;
0251 };
0252
0253 usb_otg: usb@1c19000 {
0254 compatible = "allwinner,sun8i-h3-musb";
0255 reg = <0x01c19000 0x400>;
0256 clocks = <&ccu CLK_BUS_OTG>;
0257 resets = <&ccu RST_BUS_OTG>;
0258 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0259 interrupt-names = "mc";
0260 phys = <&usbphy 0>;
0261 phy-names = "usb";
0262 extcon = <&usbphy 0>;
0263 dr_mode = "otg";
0264 status = "disabled";
0265 };
0266
0267 usbphy: phy@1c19400 {
0268 compatible = "allwinner,sun8i-h3-usb-phy";
0269 reg = <0x01c19400 0x2c>,
0270 <0x01c1a800 0x4>,
0271 <0x01c1b800 0x4>,
0272 <0x01c1c800 0x4>,
0273 <0x01c1d800 0x4>;
0274 reg-names = "phy_ctrl",
0275 "pmu0",
0276 "pmu1",
0277 "pmu2",
0278 "pmu3";
0279 clocks = <&ccu CLK_USB_PHY0>,
0280 <&ccu CLK_USB_PHY1>,
0281 <&ccu CLK_USB_PHY2>,
0282 <&ccu CLK_USB_PHY3>;
0283 clock-names = "usb0_phy",
0284 "usb1_phy",
0285 "usb2_phy",
0286 "usb3_phy";
0287 resets = <&ccu RST_USB_PHY0>,
0288 <&ccu RST_USB_PHY1>,
0289 <&ccu RST_USB_PHY2>,
0290 <&ccu RST_USB_PHY3>;
0291 reset-names = "usb0_reset",
0292 "usb1_reset",
0293 "usb2_reset",
0294 "usb3_reset";
0295 status = "disabled";
0296 #phy-cells = <1>;
0297 };
0298
0299 ehci0: usb@1c1a000 {
0300 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
0301 reg = <0x01c1a000 0x100>;
0302 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0303 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
0304 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
0305 status = "disabled";
0306 };
0307
0308 ohci0: usb@1c1a400 {
0309 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
0310 reg = <0x01c1a400 0x100>;
0311 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0312 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
0313 <&ccu CLK_USB_OHCI0>;
0314 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
0315 status = "disabled";
0316 };
0317
0318 ehci1: usb@1c1b000 {
0319 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
0320 reg = <0x01c1b000 0x100>;
0321 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0322 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
0323 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
0324 phys = <&usbphy 1>;
0325 phy-names = "usb";
0326 status = "disabled";
0327 };
0328
0329 ohci1: usb@1c1b400 {
0330 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
0331 reg = <0x01c1b400 0x100>;
0332 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0333 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
0334 <&ccu CLK_USB_OHCI1>;
0335 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
0336 phys = <&usbphy 1>;
0337 phy-names = "usb";
0338 status = "disabled";
0339 };
0340
0341 ehci2: usb@1c1c000 {
0342 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
0343 reg = <0x01c1c000 0x100>;
0344 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0345 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
0346 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
0347 phys = <&usbphy 2>;
0348 phy-names = "usb";
0349 status = "disabled";
0350 };
0351
0352 ohci2: usb@1c1c400 {
0353 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
0354 reg = <0x01c1c400 0x100>;
0355 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0356 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
0357 <&ccu CLK_USB_OHCI2>;
0358 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
0359 phys = <&usbphy 2>;
0360 phy-names = "usb";
0361 status = "disabled";
0362 };
0363
0364 ehci3: usb@1c1d000 {
0365 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
0366 reg = <0x01c1d000 0x100>;
0367 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
0368 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
0369 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
0370 phys = <&usbphy 3>;
0371 phy-names = "usb";
0372 status = "disabled";
0373 };
0374
0375 ohci3: usb@1c1d400 {
0376 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
0377 reg = <0x01c1d400 0x100>;
0378 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0379 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
0380 <&ccu CLK_USB_OHCI3>;
0381 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
0382 phys = <&usbphy 3>;
0383 phy-names = "usb";
0384 status = "disabled";
0385 };
0386
0387 ccu: clock@1c20000 {
0388 /* compatible is in per SoC .dtsi file */
0389 reg = <0x01c20000 0x400>;
0390 clocks = <&osc24M>, <&rtc CLK_OSC32K>;
0391 clock-names = "hosc", "losc";
0392 #clock-cells = <1>;
0393 #reset-cells = <1>;
0394 };
0395
0396 pio: pinctrl@1c20800 {
0397 /* compatible is in per SoC .dtsi file */
0398 reg = <0x01c20800 0x400>;
0399 interrupt-parent = <&r_intc>;
0400 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0401 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0402 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
0403 <&rtc CLK_OSC32K>;
0404 clock-names = "apb", "hosc", "losc";
0405 gpio-controller;
0406 #gpio-cells = <3>;
0407 interrupt-controller;
0408 #interrupt-cells = <3>;
0409
0410 csi_pins: csi-pins {
0411 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
0412 "PE6", "PE7", "PE8", "PE9", "PE10",
0413 "PE11";
0414 function = "csi";
0415 };
0416
0417 emac_rgmii_pins: emac-rgmii-pins {
0418 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
0419 "PD5", "PD7", "PD8", "PD9", "PD10",
0420 "PD12", "PD13", "PD15", "PD16", "PD17";
0421 function = "emac";
0422 drive-strength = <40>;
0423 };
0424
0425 i2c0_pins: i2c0-pins {
0426 pins = "PA11", "PA12";
0427 function = "i2c0";
0428 };
0429
0430 i2c1_pins: i2c1-pins {
0431 pins = "PA18", "PA19";
0432 function = "i2c1";
0433 };
0434
0435 i2c2_pins: i2c2-pins {
0436 pins = "PE12", "PE13";
0437 function = "i2c2";
0438 };
0439
0440 mmc0_pins: mmc0-pins {
0441 pins = "PF0", "PF1", "PF2", "PF3",
0442 "PF4", "PF5";
0443 function = "mmc0";
0444 drive-strength = <30>;
0445 bias-pull-up;
0446 };
0447
0448 mmc1_pins: mmc1-pins {
0449 pins = "PG0", "PG1", "PG2", "PG3",
0450 "PG4", "PG5";
0451 function = "mmc1";
0452 drive-strength = <30>;
0453 bias-pull-up;
0454 };
0455
0456 mmc2_8bit_pins: mmc2-8bit-pins {
0457 pins = "PC5", "PC6", "PC8",
0458 "PC9", "PC10", "PC11",
0459 "PC12", "PC13", "PC14",
0460 "PC15", "PC16";
0461 function = "mmc2";
0462 drive-strength = <30>;
0463 bias-pull-up;
0464 };
0465
0466 spdif_tx_pin: spdif-tx-pin {
0467 pins = "PA17";
0468 function = "spdif";
0469 };
0470
0471 spi0_pins: spi0-pins {
0472 pins = "PC0", "PC1", "PC2", "PC3";
0473 function = "spi0";
0474 };
0475
0476 spi1_pins: spi1-pins {
0477 pins = "PA15", "PA16", "PA14", "PA13";
0478 function = "spi1";
0479 };
0480
0481 uart0_pa_pins: uart0-pa-pins {
0482 pins = "PA4", "PA5";
0483 function = "uart0";
0484 };
0485
0486 uart1_pins: uart1-pins {
0487 pins = "PG6", "PG7";
0488 function = "uart1";
0489 };
0490
0491 uart1_rts_cts_pins: uart1-rts-cts-pins {
0492 pins = "PG8", "PG9";
0493 function = "uart1";
0494 };
0495
0496 uart2_pins: uart2-pins {
0497 pins = "PA0", "PA1";
0498 function = "uart2";
0499 };
0500
0501 uart2_rts_cts_pins: uart2-rts-cts-pins {
0502 pins = "PA2", "PA3";
0503 function = "uart2";
0504 };
0505
0506 uart3_pins: uart3-pins {
0507 pins = "PA13", "PA14";
0508 function = "uart3";
0509 };
0510
0511 uart3_rts_cts_pins: uart3-rts-cts-pins {
0512 pins = "PA15", "PA16";
0513 function = "uart3";
0514 };
0515 };
0516
0517 timer@1c20c00 {
0518 compatible = "allwinner,sun8i-a23-timer";
0519 reg = <0x01c20c00 0xa0>;
0520 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0521 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0522 clocks = <&osc24M>;
0523 };
0524
0525 emac: ethernet@1c30000 {
0526 compatible = "allwinner,sun8i-h3-emac";
0527 syscon = <&syscon>;
0528 reg = <0x01c30000 0x10000>;
0529 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0530 interrupt-names = "macirq";
0531 resets = <&ccu RST_BUS_EMAC>;
0532 reset-names = "stmmaceth";
0533 clocks = <&ccu CLK_BUS_EMAC>;
0534 clock-names = "stmmaceth";
0535 status = "disabled";
0536
0537 mdio: mdio {
0538 #address-cells = <1>;
0539 #size-cells = <0>;
0540 compatible = "snps,dwmac-mdio";
0541 };
0542
0543 mdio-mux {
0544 compatible = "allwinner,sun8i-h3-mdio-mux";
0545 #address-cells = <1>;
0546 #size-cells = <0>;
0547
0548 mdio-parent-bus = <&mdio>;
0549 /* Only one MDIO is usable at the time */
0550 internal_mdio: mdio@1 {
0551 compatible = "allwinner,sun8i-h3-mdio-internal";
0552 reg = <1>;
0553 #address-cells = <1>;
0554 #size-cells = <0>;
0555
0556 int_mii_phy: ethernet-phy@1 {
0557 compatible = "ethernet-phy-ieee802.3-c22";
0558 reg = <1>;
0559 clocks = <&ccu CLK_BUS_EPHY>;
0560 resets = <&ccu RST_BUS_EPHY>;
0561 };
0562 };
0563
0564 external_mdio: mdio@2 {
0565 reg = <2>;
0566 #address-cells = <1>;
0567 #size-cells = <0>;
0568 };
0569 };
0570 };
0571
0572 mbus: dram-controller@1c62000 {
0573 /* compatible is in per SoC .dtsi file */
0574 reg = <0x01c62000 0x1000>,
0575 <0x01c63000 0x1000>;
0576 reg-names = "mbus", "dram";
0577 clocks = <&ccu CLK_MBUS>,
0578 <&ccu CLK_DRAM>,
0579 <&ccu CLK_BUS_DRAM>;
0580 clock-names = "mbus", "dram", "bus";
0581 #address-cells = <1>;
0582 #size-cells = <1>;
0583 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
0584 #interconnect-cells = <1>;
0585 };
0586
0587 spi0: spi@1c68000 {
0588 compatible = "allwinner,sun8i-h3-spi";
0589 reg = <0x01c68000 0x1000>;
0590 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0591 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
0592 clock-names = "ahb", "mod";
0593 dmas = <&dma 23>, <&dma 23>;
0594 dma-names = "rx", "tx";
0595 pinctrl-names = "default";
0596 pinctrl-0 = <&spi0_pins>;
0597 resets = <&ccu RST_BUS_SPI0>;
0598 status = "disabled";
0599 #address-cells = <1>;
0600 #size-cells = <0>;
0601 };
0602
0603 spi1: spi@1c69000 {
0604 compatible = "allwinner,sun8i-h3-spi";
0605 reg = <0x01c69000 0x1000>;
0606 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
0607 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
0608 clock-names = "ahb", "mod";
0609 dmas = <&dma 24>, <&dma 24>;
0610 dma-names = "rx", "tx";
0611 pinctrl-names = "default";
0612 pinctrl-0 = <&spi1_pins>;
0613 resets = <&ccu RST_BUS_SPI1>;
0614 status = "disabled";
0615 #address-cells = <1>;
0616 #size-cells = <0>;
0617 };
0618
0619 wdt0: watchdog@1c20ca0 {
0620 compatible = "allwinner,sun6i-a31-wdt";
0621 reg = <0x01c20ca0 0x20>;
0622 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0623 clocks = <&osc24M>;
0624 };
0625
0626 spdif: spdif@1c21000 {
0627 #sound-dai-cells = <0>;
0628 compatible = "allwinner,sun8i-h3-spdif";
0629 reg = <0x01c21000 0x400>;
0630 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0631 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
0632 resets = <&ccu RST_BUS_SPDIF>;
0633 clock-names = "apb", "spdif";
0634 dmas = <&dma 2>;
0635 dma-names = "tx";
0636 status = "disabled";
0637 };
0638
0639 pwm: pwm@1c21400 {
0640 compatible = "allwinner,sun8i-h3-pwm";
0641 reg = <0x01c21400 0x8>;
0642 clocks = <&osc24M>;
0643 #pwm-cells = <3>;
0644 status = "disabled";
0645 };
0646
0647 i2s0: i2s@1c22000 {
0648 #sound-dai-cells = <0>;
0649 compatible = "allwinner,sun8i-h3-i2s";
0650 reg = <0x01c22000 0x400>;
0651 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0652 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
0653 clock-names = "apb", "mod";
0654 dmas = <&dma 3>, <&dma 3>;
0655 resets = <&ccu RST_BUS_I2S0>;
0656 dma-names = "rx", "tx";
0657 status = "disabled";
0658 };
0659
0660 i2s1: i2s@1c22400 {
0661 #sound-dai-cells = <0>;
0662 compatible = "allwinner,sun8i-h3-i2s";
0663 reg = <0x01c22400 0x400>;
0664 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0665 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
0666 clock-names = "apb", "mod";
0667 dmas = <&dma 4>, <&dma 4>;
0668 resets = <&ccu RST_BUS_I2S1>;
0669 dma-names = "rx", "tx";
0670 status = "disabled";
0671 };
0672
0673 i2s2: i2s@1c22800 {
0674 #sound-dai-cells = <0>;
0675 compatible = "allwinner,sun8i-h3-i2s";
0676 reg = <0x01c22800 0x400>;
0677 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0678 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
0679 clock-names = "apb", "mod";
0680 dmas = <&dma 27>;
0681 resets = <&ccu RST_BUS_I2S2>;
0682 dma-names = "tx";
0683 status = "disabled";
0684 };
0685
0686 codec: codec@1c22c00 {
0687 #sound-dai-cells = <0>;
0688 compatible = "allwinner,sun8i-h3-codec";
0689 reg = <0x01c22c00 0x400>;
0690 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0691 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
0692 clock-names = "apb", "codec";
0693 resets = <&ccu RST_BUS_CODEC>;
0694 dmas = <&dma 15>, <&dma 15>;
0695 dma-names = "rx", "tx";
0696 allwinner,codec-analog-controls = <&codec_analog>;
0697 status = "disabled";
0698 };
0699
0700 uart0: serial@1c28000 {
0701 compatible = "snps,dw-apb-uart";
0702 reg = <0x01c28000 0x400>;
0703 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
0704 reg-shift = <2>;
0705 reg-io-width = <4>;
0706 clocks = <&ccu CLK_BUS_UART0>;
0707 resets = <&ccu RST_BUS_UART0>;
0708 dmas = <&dma 6>, <&dma 6>;
0709 dma-names = "rx", "tx";
0710 status = "disabled";
0711 };
0712
0713 uart1: serial@1c28400 {
0714 compatible = "snps,dw-apb-uart";
0715 reg = <0x01c28400 0x400>;
0716 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0717 reg-shift = <2>;
0718 reg-io-width = <4>;
0719 clocks = <&ccu CLK_BUS_UART1>;
0720 resets = <&ccu RST_BUS_UART1>;
0721 dmas = <&dma 7>, <&dma 7>;
0722 dma-names = "rx", "tx";
0723 status = "disabled";
0724 };
0725
0726 uart2: serial@1c28800 {
0727 compatible = "snps,dw-apb-uart";
0728 reg = <0x01c28800 0x400>;
0729 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0730 reg-shift = <2>;
0731 reg-io-width = <4>;
0732 clocks = <&ccu CLK_BUS_UART2>;
0733 resets = <&ccu RST_BUS_UART2>;
0734 dmas = <&dma 8>, <&dma 8>;
0735 dma-names = "rx", "tx";
0736 status = "disabled";
0737 };
0738
0739 uart3: serial@1c28c00 {
0740 compatible = "snps,dw-apb-uart";
0741 reg = <0x01c28c00 0x400>;
0742 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0743 reg-shift = <2>;
0744 reg-io-width = <4>;
0745 clocks = <&ccu CLK_BUS_UART3>;
0746 resets = <&ccu RST_BUS_UART3>;
0747 dmas = <&dma 9>, <&dma 9>;
0748 dma-names = "rx", "tx";
0749 status = "disabled";
0750 };
0751
0752 i2c0: i2c@1c2ac00 {
0753 compatible = "allwinner,sun6i-a31-i2c";
0754 reg = <0x01c2ac00 0x400>;
0755 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0756 clocks = <&ccu CLK_BUS_I2C0>;
0757 resets = <&ccu RST_BUS_I2C0>;
0758 pinctrl-names = "default";
0759 pinctrl-0 = <&i2c0_pins>;
0760 status = "disabled";
0761 #address-cells = <1>;
0762 #size-cells = <0>;
0763 };
0764
0765 i2c1: i2c@1c2b000 {
0766 compatible = "allwinner,sun6i-a31-i2c";
0767 reg = <0x01c2b000 0x400>;
0768 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0769 clocks = <&ccu CLK_BUS_I2C1>;
0770 resets = <&ccu RST_BUS_I2C1>;
0771 pinctrl-names = "default";
0772 pinctrl-0 = <&i2c1_pins>;
0773 status = "disabled";
0774 #address-cells = <1>;
0775 #size-cells = <0>;
0776 };
0777
0778 i2c2: i2c@1c2b400 {
0779 compatible = "allwinner,sun6i-a31-i2c";
0780 reg = <0x01c2b400 0x400>;
0781 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0782 clocks = <&ccu CLK_BUS_I2C2>;
0783 resets = <&ccu RST_BUS_I2C2>;
0784 pinctrl-names = "default";
0785 pinctrl-0 = <&i2c2_pins>;
0786 status = "disabled";
0787 #address-cells = <1>;
0788 #size-cells = <0>;
0789 };
0790
0791 gic: interrupt-controller@1c81000 {
0792 compatible = "arm,gic-400";
0793 reg = <0x01c81000 0x1000>,
0794 <0x01c82000 0x2000>,
0795 <0x01c84000 0x2000>,
0796 <0x01c86000 0x2000>;
0797 interrupt-controller;
0798 #interrupt-cells = <3>;
0799 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0800 };
0801
0802 csi: camera@1cb0000 {
0803 compatible = "allwinner,sun8i-h3-csi";
0804 reg = <0x01cb0000 0x1000>;
0805 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0806 clocks = <&ccu CLK_BUS_CSI>,
0807 <&ccu CLK_CSI_SCLK>,
0808 <&ccu CLK_DRAM_CSI>;
0809 clock-names = "bus", "mod", "ram";
0810 resets = <&ccu RST_BUS_CSI>;
0811 pinctrl-names = "default";
0812 pinctrl-0 = <&csi_pins>;
0813 status = "disabled";
0814 };
0815
0816 hdmi: hdmi@1ee0000 {
0817 compatible = "allwinner,sun8i-h3-dw-hdmi",
0818 "allwinner,sun8i-a83t-dw-hdmi";
0819 reg = <0x01ee0000 0x10000>;
0820 reg-io-width = <1>;
0821 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
0822 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
0823 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
0824 clock-names = "iahb", "isfr", "tmds", "cec";
0825 resets = <&ccu RST_BUS_HDMI1>;
0826 reset-names = "ctrl";
0827 phys = <&hdmi_phy>;
0828 phy-names = "phy";
0829 status = "disabled";
0830
0831 ports {
0832 #address-cells = <1>;
0833 #size-cells = <0>;
0834
0835 hdmi_in: port@0 {
0836 reg = <0>;
0837
0838 hdmi_in_tcon0: endpoint {
0839 remote-endpoint = <&tcon0_out_hdmi>;
0840 };
0841 };
0842
0843 hdmi_out: port@1 {
0844 reg = <1>;
0845 };
0846 };
0847 };
0848
0849 hdmi_phy: hdmi-phy@1ef0000 {
0850 compatible = "allwinner,sun8i-h3-hdmi-phy";
0851 reg = <0x01ef0000 0x10000>;
0852 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
0853 <&ccu CLK_PLL_VIDEO>;
0854 clock-names = "bus", "mod", "pll-0";
0855 resets = <&ccu RST_BUS_HDMI0>;
0856 reset-names = "phy";
0857 #phy-cells = <0>;
0858 };
0859
0860 rtc: rtc@1f00000 {
0861 /* compatible is in per SoC .dtsi file */
0862 reg = <0x01f00000 0x400>;
0863 interrupt-parent = <&r_intc>;
0864 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
0865 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
0866 clock-output-names = "osc32k", "osc32k-out", "iosc";
0867 clocks = <&osc32k>;
0868 #clock-cells = <1>;
0869 };
0870
0871 r_intc: interrupt-controller@1f00c00 {
0872 compatible = "allwinner,sun8i-h3-r-intc",
0873 "allwinner,sun6i-a31-r-intc";
0874 interrupt-controller;
0875 #interrupt-cells = <3>;
0876 reg = <0x01f00c00 0x400>;
0877 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0878 };
0879
0880 r_ccu: clock@1f01400 {
0881 compatible = "allwinner,sun8i-h3-r-ccu";
0882 reg = <0x01f01400 0x100>;
0883 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
0884 <&ccu CLK_PLL_PERIPH0>;
0885 clock-names = "hosc", "losc", "iosc", "pll-periph";
0886 #clock-cells = <1>;
0887 #reset-cells = <1>;
0888 };
0889
0890 codec_analog: codec-analog@1f015c0 {
0891 compatible = "allwinner,sun8i-h3-codec-analog";
0892 reg = <0x01f015c0 0x4>;
0893 };
0894
0895 ir: ir@1f02000 {
0896 compatible = "allwinner,sun6i-a31-ir";
0897 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
0898 clock-names = "apb", "ir";
0899 resets = <&r_ccu RST_APB0_IR>;
0900 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0901 reg = <0x01f02000 0x400>;
0902 status = "disabled";
0903 };
0904
0905 r_i2c: i2c@1f02400 {
0906 compatible = "allwinner,sun6i-a31-i2c";
0907 reg = <0x01f02400 0x400>;
0908 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
0909 pinctrl-names = "default";
0910 pinctrl-0 = <&r_i2c_pins>;
0911 clocks = <&r_ccu CLK_APB0_I2C>;
0912 resets = <&r_ccu RST_APB0_I2C>;
0913 status = "disabled";
0914 #address-cells = <1>;
0915 #size-cells = <0>;
0916 };
0917
0918 r_uart: serial@1f02800 {
0919 compatible = "snps,dw-apb-uart";
0920 reg = <0x01f02800 0x400>;
0921 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0922 reg-shift = <2>;
0923 reg-io-width = <4>;
0924 clocks = <&r_ccu CLK_APB0_UART>;
0925 resets = <&r_ccu RST_APB0_UART>;
0926 pinctrl-names = "default";
0927 pinctrl-0 = <&r_uart_pins>;
0928 status = "disabled";
0929 };
0930
0931 r_pio: pinctrl@1f02c00 {
0932 compatible = "allwinner,sun8i-h3-r-pinctrl";
0933 reg = <0x01f02c00 0x400>;
0934 interrupt-parent = <&r_intc>;
0935 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0936 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
0937 <&rtc CLK_OSC32K>;
0938 clock-names = "apb", "hosc", "losc";
0939 gpio-controller;
0940 #gpio-cells = <3>;
0941 interrupt-controller;
0942 #interrupt-cells = <3>;
0943
0944 r_ir_rx_pin: r-ir-rx-pin {
0945 pins = "PL11";
0946 function = "s_cir_rx";
0947 };
0948
0949 r_i2c_pins: r-i2c-pins {
0950 pins = "PL0", "PL1";
0951 function = "s_i2c";
0952 };
0953
0954 r_pwm_pin: r-pwm-pin {
0955 pins = "PL10";
0956 function = "s_pwm";
0957 };
0958
0959 r_uart_pins: r-uart-pins {
0960 pins = "PL2", "PL3";
0961 function = "s_uart";
0962 };
0963 };
0964
0965 r_pwm: pwm@1f03800 {
0966 compatible = "allwinner,sun8i-h3-pwm";
0967 reg = <0x01f03800 0x8>;
0968 pinctrl-names = "default";
0969 pinctrl-0 = <&r_pwm_pin>;
0970 clocks = <&osc24M>;
0971 #pwm-cells = <3>;
0972 status = "disabled";
0973 };
0974 };
0975 };
