0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for Sunplus SP7021
0004 *
0005 * Copyright (C) 2021 Sunplus Technology Co.
0006 */
0007
0008 #include <dt-bindings/clock/sunplus,sp7021-clkc.h>
0009 #include <dt-bindings/interrupt-controller/irq.h>
0010 #include <dt-bindings/reset/sunplus,sp7021-reset.h>
0011 #include <dt-bindings/pinctrl/sppctl-sp7021.h>
0012 #include <dt-bindings/gpio/gpio.h>
0013
0014 #define XTAL 27000000
0015
0016 / {
0017 compatible = "sunplus,sp7021";
0018 model = "Sunplus SP7021";
0019
0020 clocks {
0021 extclk: osc0 {
0022 compatible = "fixed-clock";
0023 #clock-cells = <0>;
0024 clock-frequency = <XTAL>;
0025 clock-output-names = "extclk";
0026 };
0027 };
0028
0029 soc@9c000000 {
0030 compatible = "simple-bus";
0031 #address-cells = <1>;
0032 #size-cells = <1>;
0033 ranges = <0 0x9c000000 0x400000>;
0034 interrupt-parent = <&intc>;
0035
0036 clkc: clock-controller@4 {
0037 compatible = "sunplus,sp7021-clkc";
0038 reg = <0x4 0x28>,
0039 <0x200 0x44>,
0040 <0x268 0x04>;
0041 clocks = <&extclk>;
0042 #clock-cells = <1>;
0043 };
0044
0045 intc: interrupt-controller@780 {
0046 compatible = "sunplus,sp7021-intc";
0047 reg = <0x780 0x80>, <0xa80 0x80>;
0048 interrupt-controller;
0049 #interrupt-cells = <2>;
0050 };
0051
0052 otp: otp@af00 {
0053 compatible = "sunplus,sp7021-ocotp";
0054 reg = <0xaf00 0x34>, <0xaf80 0x58>;
0055 reg-names = "hb_gpio", "otprx";
0056 clocks = <&clkc CLK_OTPRX>;
0057 resets = <&rstc RST_OTPRX>;
0058 #address-cells = <1>;
0059 #size-cells = <1>;
0060
0061 therm_calib: thermal-calibration@14 {
0062 reg = <0x14 0x3>;
0063 };
0064 disc_vol: disconnect-voltage@18 {
0065 reg = <0x18 0x2>;
0066 };
0067 mac_addr0: mac-address0@34 {
0068 reg = <0x34 0x6>;
0069 };
0070 mac_addr1: mac-address1@3a {
0071 reg = <0x3a 0x6>;
0072 };
0073 };
0074
0075 pctl: pinctrl@100 {
0076 compatible = "sunplus,sp7021-pctl";
0077 reg = <0x100 0x100>,
0078 <0x300 0x100>,
0079 <0x32e4 0x1C>,
0080 <0x80 0x20>;
0081 reg-names = "moon2", "gpioxt", "first", "moon1";
0082 gpio-controller;
0083 #gpio-cells = <2>;
0084 clocks = <&clkc CLK_GPIO>;
0085 resets = <&rstc RST_GPIO>;
0086
0087 emac_pins: pinmux-emac-pins {
0088 sunplus,pins = <
0089 SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0)
0090 SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0)
0091 SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0)
0092 SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0)
0093 SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0)
0094 SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0)
0095 SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0)
0096 SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0)
0097 SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0)
0098 SPPCTL_IOPAD(45,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXER,0)
0099 SPPCTL_IOPAD(59,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXEN,0)
0100 SPPCTL_IOPAD(57,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD0,0)
0101 SPPCTL_IOPAD(58,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_TXD1,0)
0102 SPPCTL_IOPAD(54,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_CRSDV,0)
0103 SPPCTL_IOPAD(55,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD0,0)
0104 SPPCTL_IOPAD(56,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXD1,0)
0105 SPPCTL_IOPAD(53,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P1_MAC_RMII_RXER,0)
0106 >;
0107 sunplus,zerofunc = <
0108 MUXF_L2SW_LED_FLASH0
0109 MUXF_L2SW_LED_FLASH1
0110 MUXF_L2SW_LED_ON0
0111 MUXF_L2SW_LED_ON1
0112 MUXF_DAISY_MODE
0113 >;
0114 };
0115
0116 emmc_pins: pinmux-emmc-pins {
0117 function = "CARD0_EMMC";
0118 groups = "CARD0_EMMC";
0119 };
0120
0121 leds_pins: pinmux-leds-pins {
0122 sunplus,pins = < SPPCTL_IOPAD(0,SPPCTL_PCTL_G_GPIO,0,SPPCTL_PCTL_L_OUT) >;
0123 };
0124
0125 sdcard_pins: pinmux-sdcard-pins {
0126 function = "SD_CARD";
0127 groups = "SD_CARD";
0128 sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >;
0129 };
0130
0131 spi0_pins: pinmux-spi0-pins {
0132 sunplus,pins = <
0133 SPPCTL_IOPAD(26,SPPCTL_PCTL_G_GPIO,0,0)
0134 SPPCTL_IOPAD(28,SPPCTL_PCTL_G_GPIO,0,0)
0135 SPPCTL_IOPAD(23,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_DO,0)
0136 SPPCTL_IOPAD(25,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_DI,0)
0137 SPPCTL_IOPAD(27,SPPCTL_PCTL_G_PMUX,MUXF_SPI0S_CLK,0)
0138 >;
0139 };
0140
0141 uart0_pins: pinmux-uart0-pins {
0142 function = "UA0";
0143 groups = "UA0";
0144 };
0145
0146 uart1_pins: pinmux-uart1-pins {
0147 sunplus,pins = <
0148 SPPCTL_IOPAD(14,SPPCTL_PCTL_G_PMUX,MUXF_UA4_TX,0)
0149 SPPCTL_IOPAD(16,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RX,0)
0150 >;
0151 };
0152
0153 uart2_pins: pinmux-uart2-pins {
0154 sunplus,pins = <
0155 SPPCTL_IOPAD(16,SPPCTL_PCTL_G_PMUX,MUXF_UA2_TX,0)
0156 SPPCTL_IOPAD(17,SPPCTL_PCTL_G_PMUX,MUXF_UA2_RX,0)
0157 SPPCTL_IOPAD(18,SPPCTL_PCTL_G_PMUX,MUXF_UA2_RTS,0)
0158 SPPCTL_IOPAD(19,SPPCTL_PCTL_G_PMUX,MUXF_UA2_CTS,0)
0159 >;
0160 };
0161
0162 uart4_pins: pinmux-uart4-pins {
0163 sunplus,pins = <
0164 SPPCTL_IOPAD(22,SPPCTL_PCTL_G_PMUX,MUXF_UA4_TX,0)
0165 SPPCTL_IOPAD(20,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RX,0)
0166 SPPCTL_IOPAD(23,SPPCTL_PCTL_G_PMUX,MUXF_UA4_RTS,0)
0167 SPPCTL_IOPAD(21,SPPCTL_PCTL_G_PMUX,MUXF_UA4_CTS,0)
0168 >;
0169 };
0170 };
0171
0172 rstc: reset@54 {
0173 compatible = "sunplus,sp7021-reset";
0174 reg = <0x54 0x28>;
0175 #reset-cells = <1>;
0176 };
0177
0178 rtc: rtc@3a00 {
0179 compatible = "sunplus,sp7021-rtc";
0180 reg = <0x3a00 0x80>;
0181 reg-names = "rtc";
0182 clocks = <&clkc CLK_RTC>;
0183 resets = <&rstc RST_RTC>;
0184 interrupts = <163 IRQ_TYPE_EDGE_RISING>;
0185 };
0186
0187 spi_controller0: spi@2d80 {
0188 compatible = "sunplus,sp7021-spi";
0189 reg = <0x2d80 0x80>, <0x2e00 0x80>;
0190 reg-names = "master", "slave";
0191 interrupts = <144 IRQ_TYPE_LEVEL_HIGH>,
0192 <146 IRQ_TYPE_LEVEL_HIGH>,
0193 <145 IRQ_TYPE_LEVEL_HIGH>;
0194 interrupt-names = "dma_w", "master_risc", "slave_risc";
0195 clocks = <&clkc CLK_SPI_COMBO_0>;
0196 resets = <&rstc RST_SPI_COMBO_0>;
0197
0198 pinctrl-names = "default";
0199 pinctrl-0 = <&spi0_pins>;
0200 cs-gpios = <&pctl 26 GPIO_ACTIVE_LOW>,
0201 <&pctl 28 GPIO_ACTIVE_LOW>;
0202 };
0203
0204 spi_controller1: spi@f480 {
0205 compatible = "sunplus,sp7021-spi";
0206 reg = <0xf480 0x80>, <0xf500 0x80>;
0207 reg-names = "master", "slave";
0208 interrupts = <67 IRQ_TYPE_LEVEL_HIGH>,
0209 <69 IRQ_TYPE_LEVEL_HIGH>,
0210 <68 IRQ_TYPE_LEVEL_HIGH>;
0211 interrupt-names = "dma_w", "master_risc", "slave_risc";
0212 clocks = <&clkc CLK_SPI_COMBO_1>;
0213 resets = <&rstc RST_SPI_COMBO_1>;
0214 spi-max-frequency = <25000000>;
0215 status = "disabled";
0216 };
0217
0218 spi_controller2: spi@f600 {
0219 compatible = "sunplus,sp7021-spi";
0220 reg = <0xf600 0x80>, <0xf680 0x80>;
0221 reg-names = "master", "slave";
0222 interrupts = <70 IRQ_TYPE_LEVEL_HIGH>,
0223 <72 IRQ_TYPE_LEVEL_HIGH>,
0224 <71 IRQ_TYPE_LEVEL_HIGH>;
0225 interrupt-names = "dma_w", "master_risc", "slave_risc";
0226 clocks = <&clkc CLK_SPI_COMBO_2>;
0227 resets = <&rstc RST_SPI_COMBO_2>;
0228 spi-max-frequency = <25000000>;
0229 status = "disabled";
0230 };
0231
0232 spi_controller3: spi@f780 {
0233 compatible = "sunplus,sp7021-spi";
0234 reg = <0xf780 0x80>, <0xf800 0x80>;
0235 reg-names = "master", "slave";
0236 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>,
0237 <75 IRQ_TYPE_LEVEL_HIGH>,
0238 <74 IRQ_TYPE_LEVEL_HIGH>;
0239 interrupt-names = "dma_w", "master_risc", "slave_risc";
0240 clocks = <&clkc CLK_SPI_COMBO_3>;
0241 resets = <&rstc RST_SPI_COMBO_3>;
0242 spi-max-frequency = <25000000>;
0243 status = "disabled";
0244 };
0245
0246 uart0: serial@900 {
0247 compatible = "sunplus,sp7021-uart";
0248 reg = <0x900 0x80>;
0249 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
0250 clocks = <&clkc CLK_UA0>;
0251 resets = <&rstc RST_UA0>;
0252 pinctrl-names = "default";
0253 pinctrl-0 = <&uart0_pins>;
0254 };
0255
0256 uart1: serial@980 {
0257 compatible = "sunplus,sp7021-uart";
0258 reg = <0x980 0x80>;
0259 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
0260 clocks = <&clkc CLK_UA1>;
0261 resets = <&rstc RST_UA1>;
0262 pinctrl-names = "default";
0263 pinctrl-0 = <&uart1_pins>;
0264 status = "disabled";
0265 };
0266
0267 uart2: serial@800 {
0268 compatible = "sunplus,sp7021-uart";
0269 reg = <0x800 0x80>;
0270 interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
0271 clocks = <&clkc CLK_UA2>;
0272 resets = <&rstc RST_UA2>;
0273 pinctrl-names = "default";
0274 pinctrl-0 = <&uart2_pins>;
0275 status = "disabled";
0276 };
0277
0278 uart3: serial@880 {
0279 compatible = "sunplus,sp7021-uart";
0280 reg = <0x880 0x80>;
0281 interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
0282 clocks = <&clkc CLK_UA3>;
0283 resets = <&rstc RST_UA3>;
0284 status = "disabled";
0285 };
0286
0287 uart4: serial@8780 {
0288 compatible = "sunplus,sp7021-uart";
0289 reg = <0x8780 0x80>;
0290 interrupts = <134 IRQ_TYPE_LEVEL_HIGH>;
0291 clocks = <&clkc CLK_UA4>;
0292 resets = <&rstc RST_UA4>;
0293 pinctrl-names = "default";
0294 pinctrl-0 = <&uart4_pins>;
0295 status = "disabled";
0296 };
0297 };
0298
0299 leds {
0300 compatible = "gpio-leds";
0301 pinctrl-names = "default";
0302 pinctrl-0 = <&leds_pins>;
0303 system-led {
0304 label = "system-led";
0305 gpios = <&pctl 0 GPIO_ACTIVE_HIGH>;
0306 default-state = "off";
0307 linux,default-trigger = "heartbeat";
0308 };
0309 };
0310 };
