0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for Sunplus SP7021
0004 *
0005 * Copyright (C) 2021 Sunplus Technology Co.
0006 */
0007
0008 #include "sunplus-sp7021.dtsi"
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010
0011 / {
0012 compatible = "sunplus,sp7021-achip", "sunplus,sp7021";
0013 model = "Sunplus SP7021 (CA7)";
0014 #address-cells = <1>;
0015 #size-cells = <1>;
0016 interrupt-parent = <&gic>;
0017
0018 cpus {
0019 #address-cells = <1>;
0020 #size-cells = <0>;
0021
0022 cpu0: cpu@0 {
0023 compatible = "arm,cortex-a7";
0024 device_type = "cpu";
0025 reg = <0>;
0026 clock-frequency = <931000000>;
0027 };
0028 cpu1: cpu@1 {
0029 compatible = "arm,cortex-a7";
0030 device_type = "cpu";
0031 reg = <1>;
0032 clock-frequency = <931000000>;
0033 };
0034 cpu2: cpu@2 {
0035 compatible = "arm,cortex-a7";
0036 device_type = "cpu";
0037 reg = <2>;
0038 clock-frequency = <931000000>;
0039 };
0040 cpu3: cpu@3 {
0041 compatible = "arm,cortex-a7";
0042 device_type = "cpu";
0043 reg = <3>;
0044 clock-frequency = <931000000>;
0045 };
0046 };
0047
0048 gic: interrupt-controller@9f101000 {
0049 compatible = "arm,cortex-a7-gic";
0050 interrupt-controller;
0051 #interrupt-cells = <3>;
0052 reg = <0x9f101000 0x1000>,
0053 <0x9f102000 0x2000>,
0054 <0x9f104000 0x2000>,
0055 <0x9f106000 0x2000>;
0056 };
0057
0058 timer {
0059 compatible = "arm,armv7-timer";
0060 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0061 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0062 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0063 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0064 clock-frequency = <XTAL>;
0065 arm,cpu-registers-not-fw-configured;
0066 };
0067
0068 arm-pmu {
0069 compatible = "arm,cortex-a7-pmu";
0070 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
0071 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
0072 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
0073 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
0074 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0075 };
0076
0077 soc@9c000000 {
0078 intc: interrupt-controller@780 {
0079 interrupt-parent = <&gic>;
0080 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, /* EXT_INT0 */
0081 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; /* EXT_INT1 */
0082 };
0083 };
0084 };
