0001 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
0002 /*
0003 * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
0004 * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
0005 */
0006
0007 #include <dt-bindings/clock/suniv-ccu-f1c100s.h>
0008 #include <dt-bindings/reset/suniv-ccu-f1c100s.h>
0009
0010 / {
0011 #address-cells = <1>;
0012 #size-cells = <1>;
0013 interrupt-parent = <&intc>;
0014
0015 clocks {
0016 osc24M: clk-24M {
0017 #clock-cells = <0>;
0018 compatible = "fixed-clock";
0019 clock-frequency = <24000000>;
0020 clock-output-names = "osc24M";
0021 };
0022
0023 osc32k: clk-32k {
0024 #clock-cells = <0>;
0025 compatible = "fixed-clock";
0026 clock-frequency = <32768>;
0027 clock-output-names = "osc32k";
0028 };
0029 };
0030
0031 cpus {
0032 #address-cells = <1>;
0033 #size-cells = <0>;
0034
0035 cpu@0 {
0036 compatible = "arm,arm926ej-s";
0037 device_type = "cpu";
0038 reg = <0x0>;
0039 };
0040 };
0041
0042 soc {
0043 compatible = "simple-bus";
0044 #address-cells = <1>;
0045 #size-cells = <1>;
0046 ranges;
0047
0048 sram-controller@1c00000 {
0049 compatible = "allwinner,suniv-f1c100s-system-control",
0050 "allwinner,sun4i-a10-system-control";
0051 reg = <0x01c00000 0x30>;
0052 #address-cells = <1>;
0053 #size-cells = <1>;
0054 ranges;
0055
0056 sram_d: sram@10000 {
0057 compatible = "mmio-sram";
0058 reg = <0x00010000 0x1000>;
0059 #address-cells = <1>;
0060 #size-cells = <1>;
0061 ranges = <0 0x00010000 0x1000>;
0062
0063 otg_sram: sram-section@0 {
0064 compatible = "allwinner,suniv-f1c100s-sram-d",
0065 "allwinner,sun4i-a10-sram-d";
0066 reg = <0x0000 0x1000>;
0067 status = "disabled";
0068 };
0069 };
0070 };
0071
0072 spi0: spi@1c05000 {
0073 compatible = "allwinner,suniv-f1c100s-spi",
0074 "allwinner,sun8i-h3-spi";
0075 reg = <0x01c05000 0x1000>;
0076 interrupts = <10>;
0077 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_BUS_SPI0>;
0078 clock-names = "ahb", "mod";
0079 resets = <&ccu RST_BUS_SPI0>;
0080 status = "disabled";
0081 num-cs = <1>;
0082 #address-cells = <1>;
0083 #size-cells = <0>;
0084 };
0085
0086 spi1: spi@1c06000 {
0087 compatible = "allwinner,suniv-f1c100s-spi",
0088 "allwinner,sun8i-h3-spi";
0089 reg = <0x01c06000 0x1000>;
0090 interrupts = <11>;
0091 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_BUS_SPI1>;
0092 clock-names = "ahb", "mod";
0093 resets = <&ccu RST_BUS_SPI1>;
0094 status = "disabled";
0095 num-cs = <1>;
0096 #address-cells = <1>;
0097 #size-cells = <0>;
0098 };
0099
0100 mmc0: mmc@1c0f000 {
0101 compatible = "allwinner,suniv-f1c100s-mmc",
0102 "allwinner,sun7i-a20-mmc";
0103 reg = <0x01c0f000 0x1000>;
0104 clocks = <&ccu CLK_BUS_MMC0>,
0105 <&ccu CLK_MMC0>,
0106 <&ccu CLK_MMC0_OUTPUT>,
0107 <&ccu CLK_MMC0_SAMPLE>;
0108 clock-names = "ahb", "mmc", "output", "sample";
0109 resets = <&ccu RST_BUS_MMC0>;
0110 reset-names = "ahb";
0111 interrupts = <23>;
0112 pinctrl-names = "default";
0113 pinctrl-0 = <&mmc0_pins>;
0114 status = "disabled";
0115 #address-cells = <1>;
0116 #size-cells = <0>;
0117 };
0118
0119 mmc1: mmc@1c10000 {
0120 compatible = "allwinner,suniv-f1c100s-mmc",
0121 "allwinner,sun7i-a20-mmc";
0122 reg = <0x01c10000 0x1000>;
0123 clocks = <&ccu CLK_BUS_MMC1>,
0124 <&ccu CLK_MMC1>,
0125 <&ccu CLK_MMC1_OUTPUT>,
0126 <&ccu CLK_MMC1_SAMPLE>;
0127 clock-names = "ahb", "mmc", "output", "sample";
0128 resets = <&ccu RST_BUS_MMC1>;
0129 reset-names = "ahb";
0130 interrupts = <24>;
0131 status = "disabled";
0132 #address-cells = <1>;
0133 #size-cells = <0>;
0134 };
0135
0136 ccu: clock@1c20000 {
0137 compatible = "allwinner,suniv-f1c100s-ccu";
0138 reg = <0x01c20000 0x400>;
0139 clocks = <&osc24M>, <&osc32k>;
0140 clock-names = "hosc", "losc";
0141 #clock-cells = <1>;
0142 #reset-cells = <1>;
0143 };
0144
0145 intc: interrupt-controller@1c20400 {
0146 compatible = "allwinner,suniv-f1c100s-ic";
0147 reg = <0x01c20400 0x400>;
0148 interrupt-controller;
0149 #interrupt-cells = <1>;
0150 };
0151
0152 pio: pinctrl@1c20800 {
0153 compatible = "allwinner,suniv-f1c100s-pinctrl";
0154 reg = <0x01c20800 0x400>;
0155 interrupts = <38>, <39>, <40>;
0156 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
0157 clock-names = "apb", "hosc", "losc";
0158 gpio-controller;
0159 interrupt-controller;
0160 #interrupt-cells = <3>;
0161 #gpio-cells = <3>;
0162
0163 mmc0_pins: mmc0-pins {
0164 pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
0165 function = "mmc0";
0166 drive-strength = <30>;
0167 };
0168
0169 spi0_pc_pins: spi0-pc-pins {
0170 pins = "PC0", "PC1", "PC2", "PC3";
0171 function = "spi0";
0172 };
0173
0174 uart0_pe_pins: uart0-pe-pins {
0175 pins = "PE0", "PE1";
0176 function = "uart0";
0177 };
0178 };
0179
0180 timer@1c20c00 {
0181 compatible = "allwinner,suniv-f1c100s-timer";
0182 reg = <0x01c20c00 0x90>;
0183 interrupts = <13>, <14>, <15>;
0184 clocks = <&osc24M>;
0185 };
0186
0187 wdt: watchdog@1c20ca0 {
0188 compatible = "allwinner,suniv-f1c100s-wdt",
0189 "allwinner,sun6i-a31-wdt";
0190 reg = <0x01c20ca0 0x20>;
0191 interrupts = <16>;
0192 clocks = <&osc32k>;
0193 };
0194
0195 uart0: serial@1c25000 {
0196 compatible = "snps,dw-apb-uart";
0197 reg = <0x01c25000 0x400>;
0198 interrupts = <1>;
0199 reg-shift = <2>;
0200 reg-io-width = <4>;
0201 clocks = <&ccu CLK_BUS_UART0>;
0202 resets = <&ccu RST_BUS_UART0>;
0203 status = "disabled";
0204 };
0205
0206 uart1: serial@1c25400 {
0207 compatible = "snps,dw-apb-uart";
0208 reg = <0x01c25400 0x400>;
0209 interrupts = <2>;
0210 reg-shift = <2>;
0211 reg-io-width = <4>;
0212 clocks = <&ccu CLK_BUS_UART1>;
0213 resets = <&ccu RST_BUS_UART1>;
0214 status = "disabled";
0215 };
0216
0217 uart2: serial@1c25800 {
0218 compatible = "snps,dw-apb-uart";
0219 reg = <0x01c25800 0x400>;
0220 interrupts = <3>;
0221 reg-shift = <2>;
0222 reg-io-width = <4>;
0223 clocks = <&ccu CLK_BUS_UART2>;
0224 resets = <&ccu RST_BUS_UART2>;
0225 status = "disabled";
0226 };
0227 };
0228 };
