0001 /*
0002 * Copyright 2014 Chen-Yu Tsai
0003 *
0004 * Chen-Yu Tsai <wens@csie.org>
0005 *
0006 * This file is dual-licensed: you can use it either under the terms
0007 * of the GPL or the X11 license, at your option. Note that this dual
0008 * licensing only applies to this file, and not this project as a
0009 * whole.
0010 *
0011 * a) This file is free software; you can redistribute it and/or
0012 * modify it under the terms of the GNU General Public License as
0013 * published by the Free Software Foundation; either version 2 of the
0014 * License, or (at your option) any later version.
0015 *
0016 * This file is distributed in the hope that it will be useful,
0017 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0019 * GNU General Public License for more details.
0020 *
0021 * Or, alternatively,
0022 *
0023 * b) Permission is hereby granted, free of charge, to any person
0024 * obtaining a copy of this software and associated documentation
0025 * files (the "Software"), to deal in the Software without
0026 * restriction, including without limitation the rights to use,
0027 * copy, modify, merge, publish, distribute, sublicense, and/or
0028 * sell copies of the Software, and to permit persons to whom the
0029 * Software is furnished to do so, subject to the following
0030 * conditions:
0031 *
0032 * The above copyright notice and this permission notice shall be
0033 * included in all copies or substantial portions of the Software.
0034 *
0035 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0036 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0037 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0038 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0039 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0040 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0041 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0042 * OTHER DEALINGS IN THE SOFTWARE.
0043 */
0044
0045 #include <dt-bindings/interrupt-controller/arm-gic.h>
0046
0047 #include <dt-bindings/clock/sun9i-a80-ccu.h>
0048 #include <dt-bindings/clock/sun9i-a80-de.h>
0049 #include <dt-bindings/clock/sun9i-a80-usb.h>
0050 #include <dt-bindings/reset/sun9i-a80-ccu.h>
0051 #include <dt-bindings/reset/sun9i-a80-de.h>
0052 #include <dt-bindings/reset/sun9i-a80-usb.h>
0053
0054 / {
0055 #address-cells = <2>;
0056 #size-cells = <2>;
0057 interrupt-parent = <&gic>;
0058
0059 aliases {
0060 ethernet0 = &gmac;
0061 };
0062
0063 cpus {
0064 #address-cells = <1>;
0065 #size-cells = <0>;
0066
0067 cpu0: cpu@0 {
0068 compatible = "arm,cortex-a7";
0069 device_type = "cpu";
0070 cci-control-port = <&cci_control0>;
0071 clock-frequency = <12000000>;
0072 enable-method = "allwinner,sun9i-a80-smp";
0073 reg = <0x0>;
0074 };
0075
0076 cpu1: cpu@1 {
0077 compatible = "arm,cortex-a7";
0078 device_type = "cpu";
0079 cci-control-port = <&cci_control0>;
0080 clock-frequency = <12000000>;
0081 enable-method = "allwinner,sun9i-a80-smp";
0082 reg = <0x1>;
0083 };
0084
0085 cpu2: cpu@2 {
0086 compatible = "arm,cortex-a7";
0087 device_type = "cpu";
0088 cci-control-port = <&cci_control0>;
0089 clock-frequency = <12000000>;
0090 enable-method = "allwinner,sun9i-a80-smp";
0091 reg = <0x2>;
0092 };
0093
0094 cpu3: cpu@3 {
0095 compatible = "arm,cortex-a7";
0096 device_type = "cpu";
0097 cci-control-port = <&cci_control0>;
0098 clock-frequency = <12000000>;
0099 enable-method = "allwinner,sun9i-a80-smp";
0100 reg = <0x3>;
0101 };
0102
0103 cpu4: cpu@100 {
0104 compatible = "arm,cortex-a15";
0105 device_type = "cpu";
0106 cci-control-port = <&cci_control1>;
0107 clock-frequency = <18000000>;
0108 enable-method = "allwinner,sun9i-a80-smp";
0109 reg = <0x100>;
0110 };
0111
0112 cpu5: cpu@101 {
0113 compatible = "arm,cortex-a15";
0114 device_type = "cpu";
0115 cci-control-port = <&cci_control1>;
0116 clock-frequency = <18000000>;
0117 enable-method = "allwinner,sun9i-a80-smp";
0118 reg = <0x101>;
0119 };
0120
0121 cpu6: cpu@102 {
0122 compatible = "arm,cortex-a15";
0123 device_type = "cpu";
0124 cci-control-port = <&cci_control1>;
0125 clock-frequency = <18000000>;
0126 enable-method = "allwinner,sun9i-a80-smp";
0127 reg = <0x102>;
0128 };
0129
0130 cpu7: cpu@103 {
0131 compatible = "arm,cortex-a15";
0132 device_type = "cpu";
0133 cci-control-port = <&cci_control1>;
0134 clock-frequency = <18000000>;
0135 enable-method = "allwinner,sun9i-a80-smp";
0136 reg = <0x103>;
0137 };
0138 };
0139
0140 timer {
0141 compatible = "arm,armv7-timer";
0142 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0143 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0144 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0145 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0146 clock-frequency = <24000000>;
0147 arm,cpu-registers-not-fw-configured;
0148 };
0149
0150 clocks {
0151 #address-cells = <1>;
0152 #size-cells = <1>;
0153 /*
0154 * map 64 bit address range down to 32 bits,
0155 * as the peripherals are all under 512MB.
0156 */
0157 ranges = <0 0 0 0x20000000>;
0158
0159 /*
0160 * This clock is actually configurable from the PRCM address
0161 * space. The external 24M oscillator can be turned off, and
0162 * the clock switched to an internal 16M RC oscillator. Under
0163 * normal operation there's no reason to do this, and the
0164 * default is to use the external good one, so just model this
0165 * as a fixed clock. Also it is not entirely clear if the
0166 * osc24M mux in the PRCM affects the entire clock tree, which
0167 * would also throw all the PLL clock rates off, or just the
0168 * downstream clocks in the PRCM.
0169 */
0170 osc24M: clk-24M {
0171 #clock-cells = <0>;
0172 compatible = "fixed-clock";
0173 clock-frequency = <24000000>;
0174 clock-output-names = "osc24M";
0175 };
0176
0177 /*
0178 * The 32k clock is from an external source, normally the
0179 * AC100 codec/RTC chip. This serves as a placeholder for
0180 * board dts files to specify the source.
0181 */
0182 osc32k: clk-32k {
0183 #clock-cells = <0>;
0184 compatible = "fixed-factor-clock";
0185 clock-div = <1>;
0186 clock-mult = <1>;
0187 clock-output-names = "osc32k";
0188 };
0189
0190 /*
0191 * The following two are dummy clocks, placeholders
0192 * used in the gmac_tx clock. The gmac driver will
0193 * choose one parent depending on the PHY interface
0194 * mode, using clk_set_rate auto-reparenting.
0195 *
0196 * The actual TX clock rate is not controlled by the
0197 * gmac_tx clock.
0198 */
0199 mii_phy_tx_clk: mii_phy_tx_clk {
0200 #clock-cells = <0>;
0201 compatible = "fixed-clock";
0202 clock-frequency = <25000000>;
0203 clock-output-names = "mii_phy_tx";
0204 };
0205
0206 gmac_int_tx_clk: gmac_int_tx_clk {
0207 #clock-cells = <0>;
0208 compatible = "fixed-clock";
0209 clock-frequency = <125000000>;
0210 clock-output-names = "gmac_int_tx";
0211 };
0212
0213 gmac_tx_clk: clk@800030 {
0214 #clock-cells = <0>;
0215 compatible = "allwinner,sun7i-a20-gmac-clk";
0216 reg = <0x00800030 0x4>;
0217 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
0218 clock-output-names = "gmac_tx";
0219 };
0220
0221 cpus_clk: clk@8001410 {
0222 compatible = "allwinner,sun9i-a80-cpus-clk";
0223 reg = <0x08001410 0x4>;
0224 #clock-cells = <0>;
0225 clocks = <&osc32k>, <&osc24M>,
0226 <&ccu CLK_PLL_PERIPH0>,
0227 <&ccu CLK_PLL_AUDIO>;
0228 clock-output-names = "cpus";
0229 };
0230
0231 ahbs: clk-ahbs {
0232 compatible = "fixed-factor-clock";
0233 #clock-cells = <0>;
0234 clock-div = <1>;
0235 clock-mult = <1>;
0236 clocks = <&cpus_clk>;
0237 clock-output-names = "ahbs";
0238 };
0239
0240 apbs: clk@800141c {
0241 compatible = "allwinner,sun8i-a23-apb0-clk";
0242 reg = <0x0800141c 0x4>;
0243 #clock-cells = <0>;
0244 clocks = <&ahbs>;
0245 clock-output-names = "apbs";
0246 };
0247
0248 apbs_gates: clk@8001428 {
0249 compatible = "allwinner,sun9i-a80-apbs-gates-clk";
0250 reg = <0x08001428 0x4>;
0251 #clock-cells = <1>;
0252 clocks = <&apbs>;
0253 clock-indices = <0>, <1>,
0254 <2>, <3>,
0255 <4>, <5>,
0256 <6>, <7>,
0257 <12>, <13>,
0258 <16>, <17>,
0259 <18>, <20>;
0260 clock-output-names = "apbs_pio", "apbs_ir",
0261 "apbs_timer", "apbs_rsb",
0262 "apbs_uart", "apbs_1wire",
0263 "apbs_i2c0", "apbs_i2c1",
0264 "apbs_ps2_0", "apbs_ps2_1",
0265 "apbs_dma", "apbs_i2s0",
0266 "apbs_i2s1", "apbs_twd";
0267 };
0268
0269 r_1wire_clk: clk@8001450 {
0270 reg = <0x08001450 0x4>;
0271 #clock-cells = <0>;
0272 compatible = "allwinner,sun4i-a10-mod0-clk";
0273 clocks = <&osc32k>, <&osc24M>;
0274 clock-output-names = "r_1wire";
0275 };
0276
0277 r_ir_clk: clk@8001454 {
0278 reg = <0x08001454 0x4>;
0279 #clock-cells = <0>;
0280 compatible = "allwinner,sun4i-a10-mod0-clk";
0281 clocks = <&osc32k>, <&osc24M>;
0282 clock-output-names = "r_ir";
0283 };
0284 };
0285
0286 de: display-engine {
0287 compatible = "allwinner,sun9i-a80-display-engine";
0288 allwinner,pipelines = <&fe0>, <&fe1>;
0289 status = "disabled";
0290 };
0291
0292 soc@20000 {
0293 compatible = "simple-bus";
0294 #address-cells = <1>;
0295 #size-cells = <1>;
0296 /*
0297 * map 64 bit address range down to 32 bits,
0298 * as the peripherals are all under 512MB.
0299 */
0300 ranges = <0 0 0 0x20000000>;
0301
0302 sram_b: sram@20000 {
0303 /* 256 KiB secure SRAM at 0x20000 */
0304 compatible = "mmio-sram";
0305 reg = <0x00020000 0x40000>;
0306
0307 #address-cells = <1>;
0308 #size-cells = <1>;
0309 ranges = <0 0x00020000 0x40000>;
0310
0311 smp-sram@1000 {
0312 /*
0313 * This is checked by BROM to determine if
0314 * cpu0 should jump to SMP entry vector
0315 */
0316 compatible = "allwinner,sun9i-a80-smp-sram";
0317 reg = <0x1000 0x8>;
0318 };
0319 };
0320
0321 gmac: ethernet@830000 {
0322 compatible = "allwinner,sun7i-a20-gmac";
0323 reg = <0x00830000 0x1054>;
0324 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0325 interrupt-names = "macirq";
0326 clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>;
0327 clock-names = "stmmaceth", "allwinner_gmac_tx";
0328 resets = <&ccu RST_BUS_GMAC>;
0329 reset-names = "stmmaceth";
0330 snps,pbl = <2>;
0331 snps,fixed-burst;
0332 snps,force_sf_dma_mode;
0333 status = "disabled";
0334
0335 mdio: mdio {
0336 compatible = "snps,dwmac-mdio";
0337 #address-cells = <1>;
0338 #size-cells = <0>;
0339 };
0340 };
0341
0342 ehci0: usb@a00000 {
0343 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
0344 reg = <0x00a00000 0x100>;
0345 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0346 clocks = <&usb_clocks CLK_BUS_HCI0>;
0347 resets = <&usb_clocks RST_USB0_HCI>;
0348 phys = <&usbphy1>;
0349 phy-names = "usb";
0350 status = "disabled";
0351 };
0352
0353 ohci0: usb@a00400 {
0354 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
0355 reg = <0x00a00400 0x100>;
0356 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0357 clocks = <&usb_clocks CLK_BUS_HCI0>,
0358 <&usb_clocks CLK_USB_OHCI0>;
0359 resets = <&usb_clocks RST_USB0_HCI>;
0360 phys = <&usbphy1>;
0361 phy-names = "usb";
0362 status = "disabled";
0363 };
0364
0365 usbphy1: phy@a00800 {
0366 compatible = "allwinner,sun9i-a80-usb-phy";
0367 reg = <0x00a00800 0x4>;
0368 clocks = <&usb_clocks CLK_USB0_PHY>;
0369 clock-names = "phy";
0370 resets = <&usb_clocks RST_USB0_PHY>;
0371 reset-names = "phy";
0372 status = "disabled";
0373 #phy-cells = <0>;
0374 };
0375
0376 ehci1: usb@a01000 {
0377 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
0378 reg = <0x00a01000 0x100>;
0379 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0380 clocks = <&usb_clocks CLK_BUS_HCI1>;
0381 resets = <&usb_clocks RST_USB1_HCI>;
0382 phys = <&usbphy2>;
0383 phy-names = "usb";
0384 status = "disabled";
0385 };
0386
0387 usbphy2: phy@a01800 {
0388 compatible = "allwinner,sun9i-a80-usb-phy";
0389 reg = <0x00a01800 0x4>;
0390 clocks = <&usb_clocks CLK_USB1_PHY>,
0391 <&usb_clocks CLK_USB_HSIC>,
0392 <&usb_clocks CLK_USB1_HSIC>;
0393 clock-names = "phy",
0394 "hsic_12M",
0395 "hsic_480M";
0396 resets = <&usb_clocks RST_USB1_PHY>,
0397 <&usb_clocks RST_USB1_HSIC>;
0398 reset-names = "phy",
0399 "hsic";
0400 status = "disabled";
0401 #phy-cells = <0>;
0402 /* usb1 is always used with HSIC */
0403 phy_type = "hsic";
0404 };
0405
0406 ehci2: usb@a02000 {
0407 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
0408 reg = <0x00a02000 0x100>;
0409 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0410 clocks = <&usb_clocks CLK_BUS_HCI2>;
0411 resets = <&usb_clocks RST_USB2_HCI>;
0412 phys = <&usbphy3>;
0413 phy-names = "usb";
0414 status = "disabled";
0415 };
0416
0417 ohci2: usb@a02400 {
0418 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
0419 reg = <0x00a02400 0x100>;
0420 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0421 clocks = <&usb_clocks CLK_BUS_HCI2>,
0422 <&usb_clocks CLK_USB_OHCI2>;
0423 resets = <&usb_clocks RST_USB2_HCI>;
0424 phys = <&usbphy3>;
0425 phy-names = "usb";
0426 status = "disabled";
0427 };
0428
0429 usbphy3: phy@a02800 {
0430 compatible = "allwinner,sun9i-a80-usb-phy";
0431 reg = <0x00a02800 0x4>;
0432 clocks = <&usb_clocks CLK_USB2_PHY>,
0433 <&usb_clocks CLK_USB_HSIC>,
0434 <&usb_clocks CLK_USB2_HSIC>;
0435 clock-names = "phy",
0436 "hsic_12M",
0437 "hsic_480M";
0438 resets = <&usb_clocks RST_USB2_PHY>,
0439 <&usb_clocks RST_USB2_HSIC>;
0440 reset-names = "phy",
0441 "hsic";
0442 status = "disabled";
0443 #phy-cells = <0>;
0444 };
0445
0446 usb_clocks: clock@a08000 {
0447 compatible = "allwinner,sun9i-a80-usb-clks";
0448 reg = <0x00a08000 0x8>;
0449 clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
0450 clock-names = "bus", "hosc";
0451 #clock-cells = <1>;
0452 #reset-cells = <1>;
0453 };
0454
0455 cpucfg@1700000 {
0456 compatible = "allwinner,sun9i-a80-cpucfg";
0457 reg = <0x01700000 0x100>;
0458 };
0459
0460 crypto: crypto@1c02000 {
0461 compatible = "allwinner,sun9i-a80-crypto";
0462 reg = <0x01c02000 0x1000>;
0463 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
0464 resets = <&ccu RST_BUS_SS>;
0465 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
0466 clock-names = "bus", "mod";
0467 };
0468
0469 mmc0: mmc@1c0f000 {
0470 compatible = "allwinner,sun9i-a80-mmc";
0471 reg = <0x01c0f000 0x1000>;
0472 clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
0473 <&ccu CLK_MMC0_OUTPUT>,
0474 <&ccu CLK_MMC0_SAMPLE>;
0475 clock-names = "ahb", "mmc", "output", "sample";
0476 resets = <&mmc_config_clk 0>;
0477 reset-names = "ahb";
0478 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0479 status = "disabled";
0480 #address-cells = <1>;
0481 #size-cells = <0>;
0482 };
0483
0484 mmc1: mmc@1c10000 {
0485 compatible = "allwinner,sun9i-a80-mmc";
0486 reg = <0x01c10000 0x1000>;
0487 clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>,
0488 <&ccu CLK_MMC1_OUTPUT>,
0489 <&ccu CLK_MMC1_SAMPLE>;
0490 clock-names = "ahb", "mmc", "output", "sample";
0491 resets = <&mmc_config_clk 1>;
0492 reset-names = "ahb";
0493 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0494 status = "disabled";
0495 #address-cells = <1>;
0496 #size-cells = <0>;
0497 };
0498
0499 mmc2: mmc@1c11000 {
0500 compatible = "allwinner,sun9i-a80-mmc";
0501 reg = <0x01c11000 0x1000>;
0502 clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>,
0503 <&ccu CLK_MMC2_OUTPUT>,
0504 <&ccu CLK_MMC2_SAMPLE>;
0505 clock-names = "ahb", "mmc", "output", "sample";
0506 resets = <&mmc_config_clk 2>;
0507 reset-names = "ahb";
0508 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0509 status = "disabled";
0510 #address-cells = <1>;
0511 #size-cells = <0>;
0512 };
0513
0514 mmc3: mmc@1c12000 {
0515 compatible = "allwinner,sun9i-a80-mmc";
0516 reg = <0x01c12000 0x1000>;
0517 clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>,
0518 <&ccu CLK_MMC3_OUTPUT>,
0519 <&ccu CLK_MMC3_SAMPLE>;
0520 clock-names = "ahb", "mmc", "output", "sample";
0521 resets = <&mmc_config_clk 3>;
0522 reset-names = "ahb";
0523 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0524 status = "disabled";
0525 #address-cells = <1>;
0526 #size-cells = <0>;
0527 };
0528
0529 mmc_config_clk: clk@1c13000 {
0530 compatible = "allwinner,sun9i-a80-mmc-config-clk";
0531 reg = <0x01c13000 0x10>;
0532 clocks = <&ccu CLK_BUS_MMC>;
0533 resets = <&ccu RST_BUS_MMC>;
0534 #clock-cells = <1>;
0535 #reset-cells = <1>;
0536 clock-output-names = "mmc0_config", "mmc1_config",
0537 "mmc2_config", "mmc3_config";
0538 };
0539
0540 gic: interrupt-controller@1c41000 {
0541 compatible = "arm,gic-400";
0542 reg = <0x01c41000 0x1000>,
0543 <0x01c42000 0x2000>,
0544 <0x01c44000 0x2000>,
0545 <0x01c46000 0x2000>;
0546 interrupt-controller;
0547 #interrupt-cells = <3>;
0548 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0549 };
0550
0551 cci: cci@1c90000 {
0552 compatible = "arm,cci-400";
0553 #address-cells = <1>;
0554 #size-cells = <1>;
0555 reg = <0x01c90000 0x1000>;
0556 ranges = <0x0 0x01c90000 0x10000>;
0557
0558 cci_control0: slave-if@4000 {
0559 compatible = "arm,cci-400-ctrl-if";
0560 interface-type = "ace";
0561 reg = <0x4000 0x1000>;
0562 };
0563
0564 cci_control1: slave-if@5000 {
0565 compatible = "arm,cci-400-ctrl-if";
0566 interface-type = "ace";
0567 reg = <0x5000 0x1000>;
0568 };
0569
0570 pmu@9000 {
0571 compatible = "arm,cci-400-pmu,r1";
0572 reg = <0x9000 0x5000>;
0573 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
0574 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
0575 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
0576 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
0577 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
0578 };
0579 };
0580
0581 de_clocks: clock@3000000 {
0582 compatible = "allwinner,sun9i-a80-de-clks";
0583 reg = <0x03000000 0x30>;
0584 clocks = <&ccu CLK_DE>,
0585 <&ccu CLK_SDRAM>,
0586 <&ccu CLK_BUS_DE>;
0587 clock-names = "mod",
0588 "dram",
0589 "bus";
0590 resets = <&ccu RST_BUS_DE>;
0591 #clock-cells = <1>;
0592 #reset-cells = <1>;
0593 };
0594
0595 fe0: display-frontend@3100000 {
0596 compatible = "allwinner,sun9i-a80-display-frontend";
0597 reg = <0x03100000 0x40000>;
0598 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
0599 clocks = <&de_clocks CLK_BUS_FE0>, <&de_clocks CLK_FE0>,
0600 <&de_clocks CLK_DRAM_FE0>;
0601 clock-names = "ahb", "mod",
0602 "ram";
0603 resets = <&de_clocks RST_FE0>;
0604
0605 ports {
0606 #address-cells = <1>;
0607 #size-cells = <0>;
0608
0609 fe0_out: port@1 {
0610 reg = <1>;
0611
0612 fe0_out_deu0: endpoint {
0613 remote-endpoint = <&deu0_in_fe0>;
0614 };
0615 };
0616 };
0617 };
0618
0619 fe1: display-frontend@3140000 {
0620 compatible = "allwinner,sun9i-a80-display-frontend";
0621 reg = <0x03140000 0x40000>;
0622 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0623 clocks = <&de_clocks CLK_BUS_FE1>, <&de_clocks CLK_FE1>,
0624 <&de_clocks CLK_DRAM_FE1>;
0625 clock-names = "ahb", "mod",
0626 "ram";
0627 resets = <&de_clocks RST_FE0>;
0628
0629 ports {
0630 #address-cells = <1>;
0631 #size-cells = <0>;
0632
0633 fe1_out: port@1 {
0634 reg = <1>;
0635
0636 fe1_out_deu1: endpoint {
0637 remote-endpoint = <&deu1_in_fe1>;
0638 };
0639 };
0640 };
0641 };
0642
0643 be0: display-backend@3200000 {
0644 compatible = "allwinner,sun9i-a80-display-backend";
0645 reg = <0x03200000 0x40000>;
0646 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0647 clocks = <&de_clocks CLK_BUS_BE0>, <&de_clocks CLK_BE0>,
0648 <&de_clocks CLK_DRAM_BE0>;
0649 clock-names = "ahb", "mod",
0650 "ram";
0651 resets = <&de_clocks RST_BE0>;
0652
0653 ports {
0654 #address-cells = <1>;
0655 #size-cells = <0>;
0656
0657 be0_in: port@0 {
0658 #address-cells = <1>;
0659 #size-cells = <0>;
0660 reg = <0>;
0661
0662 be0_in_deu0: endpoint@0 {
0663 reg = <0>;
0664 remote-endpoint = <&deu0_out_be0>;
0665 };
0666
0667 be0_in_deu1: endpoint@1 {
0668 reg = <1>;
0669 remote-endpoint = <&deu1_out_be0>;
0670 };
0671 };
0672
0673 be0_out: port@1 {
0674 reg = <1>;
0675
0676 be0_out_drc0: endpoint {
0677 remote-endpoint = <&drc0_in_be0>;
0678 };
0679 };
0680 };
0681 };
0682
0683 be1: display-backend@3240000 {
0684 compatible = "allwinner,sun9i-a80-display-backend";
0685 reg = <0x03240000 0x40000>;
0686 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0687 clocks = <&de_clocks CLK_BUS_BE1>, <&de_clocks CLK_BE1>,
0688 <&de_clocks CLK_DRAM_BE1>;
0689 clock-names = "ahb", "mod",
0690 "ram";
0691 resets = <&de_clocks RST_BE1>;
0692
0693 ports {
0694 #address-cells = <1>;
0695 #size-cells = <0>;
0696
0697 be1_in: port@0 {
0698 #address-cells = <1>;
0699 #size-cells = <0>;
0700 reg = <0>;
0701
0702 be1_in_deu0: endpoint@0 {
0703 reg = <0>;
0704 remote-endpoint = <&deu0_out_be1>;
0705 };
0706
0707 be1_in_deu1: endpoint@1 {
0708 reg = <1>;
0709 remote-endpoint = <&deu1_out_be1>;
0710 };
0711 };
0712
0713 be1_out: port@1 {
0714 reg = <1>;
0715
0716 be1_out_drc1: endpoint {
0717 remote-endpoint = <&drc1_in_be1>;
0718 };
0719 };
0720 };
0721 };
0722
0723 deu0: deu@3300000 {
0724 compatible = "allwinner,sun9i-a80-deu";
0725 reg = <0x03300000 0x40000>;
0726 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0727 clocks = <&de_clocks CLK_BUS_DEU0>,
0728 <&de_clocks CLK_IEP_DEU0>,
0729 <&de_clocks CLK_DRAM_DEU0>;
0730 clock-names = "ahb",
0731 "mod",
0732 "ram";
0733 resets = <&de_clocks RST_DEU0>;
0734
0735 ports {
0736 #address-cells = <1>;
0737 #size-cells = <0>;
0738
0739 deu0_in: port@0 {
0740 reg = <0>;
0741
0742 deu0_in_fe0: endpoint {
0743 remote-endpoint = <&fe0_out_deu0>;
0744 };
0745 };
0746
0747 deu0_out: port@1 {
0748 #address-cells = <1>;
0749 #size-cells = <0>;
0750 reg = <1>;
0751
0752 deu0_out_be0: endpoint@0 {
0753 reg = <0>;
0754 remote-endpoint = <&be0_in_deu0>;
0755 };
0756
0757 deu0_out_be1: endpoint@1 {
0758 reg = <1>;
0759 remote-endpoint = <&be1_in_deu0>;
0760 };
0761 };
0762 };
0763 };
0764
0765 deu1: deu@3340000 {
0766 compatible = "allwinner,sun9i-a80-deu";
0767 reg = <0x03340000 0x40000>;
0768 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0769 clocks = <&de_clocks CLK_BUS_DEU1>,
0770 <&de_clocks CLK_IEP_DEU1>,
0771 <&de_clocks CLK_DRAM_DEU1>;
0772 clock-names = "ahb",
0773 "mod",
0774 "ram";
0775 resets = <&de_clocks RST_DEU1>;
0776
0777 ports {
0778 #address-cells = <1>;
0779 #size-cells = <0>;
0780
0781 deu1_in: port@0 {
0782 reg = <0>;
0783
0784 deu1_in_fe1: endpoint {
0785 remote-endpoint = <&fe1_out_deu1>;
0786 };
0787 };
0788
0789 deu1_out: port@1 {
0790 #address-cells = <1>;
0791 #size-cells = <0>;
0792 reg = <1>;
0793
0794 deu1_out_be0: endpoint@0 {
0795 reg = <0>;
0796 remote-endpoint = <&be0_in_deu1>;
0797 };
0798
0799 deu1_out_be1: endpoint@1 {
0800 reg = <1>;
0801 remote-endpoint = <&be1_in_deu1>;
0802 };
0803 };
0804 };
0805 };
0806
0807 drc0: drc@3400000 {
0808 compatible = "allwinner,sun9i-a80-drc";
0809 reg = <0x03400000 0x40000>;
0810 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0811 clocks = <&de_clocks CLK_BUS_DRC0>,
0812 <&de_clocks CLK_IEP_DRC0>,
0813 <&de_clocks CLK_DRAM_DRC0>;
0814 clock-names = "ahb",
0815 "mod",
0816 "ram";
0817 resets = <&de_clocks RST_DRC0>;
0818
0819 ports {
0820 #address-cells = <1>;
0821 #size-cells = <0>;
0822
0823 drc0_in: port@0 {
0824 reg = <0>;
0825
0826 drc0_in_be0: endpoint {
0827 remote-endpoint = <&be0_out_drc0>;
0828 };
0829 };
0830
0831 drc0_out: port@1 {
0832 reg = <1>;
0833
0834 drc0_out_tcon0: endpoint {
0835 remote-endpoint = <&tcon0_in_drc0>;
0836 };
0837 };
0838 };
0839 };
0840
0841 drc1: drc@3440000 {
0842 compatible = "allwinner,sun9i-a80-drc";
0843 reg = <0x03440000 0x40000>;
0844 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0845 clocks = <&de_clocks CLK_BUS_DRC1>,
0846 <&de_clocks CLK_IEP_DRC1>,
0847 <&de_clocks CLK_DRAM_DRC1>;
0848 clock-names = "ahb",
0849 "mod",
0850 "ram";
0851 resets = <&de_clocks RST_DRC1>;
0852
0853 ports {
0854 #address-cells = <1>;
0855 #size-cells = <0>;
0856
0857 drc1_in: port@0 {
0858 reg = <0>;
0859
0860 drc1_in_be1: endpoint {
0861 remote-endpoint = <&be1_out_drc1>;
0862 };
0863 };
0864
0865 drc1_out: port@1 {
0866 reg = <1>;
0867
0868 drc1_out_tcon1: endpoint {
0869 remote-endpoint = <&tcon1_in_drc1>;
0870 };
0871 };
0872 };
0873 };
0874
0875 tcon0: lcd-controller@3c00000 {
0876 compatible = "allwinner,sun9i-a80-tcon-lcd";
0877 reg = <0x03c00000 0x10000>;
0878 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0879 clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
0880 clock-names = "ahb", "tcon-ch0";
0881 resets = <&ccu RST_BUS_LCD0>,
0882 <&ccu RST_BUS_EDP>,
0883 <&ccu RST_BUS_LVDS>;
0884 reset-names = "lcd",
0885 "edp",
0886 "lvds";
0887 clock-output-names = "tcon0-pixel-clock";
0888 #clock-cells = <0>;
0889
0890 ports {
0891 #address-cells = <1>;
0892 #size-cells = <0>;
0893
0894 tcon0_in: port@0 {
0895 reg = <0>;
0896
0897 tcon0_in_drc0: endpoint {
0898 remote-endpoint = <&drc0_out_tcon0>;
0899 };
0900 };
0901
0902 tcon0_out: port@1 {
0903 reg = <1>;
0904 };
0905 };
0906 };
0907
0908 tcon1: lcd-controller@3c10000 {
0909 compatible = "allwinner,sun9i-a80-tcon-tv";
0910 reg = <0x03c10000 0x10000>;
0911 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0912 clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>;
0913 clock-names = "ahb", "tcon-ch1";
0914 resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>;
0915 reset-names = "lcd", "edp";
0916
0917 ports {
0918 #address-cells = <1>;
0919 #size-cells = <0>;
0920
0921 tcon1_in: port@0 {
0922 reg = <0>;
0923
0924 tcon1_in_drc1: endpoint {
0925 remote-endpoint = <&drc1_out_tcon1>;
0926 };
0927 };
0928
0929 tcon1_out: port@1 {
0930 reg = <1>;
0931 };
0932 };
0933 };
0934
0935 ccu: clock@6000000 {
0936 compatible = "allwinner,sun9i-a80-ccu";
0937 reg = <0x06000000 0x800>;
0938 clocks = <&osc24M>, <&osc32k>;
0939 clock-names = "hosc", "losc";
0940 #clock-cells = <1>;
0941 #reset-cells = <1>;
0942 };
0943
0944 timer@6000c00 {
0945 compatible = "allwinner,sun4i-a10-timer";
0946 reg = <0x06000c00 0xa0>;
0947 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0948 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0949 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
0950 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
0951 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
0952 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0953
0954 clocks = <&osc24M>;
0955 };
0956
0957 wdt: watchdog@6000ca0 {
0958 compatible = "allwinner,sun6i-a31-wdt";
0959 reg = <0x06000ca0 0x20>;
0960 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0961 clocks = <&osc24M>;
0962 };
0963
0964 pio: pinctrl@6000800 {
0965 compatible = "allwinner,sun9i-a80-pinctrl";
0966 reg = <0x06000800 0x400>;
0967 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0968 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
0969 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
0970 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
0971 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
0972 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
0973 clock-names = "apb", "hosc", "losc";
0974 gpio-controller;
0975 interrupt-controller;
0976 #interrupt-cells = <3>;
0977 #gpio-cells = <3>;
0978
0979 gmac_rgmii_pins: gmac-rgmii-pins {
0980 pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5",
0981 "PA7", "PA8", "PA9", "PA10", "PA12",
0982 "PA13", "PA15", "PA16", "PA17";
0983 function = "gmac";
0984 /*
0985 * data lines in RGMII mode use DDR mode
0986 * and need a higher signal drive strength
0987 */
0988 drive-strength = <40>;
0989 };
0990
0991 i2c3_pins: i2c3-pins {
0992 pins = "PG10", "PG11";
0993 function = "i2c3";
0994 };
0995
0996 lcd0_rgb888_pins: lcd0-rgb888-pins {
0997 pins = "PD0", "PD1", "PD2", "PD3",
0998 "PD4", "PD5", "PD6", "PD7",
0999 "PD8", "PD9", "PD10", "PD11",
1000 "PD12", "PD13", "PD14", "PD15",
1001 "PD16", "PD17", "PD18", "PD19",
1002 "PD20", "PD21", "PD22", "PD23",
1003 "PD24", "PD25", "PD26", "PD27";
1004 function = "lcd0";
1005 };
1006
1007 mmc0_pins: mmc0-pins {
1008 pins = "PF0", "PF1" ,"PF2", "PF3",
1009 "PF4", "PF5";
1010 function = "mmc0";
1011 drive-strength = <30>;
1012 bias-pull-up;
1013 };
1014
1015 mmc1_pins: mmc1-pins {
1016 pins = "PG0", "PG1" ,"PG2", "PG3",
1017 "PG4", "PG5";
1018 function = "mmc1";
1019 drive-strength = <30>;
1020 bias-pull-up;
1021 };
1022
1023 mmc2_8bit_pins: mmc2-8bit-pins {
1024 pins = "PC6", "PC7", "PC8", "PC9",
1025 "PC10", "PC11", "PC12",
1026 "PC13", "PC14", "PC15",
1027 "PC16";
1028 function = "mmc2";
1029 drive-strength = <30>;
1030 bias-pull-up;
1031 };
1032
1033 uart0_ph_pins: uart0-ph-pins {
1034 pins = "PH12", "PH13";
1035 function = "uart0";
1036 };
1037
1038 uart4_pins: uart4-pins {
1039 pins = "PG12", "PG13", "PG14", "PG15";
1040 function = "uart4";
1041 };
1042 };
1043
1044 uart0: serial@7000000 {
1045 compatible = "snps,dw-apb-uart";
1046 reg = <0x07000000 0x400>;
1047 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1048 reg-shift = <2>;
1049 reg-io-width = <4>;
1050 clocks = <&ccu CLK_BUS_UART0>;
1051 resets = <&ccu RST_BUS_UART0>;
1052 status = "disabled";
1053 };
1054
1055 uart1: serial@7000400 {
1056 compatible = "snps,dw-apb-uart";
1057 reg = <0x07000400 0x400>;
1058 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1059 reg-shift = <2>;
1060 reg-io-width = <4>;
1061 clocks = <&ccu CLK_BUS_UART1>;
1062 resets = <&ccu RST_BUS_UART1>;
1063 status = "disabled";
1064 };
1065
1066 uart2: serial@7000800 {
1067 compatible = "snps,dw-apb-uart";
1068 reg = <0x07000800 0x400>;
1069 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1070 reg-shift = <2>;
1071 reg-io-width = <4>;
1072 clocks = <&ccu CLK_BUS_UART2>;
1073 resets = <&ccu RST_BUS_UART2>;
1074 status = "disabled";
1075 };
1076
1077 uart3: serial@7000c00 {
1078 compatible = "snps,dw-apb-uart";
1079 reg = <0x07000c00 0x400>;
1080 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1081 reg-shift = <2>;
1082 reg-io-width = <4>;
1083 clocks = <&ccu CLK_BUS_UART3>;
1084 resets = <&ccu RST_BUS_UART3>;
1085 status = "disabled";
1086 };
1087
1088 uart4: serial@7001000 {
1089 compatible = "snps,dw-apb-uart";
1090 reg = <0x07001000 0x400>;
1091 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1092 reg-shift = <2>;
1093 reg-io-width = <4>;
1094 clocks = <&ccu CLK_BUS_UART4>;
1095 resets = <&ccu RST_BUS_UART4>;
1096 status = "disabled";
1097 };
1098
1099 uart5: serial@7001400 {
1100 compatible = "snps,dw-apb-uart";
1101 reg = <0x07001400 0x400>;
1102 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1103 reg-shift = <2>;
1104 reg-io-width = <4>;
1105 clocks = <&ccu CLK_BUS_UART5>;
1106 resets = <&ccu RST_BUS_UART5>;
1107 status = "disabled";
1108 };
1109
1110 i2c0: i2c@7002800 {
1111 compatible = "allwinner,sun6i-a31-i2c";
1112 reg = <0x07002800 0x400>;
1113 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1114 clocks = <&ccu CLK_BUS_I2C0>;
1115 resets = <&ccu RST_BUS_I2C0>;
1116 status = "disabled";
1117 #address-cells = <1>;
1118 #size-cells = <0>;
1119 };
1120
1121 i2c1: i2c@7002c00 {
1122 compatible = "allwinner,sun6i-a31-i2c";
1123 reg = <0x07002c00 0x400>;
1124 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1125 clocks = <&ccu CLK_BUS_I2C1>;
1126 resets = <&ccu RST_BUS_I2C1>;
1127 status = "disabled";
1128 #address-cells = <1>;
1129 #size-cells = <0>;
1130 };
1131
1132 i2c2: i2c@7003000 {
1133 compatible = "allwinner,sun6i-a31-i2c";
1134 reg = <0x07003000 0x400>;
1135 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1136 clocks = <&ccu CLK_BUS_I2C2>;
1137 resets = <&ccu RST_BUS_I2C2>;
1138 status = "disabled";
1139 #address-cells = <1>;
1140 #size-cells = <0>;
1141 };
1142
1143 i2c3: i2c@7003400 {
1144 compatible = "allwinner,sun6i-a31-i2c";
1145 reg = <0x07003400 0x400>;
1146 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1147 clocks = <&ccu CLK_BUS_I2C3>;
1148 resets = <&ccu RST_BUS_I2C3>;
1149 status = "disabled";
1150 #address-cells = <1>;
1151 #size-cells = <0>;
1152 };
1153
1154 i2c4: i2c@7003800 {
1155 compatible = "allwinner,sun6i-a31-i2c";
1156 reg = <0x07003800 0x400>;
1157 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1158 clocks = <&ccu CLK_BUS_I2C4>;
1159 resets = <&ccu RST_BUS_I2C4>;
1160 status = "disabled";
1161 #address-cells = <1>;
1162 #size-cells = <0>;
1163 };
1164
1165 r_wdt: watchdog@8001000 {
1166 compatible = "allwinner,sun6i-a31-wdt";
1167 reg = <0x08001000 0x20>;
1168 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1169 clocks = <&osc24M>;
1170 };
1171
1172 prcm@8001400 {
1173 compatible = "allwinner,sun9i-a80-prcm";
1174 reg = <0x08001400 0x200>;
1175 };
1176
1177 apbs_rst: reset@80014b0 {
1178 reg = <0x080014b0 0x4>;
1179 compatible = "allwinner,sun6i-a31-clock-reset";
1180 #reset-cells = <1>;
1181 };
1182
1183 nmi_intc: interrupt-controller@80015a0 {
1184 compatible = "allwinner,sun9i-a80-nmi";
1185 interrupt-controller;
1186 #interrupt-cells = <2>;
1187 reg = <0x080015a0 0xc>;
1188 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1189 };
1190
1191 r_ir: ir@8002000 {
1192 compatible = "allwinner,sun6i-a31-ir";
1193 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1194 pinctrl-names = "default";
1195 pinctrl-0 = <&r_ir_pins>;
1196 clocks = <&apbs_gates 1>, <&r_ir_clk>;
1197 clock-names = "apb", "ir";
1198 resets = <&apbs_rst 1>;
1199 reg = <0x08002000 0x40>;
1200 status = "disabled";
1201 };
1202
1203 r_uart: serial@8002800 {
1204 compatible = "snps,dw-apb-uart";
1205 reg = <0x08002800 0x400>;
1206 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1207 reg-shift = <2>;
1208 reg-io-width = <4>;
1209 clocks = <&apbs_gates 4>;
1210 resets = <&apbs_rst 4>;
1211 status = "disabled";
1212 };
1213
1214 r_pio: pinctrl@8002c00 {
1215 compatible = "allwinner,sun9i-a80-r-pinctrl";
1216 reg = <0x08002c00 0x400>;
1217 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1218 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1219 clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
1220 clock-names = "apb", "hosc", "losc";
1221 gpio-controller;
1222 interrupt-controller;
1223 #interrupt-cells = <3>;
1224 #gpio-cells = <3>;
1225
1226 r_ir_pins: r-ir-pins {
1227 pins = "PL6";
1228 function = "s_cir_rx";
1229 };
1230
1231 r_rsb_pins: r-rsb-pins {
1232 pins = "PN0", "PN1";
1233 function = "s_rsb";
1234 drive-strength = <20>;
1235 bias-pull-up;
1236 };
1237 };
1238
1239 r_rsb: rsb@8003400 {
1240 compatible = "allwinner,sun8i-a23-rsb";
1241 reg = <0x08003400 0x400>;
1242 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1243 clocks = <&apbs_gates 3>;
1244 clock-frequency = <3000000>;
1245 resets = <&apbs_rst 3>;
1246 pinctrl-names = "default";
1247 pinctrl-0 = <&r_rsb_pins>;
1248 status = "disabled";
1249 #address-cells = <1>;
1250 #size-cells = <0>;
1251 };
1252 };
1253 };
