0001 /*
0002 * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
0003 * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
0004 *
0005 * This file is dual-licensed: you can use it either under the terms
0006 * of the GPL or the X11 license, at your option. Note that this dual
0007 * licensing only applies to this file, and not this project as a
0008 * whole.
0009 *
0010 * a) This file is free software; you can redistribute it and/or
0011 * modify it under the terms of the GNU General Public License as
0012 * published by the Free Software Foundation; either version 2 of the
0013 * License, or (at your option) any later version.
0014 *
0015 * This file is distributed in the hope that it will be useful,
0016 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0017 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0018 * GNU General Public License for more details.
0019 *
0020 * Or, alternatively,
0021 *
0022 * b) Permission is hereby granted, free of charge, to any person
0023 * obtaining a copy of this software and associated documentation
0024 * files (the "Software"), to deal in the Software without
0025 * restriction, including without limitation the rights to use,
0026 * copy, modify, merge, publish, distribute, sublicense, and/or
0027 * sell copies of the Software, and to permit persons to whom the
0028 * Software is furnished to do so, subject to the following
0029 * conditions:
0030 *
0031 * The above copyright notice and this permission notice shall be
0032 * included in all copies or substantial portions of the Software.
0033 *
0034 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0035 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0036 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0037 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0038 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0039 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0040 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0041 * OTHER DEALINGS IN THE SOFTWARE.
0042 */
0043
0044 #include <dt-bindings/interrupt-controller/arm-gic.h>
0045 #include <dt-bindings/clock/sun6i-rtc.h>
0046 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
0047 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
0048 #include <dt-bindings/clock/sun8i-de2.h>
0049
0050 / {
0051 #address-cells = <1>;
0052 #size-cells = <1>;
0053 interrupt-parent = <&gic>;
0054
0055 chosen {
0056 #address-cells = <1>;
0057 #size-cells = <1>;
0058 ranges;
0059
0060 framebuffer-lcd {
0061 compatible = "allwinner,simple-framebuffer",
0062 "simple-framebuffer";
0063 allwinner,pipeline = "mixer0-lcd0";
0064 clocks = <&display_clocks CLK_MIXER0>,
0065 <&ccu CLK_TCON0>;
0066 status = "disabled";
0067 };
0068 };
0069
0070 cpus {
0071 #address-cells = <1>;
0072 #size-cells = <0>;
0073
0074 cpu@0 {
0075 compatible = "arm,cortex-a7";
0076 device_type = "cpu";
0077 reg = <0>;
0078 clocks = <&ccu CLK_CPU>;
0079 };
0080 };
0081
0082 de: display-engine {
0083 compatible = "allwinner,sun8i-v3s-display-engine";
0084 allwinner,pipelines = <&mixer0>;
0085 status = "disabled";
0086 };
0087
0088 timer {
0089 compatible = "arm,armv7-timer";
0090 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0091 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0092 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0093 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0094 };
0095
0096 clocks {
0097 #address-cells = <1>;
0098 #size-cells = <1>;
0099 ranges;
0100
0101 osc24M: osc24M_clk {
0102 #clock-cells = <0>;
0103 compatible = "fixed-clock";
0104 clock-frequency = <24000000>;
0105 clock-accuracy = <50000>;
0106 clock-output-names = "osc24M";
0107 };
0108
0109 osc32k: osc32k_clk {
0110 #clock-cells = <0>;
0111 compatible = "fixed-clock";
0112 clock-frequency = <32768>;
0113 clock-accuracy = <50000>;
0114 clock-output-names = "ext-osc32k";
0115 };
0116 };
0117
0118 soc {
0119 compatible = "simple-bus";
0120 #address-cells = <1>;
0121 #size-cells = <1>;
0122 ranges;
0123
0124 display_clocks: clock@1000000 {
0125 compatible = "allwinner,sun8i-v3s-de2-clk";
0126 reg = <0x01000000 0x10000>;
0127 clocks = <&ccu CLK_BUS_DE>,
0128 <&ccu CLK_DE>;
0129 clock-names = "bus",
0130 "mod";
0131 resets = <&ccu RST_BUS_DE>;
0132 #clock-cells = <1>;
0133 #reset-cells = <1>;
0134 };
0135
0136 mixer0: mixer@1100000 {
0137 compatible = "allwinner,sun8i-v3s-de2-mixer";
0138 reg = <0x01100000 0x100000>;
0139 clocks = <&display_clocks 0>,
0140 <&display_clocks 6>;
0141 clock-names = "bus",
0142 "mod";
0143 resets = <&display_clocks 0>;
0144
0145 ports {
0146 #address-cells = <1>;
0147 #size-cells = <0>;
0148
0149 mixer0_out: port@1 {
0150 reg = <1>;
0151
0152 mixer0_out_tcon0: endpoint {
0153 remote-endpoint = <&tcon0_in_mixer0>;
0154 };
0155 };
0156 };
0157 };
0158
0159 syscon: system-control@1c00000 {
0160 compatible = "allwinner,sun8i-v3s-system-control",
0161 "allwinner,sun8i-h3-system-control";
0162 reg = <0x01c00000 0xd0>;
0163 #address-cells = <1>;
0164 #size-cells = <1>;
0165 ranges;
0166 };
0167
0168 nmi_intc: interrupt-controller@1c000d0 {
0169 compatible = "allwinner,sun8i-v3s-nmi",
0170 "allwinner,sun9i-a80-nmi";
0171 interrupt-controller;
0172 #interrupt-cells = <2>;
0173 reg = <0x01c000d0 0x0c>;
0174 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0175 };
0176
0177 dma: dma-controller@1c02000 {
0178 compatible = "allwinner,sun8i-v3s-dma";
0179 reg = <0x01c02000 0x1000>;
0180 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0181 clocks = <&ccu CLK_BUS_DMA>;
0182 resets = <&ccu RST_BUS_DMA>;
0183 #dma-cells = <1>;
0184 };
0185
0186 tcon0: lcd-controller@1c0c000 {
0187 compatible = "allwinner,sun8i-v3s-tcon";
0188 reg = <0x01c0c000 0x1000>;
0189 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0190 clocks = <&ccu CLK_BUS_TCON0>,
0191 <&ccu CLK_TCON0>;
0192 clock-names = "ahb",
0193 "tcon-ch0";
0194 clock-output-names = "tcon-pixel-clock";
0195 #clock-cells = <0>;
0196 resets = <&ccu RST_BUS_TCON0>;
0197 reset-names = "lcd";
0198 status = "disabled";
0199
0200 ports {
0201 #address-cells = <1>;
0202 #size-cells = <0>;
0203
0204 tcon0_in: port@0 {
0205 reg = <0>;
0206
0207 tcon0_in_mixer0: endpoint {
0208 remote-endpoint = <&mixer0_out_tcon0>;
0209 };
0210 };
0211
0212 tcon0_out: port@1 {
0213 #address-cells = <1>;
0214 #size-cells = <0>;
0215 reg = <1>;
0216 };
0217 };
0218 };
0219
0220
0221 mmc0: mmc@1c0f000 {
0222 compatible = "allwinner,sun7i-a20-mmc";
0223 reg = <0x01c0f000 0x1000>;
0224 clocks = <&ccu CLK_BUS_MMC0>,
0225 <&ccu CLK_MMC0>,
0226 <&ccu CLK_MMC0_OUTPUT>,
0227 <&ccu CLK_MMC0_SAMPLE>;
0228 clock-names = "ahb",
0229 "mmc",
0230 "output",
0231 "sample";
0232 resets = <&ccu RST_BUS_MMC0>;
0233 reset-names = "ahb";
0234 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0235 pinctrl-names = "default";
0236 pinctrl-0 = <&mmc0_pins>;
0237 status = "disabled";
0238 #address-cells = <1>;
0239 #size-cells = <0>;
0240 };
0241
0242 mmc1: mmc@1c10000 {
0243 compatible = "allwinner,sun7i-a20-mmc";
0244 reg = <0x01c10000 0x1000>;
0245 clocks = <&ccu CLK_BUS_MMC1>,
0246 <&ccu CLK_MMC1>,
0247 <&ccu CLK_MMC1_OUTPUT>,
0248 <&ccu CLK_MMC1_SAMPLE>;
0249 clock-names = "ahb",
0250 "mmc",
0251 "output",
0252 "sample";
0253 resets = <&ccu RST_BUS_MMC1>;
0254 reset-names = "ahb";
0255 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0256 pinctrl-names = "default";
0257 pinctrl-0 = <&mmc1_pins>;
0258 status = "disabled";
0259 #address-cells = <1>;
0260 #size-cells = <0>;
0261 };
0262
0263 mmc2: mmc@1c11000 {
0264 compatible = "allwinner,sun7i-a20-mmc";
0265 reg = <0x01c11000 0x1000>;
0266 clocks = <&ccu CLK_BUS_MMC2>,
0267 <&ccu CLK_MMC2>,
0268 <&ccu CLK_MMC2_OUTPUT>,
0269 <&ccu CLK_MMC2_SAMPLE>;
0270 clock-names = "ahb",
0271 "mmc",
0272 "output",
0273 "sample";
0274 resets = <&ccu RST_BUS_MMC2>;
0275 reset-names = "ahb";
0276 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0277 status = "disabled";
0278 #address-cells = <1>;
0279 #size-cells = <0>;
0280 };
0281
0282 crypto@1c15000 {
0283 compatible = "allwinner,sun8i-v3s-crypto",
0284 "allwinner,sun8i-a33-crypto";
0285 reg = <0x01c15000 0x1000>;
0286 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
0287 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
0288 clock-names = "ahb", "mod";
0289 dmas = <&dma 16>, <&dma 16>;
0290 dma-names = "rx", "tx";
0291 resets = <&ccu RST_BUS_CE>;
0292 reset-names = "ahb";
0293 };
0294
0295 usb_otg: usb@1c19000 {
0296 compatible = "allwinner,sun8i-h3-musb";
0297 reg = <0x01c19000 0x0400>;
0298 clocks = <&ccu CLK_BUS_OTG>;
0299 resets = <&ccu RST_BUS_OTG>;
0300 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0301 interrupt-names = "mc";
0302 phys = <&usbphy 0>;
0303 phy-names = "usb";
0304 extcon = <&usbphy 0>;
0305 status = "disabled";
0306 };
0307
0308 usbphy: phy@1c19400 {
0309 compatible = "allwinner,sun8i-v3s-usb-phy";
0310 reg = <0x01c19400 0x2c>,
0311 <0x01c1a800 0x4>;
0312 reg-names = "phy_ctrl",
0313 "pmu0";
0314 clocks = <&ccu CLK_USB_PHY0>;
0315 clock-names = "usb0_phy";
0316 resets = <&ccu RST_USB_PHY0>;
0317 reset-names = "usb0_reset";
0318 status = "disabled";
0319 #phy-cells = <1>;
0320 };
0321
0322 ccu: clock@1c20000 {
0323 compatible = "allwinner,sun8i-v3s-ccu";
0324 reg = <0x01c20000 0x400>;
0325 clocks = <&osc24M>, <&rtc CLK_OSC32K>;
0326 clock-names = "hosc", "losc";
0327 #clock-cells = <1>;
0328 #reset-cells = <1>;
0329 };
0330
0331 rtc: rtc@1c20400 {
0332 #clock-cells = <1>;
0333 compatible = "allwinner,sun8i-v3-rtc";
0334 reg = <0x01c20400 0x54>;
0335 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
0336 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
0337 clocks = <&osc32k>;
0338 clock-output-names = "osc32k", "osc32k-out";
0339 };
0340
0341 pio: pinctrl@1c20800 {
0342 compatible = "allwinner,sun8i-v3s-pinctrl";
0343 reg = <0x01c20800 0x400>;
0344 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
0345 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0346 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
0347 <&rtc CLK_OSC32K>;
0348 clock-names = "apb", "hosc", "losc";
0349 gpio-controller;
0350 #gpio-cells = <3>;
0351 interrupt-controller;
0352 #interrupt-cells = <3>;
0353
0354 /omit-if-no-ref/
0355 csi0_mclk_pin: csi0-mclk-pin {
0356 pins = "PE20";
0357 function = "csi_mipi";
0358 };
0359
0360 /omit-if-no-ref/
0361 csi1_8bit_pins: csi1-8bit-pins {
0362 pins = "PE0", "PE2", "PE3", "PE8", "PE9",
0363 "PE10", "PE11", "PE12", "PE13", "PE14",
0364 "PE15";
0365 function = "csi";
0366 };
0367
0368 /omit-if-no-ref/
0369 csi1_mclk_pin: csi1-mclk-pin {
0370 pins = "PE1";
0371 function = "csi";
0372 };
0373
0374 i2c0_pins: i2c0-pins {
0375 pins = "PB6", "PB7";
0376 function = "i2c0";
0377 };
0378
0379 /omit-if-no-ref/
0380 i2c1_pb_pins: i2c1-pb-pins {
0381 pins = "PB8", "PB9";
0382 function = "i2c1";
0383 };
0384
0385 /omit-if-no-ref/
0386 i2c1_pe_pins: i2c1-pe-pins {
0387 pins = "PE21", "PE22";
0388 function = "i2c1";
0389 };
0390
0391 uart0_pb_pins: uart0-pb-pins {
0392 pins = "PB8", "PB9";
0393 function = "uart0";
0394 };
0395
0396 uart2_pins: uart2-pins {
0397 pins = "PB0", "PB1";
0398 function = "uart2";
0399 };
0400
0401 mmc0_pins: mmc0-pins {
0402 pins = "PF0", "PF1", "PF2", "PF3",
0403 "PF4", "PF5";
0404 function = "mmc0";
0405 drive-strength = <30>;
0406 bias-pull-up;
0407 };
0408
0409 mmc1_pins: mmc1-pins {
0410 pins = "PG0", "PG1", "PG2", "PG3",
0411 "PG4", "PG5";
0412 function = "mmc1";
0413 drive-strength = <30>;
0414 bias-pull-up;
0415 };
0416
0417 spi0_pins: spi0-pins {
0418 pins = "PC0", "PC1", "PC2", "PC3";
0419 function = "spi0";
0420 };
0421 };
0422
0423 timer@1c20c00 {
0424 compatible = "allwinner,sun8i-v3s-timer";
0425 reg = <0x01c20c00 0xa0>;
0426 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0427 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0428 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0429 clocks = <&osc24M>;
0430 };
0431
0432 wdt0: watchdog@1c20ca0 {
0433 compatible = "allwinner,sun6i-a31-wdt";
0434 reg = <0x01c20ca0 0x20>;
0435 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0436 clocks = <&osc24M>;
0437 };
0438
0439 pwm: pwm@1c21400 {
0440 compatible = "allwinner,sun8i-v3s-pwm",
0441 "allwinner,sun7i-a20-pwm";
0442 reg = <0x01c21400 0xc>;
0443 clocks = <&osc24M>;
0444 #pwm-cells = <3>;
0445 status = "disabled";
0446 };
0447
0448 lradc: lradc@1c22800 {
0449 compatible = "allwinner,sun4i-a10-lradc-keys";
0450 reg = <0x01c22800 0x400>;
0451 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0452 status = "disabled";
0453 };
0454
0455 codec: codec@1c22c00 {
0456 #sound-dai-cells = <0>;
0457 compatible = "allwinner,sun8i-v3s-codec";
0458 reg = <0x01c22c00 0x400>;
0459 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0460 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
0461 clock-names = "apb", "codec";
0462 resets = <&ccu RST_BUS_CODEC>;
0463 dmas = <&dma 15>, <&dma 15>;
0464 dma-names = "rx", "tx";
0465 allwinner,codec-analog-controls = <&codec_analog>;
0466 status = "disabled";
0467 };
0468
0469 codec_analog: codec-analog@1c23000 {
0470 compatible = "allwinner,sun8i-v3s-codec-analog";
0471 reg = <0x01c23000 0x4>;
0472 };
0473
0474 uart0: serial@1c28000 {
0475 compatible = "snps,dw-apb-uart";
0476 reg = <0x01c28000 0x400>;
0477 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
0478 reg-shift = <2>;
0479 reg-io-width = <4>;
0480 clocks = <&ccu CLK_BUS_UART0>;
0481 dmas = <&dma 6>, <&dma 6>;
0482 dma-names = "rx", "tx";
0483 resets = <&ccu RST_BUS_UART0>;
0484 status = "disabled";
0485 };
0486
0487 uart1: serial@1c28400 {
0488 compatible = "snps,dw-apb-uart";
0489 reg = <0x01c28400 0x400>;
0490 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0491 reg-shift = <2>;
0492 reg-io-width = <4>;
0493 clocks = <&ccu CLK_BUS_UART1>;
0494 dmas = <&dma 7>, <&dma 7>;
0495 dma-names = "rx", "tx";
0496 resets = <&ccu RST_BUS_UART1>;
0497 status = "disabled";
0498 };
0499
0500 uart2: serial@1c28800 {
0501 compatible = "snps,dw-apb-uart";
0502 reg = <0x01c28800 0x400>;
0503 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0504 reg-shift = <2>;
0505 reg-io-width = <4>;
0506 clocks = <&ccu CLK_BUS_UART2>;
0507 dmas = <&dma 8>, <&dma 8>;
0508 dma-names = "rx", "tx";
0509 resets = <&ccu RST_BUS_UART2>;
0510 pinctrl-0 = <&uart2_pins>;
0511 pinctrl-names = "default";
0512 status = "disabled";
0513 };
0514
0515 i2c0: i2c@1c2ac00 {
0516 compatible = "allwinner,sun6i-a31-i2c";
0517 reg = <0x01c2ac00 0x400>;
0518 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0519 clocks = <&ccu CLK_BUS_I2C0>;
0520 resets = <&ccu RST_BUS_I2C0>;
0521 pinctrl-names = "default";
0522 pinctrl-0 = <&i2c0_pins>;
0523 status = "disabled";
0524 #address-cells = <1>;
0525 #size-cells = <0>;
0526 };
0527
0528 i2c1: i2c@1c2b000 {
0529 compatible = "allwinner,sun6i-a31-i2c";
0530 reg = <0x01c2b000 0x400>;
0531 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0532 clocks = <&ccu CLK_BUS_I2C1>;
0533 resets = <&ccu RST_BUS_I2C1>;
0534 status = "disabled";
0535 #address-cells = <1>;
0536 #size-cells = <0>;
0537 };
0538
0539 emac: ethernet@1c30000 {
0540 compatible = "allwinner,sun8i-v3s-emac";
0541 syscon = <&syscon>;
0542 reg = <0x01c30000 0x10000>;
0543 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0544 interrupt-names = "macirq";
0545 resets = <&ccu RST_BUS_EMAC>;
0546 reset-names = "stmmaceth";
0547 clocks = <&ccu CLK_BUS_EMAC>;
0548 clock-names = "stmmaceth";
0549 phy-handle = <&int_mii_phy>;
0550 phy-mode = "mii";
0551 status = "disabled";
0552
0553 mdio: mdio {
0554 #address-cells = <1>;
0555 #size-cells = <0>;
0556 compatible = "snps,dwmac-mdio";
0557 };
0558
0559 mdio_mux: mdio-mux {
0560 compatible = "allwinner,sun8i-h3-mdio-mux";
0561 #address-cells = <1>;
0562 #size-cells = <0>;
0563
0564 mdio-parent-bus = <&mdio>;
0565 /* Only one MDIO is usable at the time */
0566 internal_mdio: mdio@1 {
0567 compatible = "allwinner,sun8i-h3-mdio-internal";
0568 reg = <1>;
0569 #address-cells = <1>;
0570 #size-cells = <0>;
0571
0572 int_mii_phy: ethernet-phy@1 {
0573 compatible = "ethernet-phy-ieee802.3-c22";
0574 reg = <1>;
0575 clocks = <&ccu CLK_BUS_EPHY>;
0576 resets = <&ccu RST_BUS_EPHY>;
0577 };
0578 };
0579 };
0580 };
0581
0582 spi0: spi@1c68000 {
0583 compatible = "allwinner,sun8i-h3-spi";
0584 reg = <0x01c68000 0x1000>;
0585 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0586 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
0587 clock-names = "ahb", "mod";
0588 dmas = <&dma 23>, <&dma 23>;
0589 dma-names = "rx", "tx";
0590 pinctrl-names = "default";
0591 pinctrl-0 = <&spi0_pins>;
0592 resets = <&ccu RST_BUS_SPI0>;
0593 status = "disabled";
0594 #address-cells = <1>;
0595 #size-cells = <0>;
0596 };
0597
0598 gic: interrupt-controller@1c81000 {
0599 compatible = "arm,gic-400";
0600 reg = <0x01c81000 0x1000>,
0601 <0x01c82000 0x2000>,
0602 <0x01c84000 0x2000>,
0603 <0x01c86000 0x2000>;
0604 interrupt-controller;
0605 #interrupt-cells = <3>;
0606 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0607 };
0608
0609 csi1: camera@1cb4000 {
0610 compatible = "allwinner,sun8i-v3s-csi";
0611 reg = <0x01cb4000 0x3000>;
0612 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0613 clocks = <&ccu CLK_BUS_CSI>,
0614 <&ccu CLK_CSI1_SCLK>,
0615 <&ccu CLK_DRAM_CSI>;
0616 clock-names = "bus", "mod", "ram";
0617 resets = <&ccu RST_BUS_CSI>;
0618 status = "disabled";
0619 };
0620 };
0621 };
