0001 /*
0002 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
0003 * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
0004 *
0005 * This file is dual-licensed: you can use it either under the terms
0006 * of the GPL or the X11 license, at your option. Note that this dual
0007 * licensing only applies to this file, and not this project as a
0008 * whole.
0009 *
0010 * a) This file is free software; you can redistribute it and/or
0011 * modify it under the terms of the GNU General Public License as
0012 * published by the Free Software Foundation; either version 2 of the
0013 * License, or (at your option) any later version.
0014 *
0015 * This file is distributed in the hope that it will be useful,
0016 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0017 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0018 * GNU General Public License for more details.
0019 *
0020 * Or, alternatively,
0021 *
0022 * b) Permission is hereby granted, free of charge, to any person
0023 * obtaining a copy of this software and associated documentation
0024 * files (the "Software"), to deal in the Software without
0025 * restriction, including without limitation the rights to use,
0026 * copy, modify, merge, publish, distribute, sublicense, and/or
0027 * sell copies of the Software, and to permit persons to whom the
0028 * Software is furnished to do so, subject to the following
0029 * conditions:
0030 *
0031 * The above copyright notice and this permission notice shall be
0032 * included in all copies or substantial portions of the Software.
0033 *
0034 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0035 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0036 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0037 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0038 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0039 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0040 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0041 * OTHER DEALINGS IN THE SOFTWARE.
0042 */
0043
0044 #include <dt-bindings/interrupt-controller/arm-gic.h>
0045 #include <dt-bindings/clock/sun6i-rtc.h>
0046 #include <dt-bindings/clock/sun8i-de2.h>
0047 #include <dt-bindings/clock/sun8i-r40-ccu.h>
0048 #include <dt-bindings/clock/sun8i-tcon-top.h>
0049 #include <dt-bindings/reset/sun8i-r40-ccu.h>
0050 #include <dt-bindings/reset/sun8i-de2.h>
0051 #include <dt-bindings/thermal/thermal.h>
0052
0053 / {
0054 #address-cells = <1>;
0055 #size-cells = <1>;
0056 interrupt-parent = <&gic>;
0057
0058 clocks {
0059 #address-cells = <1>;
0060 #size-cells = <1>;
0061 ranges;
0062
0063 osc24M: osc24M {
0064 #clock-cells = <0>;
0065 compatible = "fixed-clock";
0066 clock-frequency = <24000000>;
0067 clock-accuracy = <50000>;
0068 clock-output-names = "osc24M";
0069 };
0070
0071 osc32k: osc32k {
0072 #clock-cells = <0>;
0073 compatible = "fixed-clock";
0074 clock-frequency = <32768>;
0075 clock-accuracy = <20000>;
0076 clock-output-names = "ext-osc32k";
0077 };
0078 };
0079
0080 cpus {
0081 #address-cells = <1>;
0082 #size-cells = <0>;
0083
0084 cpu0: cpu@0 {
0085 compatible = "arm,cortex-a7";
0086 device_type = "cpu";
0087 reg = <0>;
0088 clocks = <&ccu CLK_CPU>;
0089 clock-names = "cpu";
0090 #cooling-cells = <2>;
0091 };
0092
0093 cpu1: cpu@1 {
0094 compatible = "arm,cortex-a7";
0095 device_type = "cpu";
0096 reg = <1>;
0097 clocks = <&ccu CLK_CPU>;
0098 clock-names = "cpu";
0099 #cooling-cells = <2>;
0100 };
0101
0102 cpu2: cpu@2 {
0103 compatible = "arm,cortex-a7";
0104 device_type = "cpu";
0105 reg = <2>;
0106 clocks = <&ccu CLK_CPU>;
0107 clock-names = "cpu";
0108 #cooling-cells = <2>;
0109 };
0110
0111 cpu3: cpu@3 {
0112 compatible = "arm,cortex-a7";
0113 device_type = "cpu";
0114 reg = <3>;
0115 clocks = <&ccu CLK_CPU>;
0116 clock-names = "cpu";
0117 #cooling-cells = <2>;
0118 };
0119 };
0120
0121 de: display-engine {
0122 compatible = "allwinner,sun8i-r40-display-engine";
0123 allwinner,pipelines = <&mixer0>, <&mixer1>;
0124 status = "disabled";
0125 };
0126
0127 thermal-zones {
0128 cpu_thermal: cpu0-thermal {
0129 /* milliseconds */
0130 polling-delay-passive = <0>;
0131 polling-delay = <0>;
0132 thermal-sensors = <&ths 0>;
0133
0134 trips {
0135 cpu_hot_trip: cpu-hot {
0136 temperature = <80000>;
0137 hysteresis = <2000>;
0138 type = "passive";
0139 };
0140
0141 cpu_very_hot_trip: cpu-very-hot {
0142 temperature = <115000>;
0143 hysteresis = <0>;
0144 type = "critical";
0145 };
0146 };
0147
0148 cooling-maps {
0149 cpu-hot-limit {
0150 trip = <&cpu_hot_trip>;
0151 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0152 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0153 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0154 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0155 };
0156 };
0157 };
0158
0159 gpu_thermal: gpu-thermal {
0160 /* milliseconds */
0161 polling-delay-passive = <0>;
0162 polling-delay = <0>;
0163 thermal-sensors = <&ths 1>;
0164 };
0165 };
0166
0167 soc {
0168 compatible = "simple-bus";
0169 #address-cells = <1>;
0170 #size-cells = <1>;
0171 ranges;
0172
0173 display_clocks: clock@1000000 {
0174 compatible = "allwinner,sun8i-r40-de2-clk",
0175 "allwinner,sun8i-h3-de2-clk";
0176 reg = <0x01000000 0x10000>;
0177 clocks = <&ccu CLK_BUS_DE>,
0178 <&ccu CLK_DE>;
0179 clock-names = "bus",
0180 "mod";
0181 resets = <&ccu RST_BUS_DE>;
0182 #clock-cells = <1>;
0183 #reset-cells = <1>;
0184 };
0185
0186 mixer0: mixer@1100000 {
0187 compatible = "allwinner,sun8i-r40-de2-mixer-0";
0188 reg = <0x01100000 0x100000>;
0189 clocks = <&display_clocks CLK_BUS_MIXER0>,
0190 <&display_clocks CLK_MIXER0>;
0191 clock-names = "bus",
0192 "mod";
0193 resets = <&display_clocks RST_MIXER0>;
0194
0195 ports {
0196 #address-cells = <1>;
0197 #size-cells = <0>;
0198
0199 mixer0_out: port@1 {
0200 reg = <1>;
0201 mixer0_out_tcon_top: endpoint {
0202 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
0203 };
0204 };
0205 };
0206 };
0207
0208 mixer1: mixer@1200000 {
0209 compatible = "allwinner,sun8i-r40-de2-mixer-1";
0210 reg = <0x01200000 0x100000>;
0211 clocks = <&display_clocks CLK_BUS_MIXER1>,
0212 <&display_clocks CLK_MIXER1>;
0213 clock-names = "bus",
0214 "mod";
0215 resets = <&display_clocks RST_WB>;
0216
0217 ports {
0218 #address-cells = <1>;
0219 #size-cells = <0>;
0220
0221 mixer1_out: port@1 {
0222 reg = <1>;
0223 mixer1_out_tcon_top: endpoint {
0224 remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
0225 };
0226 };
0227 };
0228 };
0229
0230 deinterlace: deinterlace@1400000 {
0231 compatible = "allwinner,sun8i-r40-deinterlace",
0232 "allwinner,sun8i-h3-deinterlace";
0233 reg = <0x01400000 0x20000>;
0234 clocks = <&ccu CLK_BUS_DEINTERLACE>,
0235 <&ccu CLK_DEINTERLACE>,
0236 /*
0237 * NOTE: Contrary to what datasheet claims,
0238 * DRAM deinterlace gate doesn't exist and
0239 * it's shared with CSI1.
0240 */
0241 <&ccu CLK_DRAM_CSI1>;
0242 clock-names = "bus", "mod", "ram";
0243 resets = <&ccu RST_BUS_DEINTERLACE>;
0244 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
0245 interconnects = <&mbus 9>;
0246 interconnect-names = "dma-mem";
0247 };
0248
0249 syscon: system-control@1c00000 {
0250 compatible = "allwinner,sun8i-r40-system-control",
0251 "allwinner,sun4i-a10-system-control";
0252 reg = <0x01c00000 0x30>;
0253 #address-cells = <1>;
0254 #size-cells = <1>;
0255 ranges;
0256
0257 sram_c: sram@1d00000 {
0258 compatible = "mmio-sram";
0259 reg = <0x01d00000 0xd0000>;
0260 #address-cells = <1>;
0261 #size-cells = <1>;
0262 ranges = <0 0x01d00000 0xd0000>;
0263
0264 ve_sram: sram-section@0 {
0265 compatible = "allwinner,sun8i-r40-sram-c1",
0266 "allwinner,sun4i-a10-sram-c1";
0267 reg = <0x000000 0x80000>;
0268 };
0269 };
0270 };
0271
0272 nmi_intc: interrupt-controller@1c00030 {
0273 compatible = "allwinner,sun7i-a20-sc-nmi";
0274 interrupt-controller;
0275 #interrupt-cells = <2>;
0276 reg = <0x01c00030 0x0c>;
0277 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
0278 };
0279
0280 dma: dma-controller@1c02000 {
0281 compatible = "allwinner,sun8i-r40-dma",
0282 "allwinner,sun50i-a64-dma";
0283 reg = <0x01c02000 0x1000>;
0284 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0285 clocks = <&ccu CLK_BUS_DMA>;
0286 dma-channels = <16>;
0287 dma-requests = <31>;
0288 resets = <&ccu RST_BUS_DMA>;
0289 #dma-cells = <1>;
0290 };
0291
0292 spi0: spi@1c05000 {
0293 compatible = "allwinner,sun8i-r40-spi",
0294 "allwinner,sun8i-h3-spi";
0295 reg = <0x01c05000 0x1000>;
0296 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0297 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
0298 clock-names = "ahb", "mod";
0299 resets = <&ccu RST_BUS_SPI0>;
0300 status = "disabled";
0301 #address-cells = <1>;
0302 #size-cells = <0>;
0303 };
0304
0305 spi1: spi@1c06000 {
0306 compatible = "allwinner,sun8i-r40-spi",
0307 "allwinner,sun8i-h3-spi";
0308 reg = <0x01c06000 0x1000>;
0309 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0310 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
0311 clock-names = "ahb", "mod";
0312 resets = <&ccu RST_BUS_SPI1>;
0313 status = "disabled";
0314 #address-cells = <1>;
0315 #size-cells = <0>;
0316 };
0317
0318 csi0: csi@1c09000 {
0319 compatible = "allwinner,sun8i-r40-csi0",
0320 "allwinner,sun7i-a20-csi0";
0321 reg = <0x01c09000 0x1000>;
0322 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0323 clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
0324 <&ccu CLK_DRAM_CSI0>;
0325 clock-names = "bus", "isp", "ram";
0326 resets = <&ccu RST_BUS_CSI0>;
0327 interconnects = <&mbus 5>;
0328 interconnect-names = "dma-mem";
0329 status = "disabled";
0330 };
0331
0332 video-codec@1c0e000 {
0333 compatible = "allwinner,sun8i-r40-video-engine";
0334 reg = <0x01c0e000 0x1000>;
0335 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
0336 <&ccu CLK_DRAM_VE>;
0337 clock-names = "ahb", "mod", "ram";
0338 resets = <&ccu RST_BUS_VE>;
0339 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
0340 allwinner,sram = <&ve_sram 1>;
0341 };
0342
0343 mmc0: mmc@1c0f000 {
0344 compatible = "allwinner,sun8i-r40-mmc",
0345 "allwinner,sun50i-a64-mmc";
0346 reg = <0x01c0f000 0x1000>;
0347 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
0348 clock-names = "ahb", "mmc";
0349 resets = <&ccu RST_BUS_MMC0>;
0350 reset-names = "ahb";
0351 pinctrl-0 = <&mmc0_pins>;
0352 pinctrl-names = "default";
0353 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0354 status = "disabled";
0355 #address-cells = <1>;
0356 #size-cells = <0>;
0357 };
0358
0359 mmc1: mmc@1c10000 {
0360 compatible = "allwinner,sun8i-r40-mmc",
0361 "allwinner,sun50i-a64-mmc";
0362 reg = <0x01c10000 0x1000>;
0363 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
0364 clock-names = "ahb", "mmc";
0365 resets = <&ccu RST_BUS_MMC1>;
0366 reset-names = "ahb";
0367 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0368 status = "disabled";
0369 #address-cells = <1>;
0370 #size-cells = <0>;
0371 };
0372
0373 mmc2: mmc@1c11000 {
0374 compatible = "allwinner,sun8i-r40-emmc",
0375 "allwinner,sun50i-a64-emmc";
0376 reg = <0x01c11000 0x1000>;
0377 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
0378 clock-names = "ahb", "mmc";
0379 resets = <&ccu RST_BUS_MMC2>;
0380 reset-names = "ahb";
0381 pinctrl-0 = <&mmc2_pins>;
0382 pinctrl-names = "default";
0383 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0384 status = "disabled";
0385 #address-cells = <1>;
0386 #size-cells = <0>;
0387 };
0388
0389 mmc3: mmc@1c12000 {
0390 compatible = "allwinner,sun8i-r40-mmc",
0391 "allwinner,sun50i-a64-mmc";
0392 reg = <0x01c12000 0x1000>;
0393 clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
0394 clock-names = "ahb", "mmc";
0395 resets = <&ccu RST_BUS_MMC3>;
0396 reset-names = "ahb";
0397 pinctrl-0 = <&mmc3_pins>;
0398 pinctrl-names = "default";
0399 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0400 status = "disabled";
0401 #address-cells = <1>;
0402 #size-cells = <0>;
0403 };
0404
0405 usbphy: phy@1c13400 {
0406 compatible = "allwinner,sun8i-r40-usb-phy";
0407 reg = <0x01c13400 0x14>,
0408 <0x01c14800 0x4>,
0409 <0x01c19800 0x4>,
0410 <0x01c1c800 0x4>;
0411 reg-names = "phy_ctrl",
0412 "pmu0",
0413 "pmu1",
0414 "pmu2";
0415 clocks = <&ccu CLK_USB_PHY0>,
0416 <&ccu CLK_USB_PHY1>,
0417 <&ccu CLK_USB_PHY2>;
0418 clock-names = "usb0_phy",
0419 "usb1_phy",
0420 "usb2_phy";
0421 resets = <&ccu RST_USB_PHY0>,
0422 <&ccu RST_USB_PHY1>,
0423 <&ccu RST_USB_PHY2>;
0424 reset-names = "usb0_reset",
0425 "usb1_reset",
0426 "usb2_reset";
0427 status = "disabled";
0428 #phy-cells = <1>;
0429 };
0430
0431 crypto: crypto@1c15000 {
0432 compatible = "allwinner,sun8i-r40-crypto";
0433 reg = <0x01c15000 0x1000>;
0434 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0435 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
0436 clock-names = "bus", "mod";
0437 resets = <&ccu RST_BUS_CE>;
0438 };
0439
0440 spi2: spi@1c17000 {
0441 compatible = "allwinner,sun8i-r40-spi",
0442 "allwinner,sun8i-h3-spi";
0443 reg = <0x01c17000 0x1000>;
0444 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0445 clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
0446 clock-names = "ahb", "mod";
0447 resets = <&ccu RST_BUS_SPI2>;
0448 status = "disabled";
0449 #address-cells = <1>;
0450 #size-cells = <0>;
0451 };
0452
0453 ahci: sata@1c18000 {
0454 compatible = "allwinner,sun8i-r40-ahci";
0455 reg = <0x01c18000 0x1000>;
0456 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0457 clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
0458 resets = <&ccu RST_BUS_SATA>;
0459 reset-names = "ahci";
0460 status = "disabled";
0461 };
0462
0463 ehci1: usb@1c19000 {
0464 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
0465 reg = <0x01c19000 0x100>;
0466 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0467 clocks = <&ccu CLK_BUS_EHCI1>;
0468 resets = <&ccu RST_BUS_EHCI1>;
0469 phys = <&usbphy 1>;
0470 phy-names = "usb";
0471 status = "disabled";
0472 };
0473
0474 ohci1: usb@1c19400 {
0475 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
0476 reg = <0x01c19400 0x100>;
0477 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
0478 clocks = <&ccu CLK_BUS_OHCI1>,
0479 <&ccu CLK_USB_OHCI1>;
0480 resets = <&ccu RST_BUS_OHCI1>;
0481 phys = <&usbphy 1>;
0482 phy-names = "usb";
0483 status = "disabled";
0484 };
0485
0486 ehci2: usb@1c1c000 {
0487 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
0488 reg = <0x01c1c000 0x100>;
0489 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
0490 clocks = <&ccu CLK_BUS_EHCI2>;
0491 resets = <&ccu RST_BUS_EHCI2>;
0492 phys = <&usbphy 2>;
0493 phy-names = "usb";
0494 status = "disabled";
0495 };
0496
0497 ohci2: usb@1c1c400 {
0498 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
0499 reg = <0x01c1c400 0x100>;
0500 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0501 clocks = <&ccu CLK_BUS_OHCI2>,
0502 <&ccu CLK_USB_OHCI2>;
0503 resets = <&ccu RST_BUS_OHCI2>;
0504 phys = <&usbphy 2>;
0505 phy-names = "usb";
0506 status = "disabled";
0507 };
0508
0509 spi3: spi@1c1f000 {
0510 compatible = "allwinner,sun8i-r40-spi",
0511 "allwinner,sun8i-h3-spi";
0512 reg = <0x01c1f000 0x1000>;
0513 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0514 clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
0515 clock-names = "ahb", "mod";
0516 resets = <&ccu RST_BUS_SPI3>;
0517 status = "disabled";
0518 #address-cells = <1>;
0519 #size-cells = <0>;
0520 };
0521
0522 ccu: clock@1c20000 {
0523 compatible = "allwinner,sun8i-r40-ccu";
0524 reg = <0x01c20000 0x400>;
0525 clocks = <&osc24M>, <&rtc CLK_OSC32K>;
0526 clock-names = "hosc", "losc";
0527 #clock-cells = <1>;
0528 #reset-cells = <1>;
0529 };
0530
0531 rtc: rtc@1c20400 {
0532 compatible = "allwinner,sun8i-r40-rtc";
0533 reg = <0x01c20400 0x400>;
0534 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0535 clock-output-names = "osc32k", "osc32k-out";
0536 clocks = <&osc32k>;
0537 #clock-cells = <1>;
0538 };
0539
0540 pio: pinctrl@1c20800 {
0541 compatible = "allwinner,sun8i-r40-pinctrl";
0542 reg = <0x01c20800 0x400>;
0543 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0544 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
0545 <&rtc CLK_OSC32K>;
0546 clock-names = "apb", "hosc", "losc";
0547 gpio-controller;
0548 interrupt-controller;
0549 #interrupt-cells = <3>;
0550 #gpio-cells = <3>;
0551
0552 can_ph_pins: can-ph-pins {
0553 pins = "PH20", "PH21";
0554 function = "can";
0555 };
0556
0557 can_pa_pins: can-pa-pins {
0558 pins = "PA16", "PA17";
0559 function = "can";
0560 };
0561
0562 clk_out_a_pin: clk-out-a-pin {
0563 pins = "PI12";
0564 function = "clk_out_a";
0565 };
0566
0567 /omit-if-no-ref/
0568 csi0_8bits_pins: csi0-8bits-pins {
0569 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
0570 "PE6", "PE7", "PE8", "PE9", "PE10",
0571 "PE11";
0572 function = "csi0";
0573 };
0574
0575 /omit-if-no-ref/
0576 csi0_mclk_pin: csi0-mclk-pin {
0577 pins = "PE1";
0578 function = "csi0";
0579 };
0580
0581 gmac_rgmii_pins: gmac-rgmii-pins {
0582 pins = "PA0", "PA1", "PA2", "PA3",
0583 "PA4", "PA5", "PA6", "PA7",
0584 "PA8", "PA10", "PA11", "PA12",
0585 "PA13", "PA15", "PA16";
0586 function = "gmac";
0587 /*
0588 * data lines in RGMII mode use DDR mode
0589 * and need a higher signal drive strength
0590 */
0591 drive-strength = <40>;
0592 };
0593
0594 i2c0_pins: i2c0-pins {
0595 pins = "PB0", "PB1";
0596 function = "i2c0";
0597 };
0598
0599 i2c1_pins: i2c1-pins {
0600 pins = "PB18", "PB19";
0601 function = "i2c1";
0602 };
0603
0604 i2c2_pins: i2c2-pins {
0605 pins = "PB20", "PB21";
0606 function = "i2c2";
0607 };
0608
0609 i2c3_pins: i2c3-pins {
0610 pins = "PI0", "PI1";
0611 function = "i2c3";
0612 };
0613
0614 i2c4_pins: i2c4-pins {
0615 pins = "PI2", "PI3";
0616 function = "i2c4";
0617 };
0618
0619 ir0_pins: ir0-pins {
0620 pins = "PB4";
0621 function = "ir0";
0622 };
0623
0624 ir1_pins: ir1-pins {
0625 pins = "PB23";
0626 function = "ir1";
0627 };
0628
0629 mmc0_pins: mmc0-pins {
0630 pins = "PF0", "PF1", "PF2",
0631 "PF3", "PF4", "PF5";
0632 function = "mmc0";
0633 drive-strength = <30>;
0634 bias-pull-up;
0635 };
0636
0637 mmc1_pg_pins: mmc1-pg-pins {
0638 pins = "PG0", "PG1", "PG2",
0639 "PG3", "PG4", "PG5";
0640 function = "mmc1";
0641 drive-strength = <30>;
0642 bias-pull-up;
0643 };
0644
0645 mmc2_pins: mmc2-pins {
0646 pins = "PC5", "PC6", "PC7", "PC8", "PC9",
0647 "PC10", "PC11", "PC12", "PC13", "PC14",
0648 "PC15", "PC24";
0649 function = "mmc2";
0650 drive-strength = <30>;
0651 bias-pull-up;
0652 };
0653
0654 /omit-if-no-ref/
0655 mmc3_pins: mmc3-pins {
0656 pins = "PI4", "PI5", "PI6",
0657 "PI7", "PI8", "PI9";
0658 function = "mmc3";
0659 drive-strength = <30>;
0660 bias-pull-up;
0661 };
0662
0663 /omit-if-no-ref/
0664 spi0_pc_pins: spi0-pc-pins {
0665 pins = "PC0", "PC1", "PC2";
0666 function = "spi0";
0667 };
0668
0669 /omit-if-no-ref/
0670 spi0_cs0_pc_pin: spi0-cs0-pc-pin {
0671 pins = "PC23";
0672 function = "spi0";
0673 };
0674
0675 /omit-if-no-ref/
0676 spi1_pi_pins: spi1-pi-pins {
0677 pins = "PI17", "PI18", "PI19";
0678 function = "spi1";
0679 };
0680
0681 /omit-if-no-ref/
0682 spi1_cs0_pi_pin: spi1-cs0-pi-pin {
0683 pins = "PI16";
0684 function = "spi1";
0685 };
0686
0687 /omit-if-no-ref/
0688 spi1_cs1_pi_pin: spi1-cs1-pi-pin {
0689 pins = "PI15";
0690 function = "spi1";
0691 };
0692
0693 /omit-if-no-ref/
0694 uart0_pb_pins: uart0-pb-pins {
0695 pins = "PB22", "PB23";
0696 function = "uart0";
0697 };
0698
0699 /omit-if-no-ref/
0700 uart2_pi_pins: uart2-pi-pins {
0701 pins = "PI18", "PI19";
0702 function = "uart2";
0703 };
0704
0705 /omit-if-no-ref/
0706 uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{
0707 pins = "PI16", "PI17";
0708 function = "uart2";
0709 };
0710
0711 /omit-if-no-ref/
0712 uart3_pg_pins: uart3-pg-pins {
0713 pins = "PG6", "PG7";
0714 function = "uart3";
0715 };
0716
0717 /omit-if-no-ref/
0718 uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
0719 pins = "PG8", "PG9";
0720 function = "uart3";
0721 };
0722
0723 /omit-if-no-ref/
0724 uart4_pg_pins: uart4-pg-pins {
0725 pins = "PG10", "PG11";
0726 function = "uart4";
0727 };
0728
0729 /omit-if-no-ref/
0730 uart5_ph_pins: uart5-ph-pins {
0731 pins = "PH6", "PH7";
0732 function = "uart5";
0733 };
0734
0735 /omit-if-no-ref/
0736 uart7_pi_pins: uart7-pi-pins {
0737 pins = "PI20", "PI21";
0738 function = "uart7";
0739 };
0740 };
0741
0742 timer@1c20c00 {
0743 compatible = "allwinner,sun4i-a10-timer";
0744 reg = <0x01c20c00 0x90>;
0745 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
0746 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
0747 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
0748 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
0749 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
0750 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
0751 clocks = <&osc24M>;
0752 };
0753
0754 wdt: watchdog@1c20c90 {
0755 compatible = "allwinner,sun4i-a10-wdt";
0756 reg = <0x01c20c90 0x10>;
0757 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0758 clocks = <&osc24M>;
0759 };
0760
0761 ir0: ir@1c21800 {
0762 compatible = "allwinner,sun8i-r40-ir",
0763 "allwinner,sun6i-a31-ir";
0764 reg = <0x01c21800 0x400>;
0765 pinctrl-0 = <&ir0_pins>;
0766 pinctrl-names = "default";
0767 clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>;
0768 clock-names = "apb", "ir";
0769 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
0770 resets = <&ccu RST_BUS_IR0>;
0771 status = "disabled";
0772 };
0773
0774 ir1: ir@1c21c00 {
0775 compatible = "allwinner,sun8i-r40-ir",
0776 "allwinner,sun6i-a31-ir";
0777 reg = <0x01c21c00 0x400>;
0778 pinctrl-0 = <&ir1_pins>;
0779 pinctrl-names = "default";
0780 clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>;
0781 clock-names = "apb", "ir";
0782 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0783 resets = <&ccu RST_BUS_IR1>;
0784 status = "disabled";
0785 };
0786
0787 i2s0: i2s@1c22000 {
0788 #sound-dai-cells = <0>;
0789 compatible = "allwinner,sun8i-r40-i2s",
0790 "allwinner,sun8i-h3-i2s";
0791 reg = <0x01c22000 0x400>;
0792 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
0793 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
0794 clock-names = "apb", "mod";
0795 resets = <&ccu RST_BUS_I2S0>;
0796 dmas = <&dma 3>, <&dma 3>;
0797 dma-names = "rx", "tx";
0798 };
0799
0800 i2s1: i2s@1c22400 {
0801 #sound-dai-cells = <0>;
0802 compatible = "allwinner,sun8i-r40-i2s",
0803 "allwinner,sun8i-h3-i2s";
0804 reg = <0x01c22400 0x400>;
0805 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0806 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
0807 clock-names = "apb", "mod";
0808 resets = <&ccu RST_BUS_I2S1>;
0809 dmas = <&dma 4>, <&dma 4>;
0810 dma-names = "rx", "tx";
0811 };
0812
0813 i2s2: i2s@1c22800 {
0814 #sound-dai-cells = <0>;
0815 compatible = "allwinner,sun8i-r40-i2s",
0816 "allwinner,sun8i-h3-i2s";
0817 reg = <0x01c22800 0x400>;
0818 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0819 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
0820 clock-names = "apb", "mod";
0821 resets = <&ccu RST_BUS_I2S2>;
0822 dmas = <&dma 6>, <&dma 6>;
0823 dma-names = "rx", "tx";
0824 };
0825
0826 ths: thermal-sensor@1c24c00 {
0827 compatible = "allwinner,sun8i-r40-ths";
0828 reg = <0x01c24c00 0x100>;
0829 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
0830 clock-names = "bus", "mod";
0831 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0832 resets = <&ccu RST_BUS_THS>;
0833 /* TODO: add nvmem-cells for calibration */
0834 #thermal-sensor-cells = <1>;
0835 };
0836
0837 uart0: serial@1c28000 {
0838 compatible = "snps,dw-apb-uart";
0839 reg = <0x01c28000 0x400>;
0840 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0841 reg-shift = <2>;
0842 reg-io-width = <4>;
0843 clocks = <&ccu CLK_BUS_UART0>;
0844 resets = <&ccu RST_BUS_UART0>;
0845 status = "disabled";
0846 };
0847
0848 uart1: serial@1c28400 {
0849 compatible = "snps,dw-apb-uart";
0850 reg = <0x01c28400 0x400>;
0851 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0852 reg-shift = <2>;
0853 reg-io-width = <4>;
0854 clocks = <&ccu CLK_BUS_UART1>;
0855 resets = <&ccu RST_BUS_UART1>;
0856 status = "disabled";
0857 };
0858
0859 uart2: serial@1c28800 {
0860 compatible = "snps,dw-apb-uart";
0861 reg = <0x01c28800 0x400>;
0862 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0863 reg-shift = <2>;
0864 reg-io-width = <4>;
0865 clocks = <&ccu CLK_BUS_UART2>;
0866 resets = <&ccu RST_BUS_UART2>;
0867 status = "disabled";
0868 };
0869
0870 uart3: serial@1c28c00 {
0871 compatible = "snps,dw-apb-uart";
0872 reg = <0x01c28c00 0x400>;
0873 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0874 reg-shift = <2>;
0875 reg-io-width = <4>;
0876 clocks = <&ccu CLK_BUS_UART3>;
0877 resets = <&ccu RST_BUS_UART3>;
0878 status = "disabled";
0879 };
0880
0881 uart4: serial@1c29000 {
0882 compatible = "snps,dw-apb-uart";
0883 reg = <0x01c29000 0x400>;
0884 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0885 reg-shift = <2>;
0886 reg-io-width = <4>;
0887 clocks = <&ccu CLK_BUS_UART4>;
0888 resets = <&ccu RST_BUS_UART4>;
0889 status = "disabled";
0890 };
0891
0892 uart5: serial@1c29400 {
0893 compatible = "snps,dw-apb-uart";
0894 reg = <0x01c29400 0x400>;
0895 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
0896 reg-shift = <2>;
0897 reg-io-width = <4>;
0898 clocks = <&ccu CLK_BUS_UART5>;
0899 resets = <&ccu RST_BUS_UART5>;
0900 status = "disabled";
0901 };
0902
0903 uart6: serial@1c29800 {
0904 compatible = "snps,dw-apb-uart";
0905 reg = <0x01c29800 0x400>;
0906 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0907 reg-shift = <2>;
0908 reg-io-width = <4>;
0909 clocks = <&ccu CLK_BUS_UART6>;
0910 resets = <&ccu RST_BUS_UART6>;
0911 status = "disabled";
0912 };
0913
0914 uart7: serial@1c29c00 {
0915 compatible = "snps,dw-apb-uart";
0916 reg = <0x01c29c00 0x400>;
0917 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
0918 reg-shift = <2>;
0919 reg-io-width = <4>;
0920 clocks = <&ccu CLK_BUS_UART7>;
0921 resets = <&ccu RST_BUS_UART7>;
0922 status = "disabled";
0923 };
0924
0925 i2c0: i2c@1c2ac00 {
0926 compatible = "allwinner,sun6i-a31-i2c";
0927 reg = <0x01c2ac00 0x400>;
0928 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0929 clocks = <&ccu CLK_BUS_I2C0>;
0930 resets = <&ccu RST_BUS_I2C0>;
0931 pinctrl-0 = <&i2c0_pins>;
0932 pinctrl-names = "default";
0933 status = "disabled";
0934 #address-cells = <1>;
0935 #size-cells = <0>;
0936 };
0937
0938 i2c1: i2c@1c2b000 {
0939 compatible = "allwinner,sun6i-a31-i2c";
0940 reg = <0x01c2b000 0x400>;
0941 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0942 clocks = <&ccu CLK_BUS_I2C1>;
0943 resets = <&ccu RST_BUS_I2C1>;
0944 pinctrl-0 = <&i2c1_pins>;
0945 pinctrl-names = "default";
0946 status = "disabled";
0947 #address-cells = <1>;
0948 #size-cells = <0>;
0949 };
0950
0951 i2c2: i2c@1c2b400 {
0952 compatible = "allwinner,sun6i-a31-i2c";
0953 reg = <0x01c2b400 0x400>;
0954 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0955 clocks = <&ccu CLK_BUS_I2C2>;
0956 resets = <&ccu RST_BUS_I2C2>;
0957 pinctrl-0 = <&i2c2_pins>;
0958 pinctrl-names = "default";
0959 status = "disabled";
0960 #address-cells = <1>;
0961 #size-cells = <0>;
0962 };
0963
0964 i2c3: i2c@1c2b800 {
0965 compatible = "allwinner,sun6i-a31-i2c";
0966 reg = <0x01c2b800 0x400>;
0967 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
0968 clocks = <&ccu CLK_BUS_I2C3>;
0969 resets = <&ccu RST_BUS_I2C3>;
0970 pinctrl-0 = <&i2c3_pins>;
0971 pinctrl-names = "default";
0972 status = "disabled";
0973 #address-cells = <1>;
0974 #size-cells = <0>;
0975 };
0976
0977 can0: can@1c2bc00 {
0978 compatible = "allwinner,sun8i-r40-can";
0979 reg = <0x01c2bc00 0x400>;
0980 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0981 clocks = <&ccu CLK_BUS_CAN>;
0982 resets = <&ccu RST_BUS_CAN>;
0983 status = "disabled";
0984 };
0985
0986 i2c4: i2c@1c2c000 {
0987 compatible = "allwinner,sun6i-a31-i2c";
0988 reg = <0x01c2c000 0x400>;
0989 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0990 clocks = <&ccu CLK_BUS_I2C4>;
0991 resets = <&ccu RST_BUS_I2C4>;
0992 pinctrl-0 = <&i2c4_pins>;
0993 pinctrl-names = "default";
0994 status = "disabled";
0995 #address-cells = <1>;
0996 #size-cells = <0>;
0997 };
0998
0999 mali: gpu@1c40000 {
1000 compatible = "allwinner,sun8i-r40-mali", "arm,mali-400";
1001 reg = <0x01c40000 0x10000>;
1002 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1003 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1004 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1005 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1006 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
1007 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1008 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1009 interrupt-names = "gp",
1010 "gpmmu",
1011 "pp0",
1012 "ppmmu0",
1013 "pp1",
1014 "ppmmu1",
1015 "pmu";
1016 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
1017 clock-names = "bus", "core";
1018 resets = <&ccu RST_BUS_GPU>;
1019 };
1020
1021 gmac: ethernet@1c50000 {
1022 compatible = "allwinner,sun8i-r40-gmac";
1023 syscon = <&ccu>;
1024 reg = <0x01c50000 0x10000>;
1025 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1026 interrupt-names = "macirq";
1027 resets = <&ccu RST_BUS_GMAC>;
1028 reset-names = "stmmaceth";
1029 clocks = <&ccu CLK_BUS_GMAC>;
1030 clock-names = "stmmaceth";
1031 status = "disabled";
1032
1033 gmac_mdio: mdio {
1034 compatible = "snps,dwmac-mdio";
1035 #address-cells = <1>;
1036 #size-cells = <0>;
1037 };
1038 };
1039
1040 mbus: dram-controller@1c62000 {
1041 compatible = "allwinner,sun8i-r40-mbus";
1042 reg = <0x01c62000 0x1000>;
1043 clocks = <&ccu 155>;
1044 #address-cells = <1>;
1045 #size-cells = <1>;
1046 dma-ranges = <0x00000000 0x40000000 0x80000000>;
1047 #interconnect-cells = <1>;
1048 };
1049
1050 tcon_top: tcon-top@1c70000 {
1051 compatible = "allwinner,sun8i-r40-tcon-top";
1052 reg = <0x01c70000 0x1000>;
1053 clocks = <&ccu CLK_BUS_TCON_TOP>,
1054 <&ccu CLK_TCON_TV0>,
1055 <&ccu CLK_TVE0>,
1056 <&ccu CLK_TCON_TV1>,
1057 <&ccu CLK_TVE1>,
1058 <&ccu CLK_DSI_DPHY>;
1059 clock-names = "bus",
1060 "tcon-tv0",
1061 "tve0",
1062 "tcon-tv1",
1063 "tve1",
1064 "dsi";
1065 clock-output-names = "tcon-top-tv0",
1066 "tcon-top-tv1",
1067 "tcon-top-dsi";
1068 resets = <&ccu RST_BUS_TCON_TOP>;
1069 #clock-cells = <1>;
1070
1071 ports {
1072 #address-cells = <1>;
1073 #size-cells = <0>;
1074
1075 tcon_top_mixer0_in: port@0 {
1076 reg = <0>;
1077
1078 tcon_top_mixer0_in_mixer0: endpoint {
1079 remote-endpoint = <&mixer0_out_tcon_top>;
1080 };
1081 };
1082
1083 tcon_top_mixer0_out: port@1 {
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1086 reg = <1>;
1087
1088 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
1089 reg = <0>;
1090 };
1091
1092 tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
1093 reg = <1>;
1094 };
1095
1096 tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
1097 reg = <2>;
1098 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
1099 };
1100
1101 tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
1102 reg = <3>;
1103 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
1104 };
1105 };
1106
1107 tcon_top_mixer1_in: port@2 {
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1110 reg = <2>;
1111
1112 tcon_top_mixer1_in_mixer1: endpoint@1 {
1113 reg = <1>;
1114 remote-endpoint = <&mixer1_out_tcon_top>;
1115 };
1116 };
1117
1118 tcon_top_mixer1_out: port@3 {
1119 #address-cells = <1>;
1120 #size-cells = <0>;
1121 reg = <3>;
1122
1123 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
1124 reg = <0>;
1125 };
1126
1127 tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
1128 reg = <1>;
1129 };
1130
1131 tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
1132 reg = <2>;
1133 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
1134 };
1135
1136 tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
1137 reg = <3>;
1138 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
1139 };
1140 };
1141
1142 tcon_top_hdmi_in: port@4 {
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1145 reg = <4>;
1146
1147 tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
1148 reg = <0>;
1149 remote-endpoint = <&tcon_tv0_out_tcon_top>;
1150 };
1151
1152 tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
1153 reg = <1>;
1154 remote-endpoint = <&tcon_tv1_out_tcon_top>;
1155 };
1156 };
1157
1158 tcon_top_hdmi_out: port@5 {
1159 reg = <5>;
1160
1161 tcon_top_hdmi_out_hdmi: endpoint {
1162 remote-endpoint = <&hdmi_in_tcon_top>;
1163 };
1164 };
1165 };
1166 };
1167
1168 tcon_tv0: lcd-controller@1c73000 {
1169 compatible = "allwinner,sun8i-r40-tcon-tv";
1170 reg = <0x01c73000 0x1000>;
1171 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1172 clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>;
1173 clock-names = "ahb", "tcon-ch1";
1174 resets = <&ccu RST_BUS_TCON_TV0>;
1175 reset-names = "lcd";
1176 status = "disabled";
1177
1178 ports {
1179 #address-cells = <1>;
1180 #size-cells = <0>;
1181
1182 tcon_tv0_in: port@0 {
1183 #address-cells = <1>;
1184 #size-cells = <0>;
1185 reg = <0>;
1186
1187 tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
1188 reg = <0>;
1189 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
1190 };
1191
1192 tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
1193 reg = <1>;
1194 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
1195 };
1196 };
1197
1198 tcon_tv0_out: port@1 {
1199 #address-cells = <1>;
1200 #size-cells = <0>;
1201 reg = <1>;
1202
1203 tcon_tv0_out_tcon_top: endpoint@1 {
1204 reg = <1>;
1205 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
1206 };
1207 };
1208 };
1209 };
1210
1211 tcon_tv1: lcd-controller@1c74000 {
1212 compatible = "allwinner,sun8i-r40-tcon-tv";
1213 reg = <0x01c74000 0x1000>;
1214 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1215 clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>;
1216 clock-names = "ahb", "tcon-ch1";
1217 resets = <&ccu RST_BUS_TCON_TV1>;
1218 reset-names = "lcd";
1219 status = "disabled";
1220
1221 ports {
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1224
1225 tcon_tv1_in: port@0 {
1226 #address-cells = <1>;
1227 #size-cells = <0>;
1228 reg = <0>;
1229
1230 tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
1231 reg = <0>;
1232 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
1233 };
1234
1235 tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
1236 reg = <1>;
1237 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
1238 };
1239 };
1240
1241 tcon_tv1_out: port@1 {
1242 #address-cells = <1>;
1243 #size-cells = <0>;
1244 reg = <1>;
1245
1246 tcon_tv1_out_tcon_top: endpoint@1 {
1247 reg = <1>;
1248 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
1249 };
1250 };
1251 };
1252 };
1253
1254 gic: interrupt-controller@1c81000 {
1255 compatible = "arm,gic-400";
1256 reg = <0x01c81000 0x1000>,
1257 <0x01c82000 0x2000>,
1258 <0x01c84000 0x2000>,
1259 <0x01c86000 0x2000>;
1260 interrupt-controller;
1261 #interrupt-cells = <3>;
1262 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1263 };
1264
1265 hdmi: hdmi@1ee0000 {
1266 compatible = "allwinner,sun8i-r40-dw-hdmi",
1267 "allwinner,sun8i-a83t-dw-hdmi";
1268 reg = <0x01ee0000 0x10000>;
1269 reg-io-width = <1>;
1270 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1271 clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
1272 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
1273 clock-names = "iahb", "isfr", "tmds", "cec";
1274 resets = <&ccu RST_BUS_HDMI1>;
1275 reset-names = "ctrl";
1276 phys = <&hdmi_phy>;
1277 phy-names = "phy";
1278 status = "disabled";
1279
1280 ports {
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1283
1284 hdmi_in: port@0 {
1285 reg = <0>;
1286
1287 hdmi_in_tcon_top: endpoint {
1288 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
1289 };
1290 };
1291
1292 hdmi_out: port@1 {
1293 reg = <1>;
1294 };
1295 };
1296 };
1297
1298 hdmi_phy: hdmi-phy@1ef0000 {
1299 compatible = "allwinner,sun8i-r40-hdmi-phy";
1300 reg = <0x01ef0000 0x10000>;
1301 clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
1302 <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>;
1303 clock-names = "bus", "mod", "pll-0", "pll-1";
1304 resets = <&ccu RST_BUS_HDMI0>;
1305 reset-names = "phy";
1306 #phy-cells = <0>;
1307 };
1308 };
1309
1310 pmu {
1311 compatible = "arm,cortex-a7-pmu";
1312 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1313 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1314 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1315 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1316 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
1317 };
1318
1319 timer {
1320 compatible = "arm,armv7-timer";
1321 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1322 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1323 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1324 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1325 };
1326 };
