0001 /*
0002 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
0003 *
0004 * This file is dual-licensed: you can use it either under the terms
0005 * of the GPL or the X11 license, at your option. Note that this dual
0006 * licensing only applies to this file, and not this project as a
0007 * whole.
0008 *
0009 * a) This file is free software; you can redistribute it and/or
0010 * modify it under the terms of the GNU General Public License as
0011 * published by the Free Software Foundation; either version 2 of the
0012 * License, or (at your option) any later version.
0013 *
0014 * This file is distributed in the hope that it will be useful,
0015 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0017 * GNU General Public License for more details.
0018 *
0019 * Or, alternatively,
0020 *
0021 * b) Permission is hereby granted, free of charge, to any person
0022 * obtaining a copy of this software and associated documentation
0023 * files (the "Software"), to deal in the Software without
0024 * restriction, including without limitation the rights to use,
0025 * copy, modify, merge, publish, distribute, sublicense, and/or
0026 * sell copies of the Software, and to permit persons to whom the
0027 * Software is furnished to do so, subject to the following
0028 * conditions:
0029 *
0030 * The above copyright notice and this permission notice shall be
0031 * included in all copies or substantial portions of the Software.
0032 *
0033 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0034 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0035 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0036 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0037 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0038 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0039 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0040 * OTHER DEALINGS IN THE SOFTWARE.
0041 */
0042
0043 #include "sunxi-h3-h5.dtsi"
0044 #include <dt-bindings/thermal/thermal.h>
0045
0046 / {
0047 cpu0_opp_table: opp-table-cpu {
0048 compatible = "operating-points-v2";
0049 opp-shared;
0050
0051 opp-648000000 {
0052 opp-hz = /bits/ 64 <648000000>;
0053 opp-microvolt = <1040000 1040000 1300000>;
0054 clock-latency-ns = <244144>; /* 8 32k periods */
0055 };
0056
0057 opp-816000000 {
0058 opp-hz = /bits/ 64 <816000000>;
0059 opp-microvolt = <1100000 1100000 1300000>;
0060 clock-latency-ns = <244144>; /* 8 32k periods */
0061 };
0062
0063 opp-1008000000 {
0064 opp-hz = /bits/ 64 <1008000000>;
0065 opp-microvolt = <1200000 1200000 1300000>;
0066 clock-latency-ns = <244144>; /* 8 32k periods */
0067 };
0068 };
0069
0070 cpus {
0071 #address-cells = <1>;
0072 #size-cells = <0>;
0073
0074 cpu0: cpu@0 {
0075 compatible = "arm,cortex-a7";
0076 device_type = "cpu";
0077 reg = <0>;
0078 clocks = <&ccu CLK_CPUX>;
0079 clock-names = "cpu";
0080 operating-points-v2 = <&cpu0_opp_table>;
0081 #cooling-cells = <2>;
0082 };
0083
0084 cpu1: cpu@1 {
0085 compatible = "arm,cortex-a7";
0086 device_type = "cpu";
0087 reg = <1>;
0088 clocks = <&ccu CLK_CPUX>;
0089 clock-names = "cpu";
0090 operating-points-v2 = <&cpu0_opp_table>;
0091 #cooling-cells = <2>;
0092 };
0093
0094 cpu2: cpu@2 {
0095 compatible = "arm,cortex-a7";
0096 device_type = "cpu";
0097 reg = <2>;
0098 clocks = <&ccu CLK_CPUX>;
0099 clock-names = "cpu";
0100 operating-points-v2 = <&cpu0_opp_table>;
0101 #cooling-cells = <2>;
0102 };
0103
0104 cpu3: cpu@3 {
0105 compatible = "arm,cortex-a7";
0106 device_type = "cpu";
0107 reg = <3>;
0108 clocks = <&ccu CLK_CPUX>;
0109 clock-names = "cpu";
0110 operating-points-v2 = <&cpu0_opp_table>;
0111 #cooling-cells = <2>;
0112 };
0113 };
0114
0115 gpu_opp_table: opp-table-gpu {
0116 compatible = "operating-points-v2";
0117
0118 opp-120000000 {
0119 opp-hz = /bits/ 64 <120000000>;
0120 };
0121
0122 opp-312000000 {
0123 opp-hz = /bits/ 64 <312000000>;
0124 };
0125
0126 opp-432000000 {
0127 opp-hz = /bits/ 64 <432000000>;
0128 };
0129
0130 opp-576000000 {
0131 opp-hz = /bits/ 64 <576000000>;
0132 };
0133 };
0134
0135 pmu {
0136 compatible = "arm,cortex-a7-pmu";
0137 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
0138 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
0139 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
0140 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
0141 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
0142 };
0143
0144 timer {
0145 compatible = "arm,armv7-timer";
0146 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0147 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0148 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0149 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0150 };
0151
0152 soc {
0153 deinterlace: deinterlace@1400000 {
0154 compatible = "allwinner,sun8i-h3-deinterlace";
0155 reg = <0x01400000 0x20000>;
0156 clocks = <&ccu CLK_BUS_DEINTERLACE>,
0157 <&ccu CLK_DEINTERLACE>,
0158 <&ccu CLK_DRAM_DEINTERLACE>;
0159 clock-names = "bus", "mod", "ram";
0160 resets = <&ccu RST_BUS_DEINTERLACE>;
0161 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
0162 interconnects = <&mbus 9>;
0163 interconnect-names = "dma-mem";
0164 };
0165
0166 syscon: system-control@1c00000 {
0167 compatible = "allwinner,sun8i-h3-system-control";
0168 reg = <0x01c00000 0x1000>;
0169 #address-cells = <1>;
0170 #size-cells = <1>;
0171 ranges;
0172
0173 sram_c: sram@1d00000 {
0174 compatible = "mmio-sram";
0175 reg = <0x01d00000 0x80000>;
0176 #address-cells = <1>;
0177 #size-cells = <1>;
0178 ranges = <0 0x01d00000 0x80000>;
0179
0180 ve_sram: sram-section@0 {
0181 compatible = "allwinner,sun8i-h3-sram-c1",
0182 "allwinner,sun4i-a10-sram-c1";
0183 reg = <0x000000 0x80000>;
0184 };
0185 };
0186 };
0187
0188 video-codec@1c0e000 {
0189 compatible = "allwinner,sun8i-h3-video-engine";
0190 reg = <0x01c0e000 0x1000>;
0191 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
0192 <&ccu CLK_DRAM_VE>;
0193 clock-names = "ahb", "mod", "ram";
0194 resets = <&ccu RST_BUS_VE>;
0195 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
0196 allwinner,sram = <&ve_sram 1>;
0197 };
0198
0199 crypto: crypto@1c15000 {
0200 compatible = "allwinner,sun8i-h3-crypto";
0201 reg = <0x01c15000 0x1000>;
0202 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0203 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
0204 clock-names = "bus", "mod";
0205 resets = <&ccu RST_BUS_CE>;
0206 };
0207
0208 mali: gpu@1c40000 {
0209 compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
0210 reg = <0x01c40000 0x10000>;
0211 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
0212 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
0213 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
0214 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
0215 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
0216 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
0217 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
0218 interrupt-names = "gp",
0219 "gpmmu",
0220 "pp0",
0221 "ppmmu0",
0222 "pp1",
0223 "ppmmu1",
0224 "pmu";
0225 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
0226 clock-names = "bus", "core";
0227 resets = <&ccu RST_BUS_GPU>;
0228 operating-points-v2 = <&gpu_opp_table>;
0229 };
0230
0231 ths: thermal-sensor@1c25000 {
0232 compatible = "allwinner,sun8i-h3-ths";
0233 reg = <0x01c25000 0x400>;
0234 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
0235 resets = <&ccu RST_BUS_THS>;
0236 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
0237 clock-names = "bus", "mod";
0238 nvmem-cells = <&ths_calibration>;
0239 nvmem-cell-names = "calibration";
0240 #thermal-sensor-cells = <0>;
0241 };
0242 };
0243
0244 thermal-zones {
0245 cpu_thermal: cpu-thermal {
0246 polling-delay-passive = <0>;
0247 polling-delay = <0>;
0248 thermal-sensors = <&ths>;
0249
0250 trips {
0251 cpu_hot_trip: cpu-hot {
0252 temperature = <80000>;
0253 hysteresis = <2000>;
0254 type = "passive";
0255 };
0256
0257 cpu_very_hot_trip: cpu-very-hot {
0258 temperature = <100000>;
0259 hysteresis = <0>;
0260 type = "critical";
0261 };
0262 };
0263
0264 cooling-maps {
0265 cpu-hot-limit {
0266 trip = <&cpu_hot_trip>;
0267 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0268 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0269 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0270 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0271 };
0272 };
0273 };
0274 };
0275 };
0276
0277 &ccu {
0278 compatible = "allwinner,sun8i-h3-ccu";
0279 };
0280
0281 &display_clocks {
0282 compatible = "allwinner,sun8i-h3-de2-clk";
0283 };
0284
0285 &mbus {
0286 compatible = "allwinner,sun8i-h3-mbus";
0287 };
0288
0289 &mmc0 {
0290 compatible = "allwinner,sun7i-a20-mmc";
0291 clocks = <&ccu CLK_BUS_MMC0>,
0292 <&ccu CLK_MMC0>,
0293 <&ccu CLK_MMC0_OUTPUT>,
0294 <&ccu CLK_MMC0_SAMPLE>;
0295 clock-names = "ahb",
0296 "mmc",
0297 "output",
0298 "sample";
0299 };
0300
0301 &mmc1 {
0302 compatible = "allwinner,sun7i-a20-mmc";
0303 clocks = <&ccu CLK_BUS_MMC1>,
0304 <&ccu CLK_MMC1>,
0305 <&ccu CLK_MMC1_OUTPUT>,
0306 <&ccu CLK_MMC1_SAMPLE>;
0307 clock-names = "ahb",
0308 "mmc",
0309 "output",
0310 "sample";
0311 };
0312
0313 &mmc2 {
0314 compatible = "allwinner,sun7i-a20-mmc";
0315 clocks = <&ccu CLK_BUS_MMC2>,
0316 <&ccu CLK_MMC2>,
0317 <&ccu CLK_MMC2_OUTPUT>,
0318 <&ccu CLK_MMC2_SAMPLE>;
0319 clock-names = "ahb",
0320 "mmc",
0321 "output",
0322 "sample";
0323 };
0324
0325 &pio {
0326 compatible = "allwinner,sun8i-h3-pinctrl";
0327 };
0328
0329 &rtc {
0330 compatible = "allwinner,sun8i-h3-rtc";
0331 };
0332
0333 &sid {
0334 compatible = "allwinner,sun8i-h3-sid";
0335 };
