0001 /*
0002 * Copyright 2015 Vishnu Patekar
0003 *
0004 * Vishnu Patekar <vishnupatekar0510@gmail.com>
0005 *
0006 * This file is dual-licensed: you can use it either under the terms
0007 * of the GPL or the X11 license, at your option. Note that this dual
0008 * licensing only applies to this file, and not this project as a
0009 * whole.
0010 *
0011 * a) This file is free software; you can redistribute it and/or
0012 * modify it under the terms of the GNU General Public License as
0013 * published by the Free Software Foundation; either version 2 of the
0014 * License, or (at your option) any later version.
0015 *
0016 * This file is distributed in the hope that it will be useful,
0017 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0019 * GNU General Public License for more details.
0020 *
0021 * Or, alternatively,
0022 *
0023 * b) Permission is hereby granted, free of charge, to any person
0024 * obtaining a copy of this software and associated documentation
0025 * files (the "Software"), to deal in the Software without
0026 * restriction, including without limitation the rights to use,
0027 * copy, modify, merge, publish, distribute, sublicense, and/or
0028 * sell copies of the Software, and to permit persons to whom the
0029 * Software is furnished to do so, subject to the following
0030 * conditions:
0031 *
0032 * The above copyright notice and this permission notice shall be
0033 * included in all copies or substantial portions of the Software.
0034 *
0035 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0036 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0037 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0038 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0039 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0040 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0041 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0042 * OTHER DEALINGS IN THE SOFTWARE.
0043 */
0044
0045 #include <dt-bindings/interrupt-controller/arm-gic.h>
0046
0047 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
0048 #include <dt-bindings/clock/sun8i-de2.h>
0049 #include <dt-bindings/clock/sun8i-r-ccu.h>
0050 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
0051 #include <dt-bindings/reset/sun8i-de2.h>
0052 #include <dt-bindings/reset/sun8i-r-ccu.h>
0053 #include <dt-bindings/thermal/thermal.h>
0054
0055 / {
0056 interrupt-parent = <&gic>;
0057 #address-cells = <1>;
0058 #size-cells = <1>;
0059
0060 cpus {
0061 #address-cells = <1>;
0062 #size-cells = <0>;
0063
0064 cpu0: cpu@0 {
0065 compatible = "arm,cortex-a7";
0066 device_type = "cpu";
0067 clocks = <&ccu CLK_C0CPUX>;
0068 operating-points-v2 = <&cpu0_opp_table>;
0069 cci-control-port = <&cci_control0>;
0070 enable-method = "allwinner,sun8i-a83t-smp";
0071 reg = <0>;
0072 #cooling-cells = <2>;
0073 };
0074
0075 cpu1: cpu@1 {
0076 compatible = "arm,cortex-a7";
0077 device_type = "cpu";
0078 clocks = <&ccu CLK_C0CPUX>;
0079 operating-points-v2 = <&cpu0_opp_table>;
0080 cci-control-port = <&cci_control0>;
0081 enable-method = "allwinner,sun8i-a83t-smp";
0082 reg = <1>;
0083 #cooling-cells = <2>;
0084 };
0085
0086 cpu2: cpu@2 {
0087 compatible = "arm,cortex-a7";
0088 device_type = "cpu";
0089 clocks = <&ccu CLK_C0CPUX>;
0090 operating-points-v2 = <&cpu0_opp_table>;
0091 cci-control-port = <&cci_control0>;
0092 enable-method = "allwinner,sun8i-a83t-smp";
0093 reg = <2>;
0094 #cooling-cells = <2>;
0095 };
0096
0097 cpu3: cpu@3 {
0098 compatible = "arm,cortex-a7";
0099 device_type = "cpu";
0100 clocks = <&ccu CLK_C0CPUX>;
0101 operating-points-v2 = <&cpu0_opp_table>;
0102 cci-control-port = <&cci_control0>;
0103 enable-method = "allwinner,sun8i-a83t-smp";
0104 reg = <3>;
0105 #cooling-cells = <2>;
0106 };
0107
0108 cpu100: cpu@100 {
0109 compatible = "arm,cortex-a7";
0110 device_type = "cpu";
0111 clocks = <&ccu CLK_C1CPUX>;
0112 operating-points-v2 = <&cpu1_opp_table>;
0113 cci-control-port = <&cci_control1>;
0114 enable-method = "allwinner,sun8i-a83t-smp";
0115 reg = <0x100>;
0116 #cooling-cells = <2>;
0117 };
0118
0119 cpu101: cpu@101 {
0120 compatible = "arm,cortex-a7";
0121 device_type = "cpu";
0122 clocks = <&ccu CLK_C1CPUX>;
0123 operating-points-v2 = <&cpu1_opp_table>;
0124 cci-control-port = <&cci_control1>;
0125 enable-method = "allwinner,sun8i-a83t-smp";
0126 reg = <0x101>;
0127 #cooling-cells = <2>;
0128 };
0129
0130 cpu102: cpu@102 {
0131 compatible = "arm,cortex-a7";
0132 device_type = "cpu";
0133 clocks = <&ccu CLK_C1CPUX>;
0134 operating-points-v2 = <&cpu1_opp_table>;
0135 cci-control-port = <&cci_control1>;
0136 enable-method = "allwinner,sun8i-a83t-smp";
0137 reg = <0x102>;
0138 #cooling-cells = <2>;
0139 };
0140
0141 cpu103: cpu@103 {
0142 compatible = "arm,cortex-a7";
0143 device_type = "cpu";
0144 clocks = <&ccu CLK_C1CPUX>;
0145 operating-points-v2 = <&cpu1_opp_table>;
0146 cci-control-port = <&cci_control1>;
0147 enable-method = "allwinner,sun8i-a83t-smp";
0148 reg = <0x103>;
0149 #cooling-cells = <2>;
0150 };
0151 };
0152
0153 timer {
0154 compatible = "arm,armv7-timer";
0155 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0156 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0157 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
0158 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
0159 };
0160
0161 clocks {
0162 #address-cells = <1>;
0163 #size-cells = <1>;
0164 ranges;
0165
0166 /* TODO: PRCM block has a mux for this. */
0167 osc24M: osc24M_clk {
0168 #clock-cells = <0>;
0169 compatible = "fixed-clock";
0170 clock-frequency = <24000000>;
0171 clock-accuracy = <50000>;
0172 clock-output-names = "osc24M";
0173 };
0174
0175 /*
0176 * This is called "internal OSC" in some places.
0177 * It is an internal RC-based oscillator.
0178 * TODO: Its controls are in the PRCM block.
0179 */
0180 osc16M: osc16M_clk {
0181 #clock-cells = <0>;
0182 compatible = "fixed-clock";
0183 clock-frequency = <16000000>;
0184 clock-output-names = "osc16M";
0185 };
0186
0187 osc16Md512: osc16Md512_clk {
0188 #clock-cells = <0>;
0189 compatible = "fixed-factor-clock";
0190 clock-div = <512>;
0191 clock-mult = <1>;
0192 clocks = <&osc16M>;
0193 clock-output-names = "osc16M-d512";
0194 };
0195 };
0196
0197 de: display-engine {
0198 compatible = "allwinner,sun8i-a83t-display-engine";
0199 allwinner,pipelines = <&mixer0>, <&mixer1>;
0200 status = "disabled";
0201 };
0202
0203 cpu0_opp_table: opp-table-cluster0 {
0204 compatible = "operating-points-v2";
0205 opp-shared;
0206
0207 opp-480000000 {
0208 opp-hz = /bits/ 64 <480000000>;
0209 opp-microvolt = <840000>;
0210 clock-latency-ns = <244144>; /* 8 32k periods */
0211 };
0212
0213 opp-600000000 {
0214 opp-hz = /bits/ 64 <600000000>;
0215 opp-microvolt = <840000>;
0216 clock-latency-ns = <244144>; /* 8 32k periods */
0217 };
0218
0219 opp-720000000 {
0220 opp-hz = /bits/ 64 <720000000>;
0221 opp-microvolt = <840000>;
0222 clock-latency-ns = <244144>; /* 8 32k periods */
0223 };
0224
0225 opp-864000000 {
0226 opp-hz = /bits/ 64 <864000000>;
0227 opp-microvolt = <840000>;
0228 clock-latency-ns = <244144>; /* 8 32k periods */
0229 };
0230
0231 opp-912000000 {
0232 opp-hz = /bits/ 64 <912000000>;
0233 opp-microvolt = <840000>;
0234 clock-latency-ns = <244144>; /* 8 32k periods */
0235 };
0236
0237 opp-1008000000 {
0238 opp-hz = /bits/ 64 <1008000000>;
0239 opp-microvolt = <840000>;
0240 clock-latency-ns = <244144>; /* 8 32k periods */
0241 };
0242
0243 opp-1128000000 {
0244 opp-hz = /bits/ 64 <1128000000>;
0245 opp-microvolt = <840000>;
0246 clock-latency-ns = <244144>; /* 8 32k periods */
0247 };
0248
0249 opp-1200000000 {
0250 opp-hz = /bits/ 64 <1200000000>;
0251 opp-microvolt = <840000>;
0252 clock-latency-ns = <244144>; /* 8 32k periods */
0253 };
0254 };
0255
0256 cpu1_opp_table: opp-table-cluster1 {
0257 compatible = "operating-points-v2";
0258 opp-shared;
0259
0260 opp-480000000 {
0261 opp-hz = /bits/ 64 <480000000>;
0262 opp-microvolt = <840000>;
0263 clock-latency-ns = <244144>; /* 8 32k periods */
0264 };
0265
0266 opp-600000000 {
0267 opp-hz = /bits/ 64 <600000000>;
0268 opp-microvolt = <840000>;
0269 clock-latency-ns = <244144>; /* 8 32k periods */
0270 };
0271
0272 opp-720000000 {
0273 opp-hz = /bits/ 64 <720000000>;
0274 opp-microvolt = <840000>;
0275 clock-latency-ns = <244144>; /* 8 32k periods */
0276 };
0277
0278 opp-864000000 {
0279 opp-hz = /bits/ 64 <864000000>;
0280 opp-microvolt = <840000>;
0281 clock-latency-ns = <244144>; /* 8 32k periods */
0282 };
0283
0284 opp-912000000 {
0285 opp-hz = /bits/ 64 <912000000>;
0286 opp-microvolt = <840000>;
0287 clock-latency-ns = <244144>; /* 8 32k periods */
0288 };
0289
0290 opp-1008000000 {
0291 opp-hz = /bits/ 64 <1008000000>;
0292 opp-microvolt = <840000>;
0293 clock-latency-ns = <244144>; /* 8 32k periods */
0294 };
0295
0296 opp-1128000000 {
0297 opp-hz = /bits/ 64 <1128000000>;
0298 opp-microvolt = <840000>;
0299 clock-latency-ns = <244144>; /* 8 32k periods */
0300 };
0301
0302 opp-1200000000 {
0303 opp-hz = /bits/ 64 <1200000000>;
0304 opp-microvolt = <840000>;
0305 clock-latency-ns = <244144>; /* 8 32k periods */
0306 };
0307 };
0308
0309 soc {
0310 compatible = "simple-bus";
0311 #address-cells = <1>;
0312 #size-cells = <1>;
0313 ranges;
0314
0315 display_clocks: clock@1000000 {
0316 compatible = "allwinner,sun8i-a83t-de2-clk";
0317 reg = <0x01000000 0x10000>;
0318 clocks = <&ccu CLK_BUS_DE>,
0319 <&ccu CLK_PLL_DE>;
0320 clock-names = "bus",
0321 "mod";
0322 resets = <&ccu RST_BUS_DE>;
0323 #clock-cells = <1>;
0324 #reset-cells = <1>;
0325 };
0326
0327 rotate: rotate@1020000 {
0328 compatible = "allwinner,sun8i-a83t-de2-rotate";
0329 reg = <0x1020000 0x10000>;
0330 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0331 clocks = <&display_clocks CLK_BUS_ROT>,
0332 <&display_clocks CLK_ROT>;
0333 clock-names = "bus",
0334 "mod";
0335 resets = <&display_clocks RST_ROT>;
0336 };
0337
0338 mixer0: mixer@1100000 {
0339 compatible = "allwinner,sun8i-a83t-de2-mixer-0";
0340 reg = <0x01100000 0x100000>;
0341 clocks = <&display_clocks CLK_BUS_MIXER0>,
0342 <&display_clocks CLK_MIXER0>;
0343 clock-names = "bus",
0344 "mod";
0345 resets = <&display_clocks RST_MIXER0>;
0346
0347 ports {
0348 #address-cells = <1>;
0349 #size-cells = <0>;
0350
0351 mixer0_out: port@1 {
0352 #address-cells = <1>;
0353 #size-cells = <0>;
0354 reg = <1>;
0355
0356 mixer0_out_tcon0: endpoint@0 {
0357 reg = <0>;
0358 remote-endpoint = <&tcon0_in_mixer0>;
0359 };
0360
0361 mixer0_out_tcon1: endpoint@1 {
0362 reg = <1>;
0363 remote-endpoint = <&tcon1_in_mixer0>;
0364 };
0365 };
0366 };
0367 };
0368
0369 mixer1: mixer@1200000 {
0370 compatible = "allwinner,sun8i-a83t-de2-mixer-1";
0371 reg = <0x01200000 0x100000>;
0372 clocks = <&display_clocks CLK_BUS_MIXER1>,
0373 <&display_clocks CLK_MIXER1>;
0374 clock-names = "bus",
0375 "mod";
0376 resets = <&display_clocks RST_WB>;
0377
0378 ports {
0379 #address-cells = <1>;
0380 #size-cells = <0>;
0381
0382 mixer1_out: port@1 {
0383 #address-cells = <1>;
0384 #size-cells = <0>;
0385 reg = <1>;
0386
0387 mixer1_out_tcon0: endpoint@0 {
0388 reg = <0>;
0389 remote-endpoint = <&tcon0_in_mixer1>;
0390 };
0391
0392 mixer1_out_tcon1: endpoint@1 {
0393 reg = <1>;
0394 remote-endpoint = <&tcon1_in_mixer1>;
0395 };
0396 };
0397 };
0398 };
0399
0400 cpucfg@1700000 {
0401 compatible = "allwinner,sun8i-a83t-cpucfg";
0402 reg = <0x01700000 0x400>;
0403 };
0404
0405 cci@1790000 {
0406 compatible = "arm,cci-400";
0407 #address-cells = <1>;
0408 #size-cells = <1>;
0409 reg = <0x01790000 0x10000>;
0410 ranges = <0x0 0x01790000 0x10000>;
0411
0412 cci_control0: slave-if@4000 {
0413 compatible = "arm,cci-400-ctrl-if";
0414 interface-type = "ace";
0415 reg = <0x4000 0x1000>;
0416 };
0417
0418 cci_control1: slave-if@5000 {
0419 compatible = "arm,cci-400-ctrl-if";
0420 interface-type = "ace";
0421 reg = <0x5000 0x1000>;
0422 };
0423
0424 pmu@9000 {
0425 compatible = "arm,cci-400-pmu,r1";
0426 reg = <0x9000 0x5000>;
0427 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
0428 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
0429 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
0430 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
0431 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
0432 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
0433 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
0434 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
0435 };
0436 };
0437
0438 syscon: syscon@1c00000 {
0439 compatible = "allwinner,sun8i-a83t-system-controller",
0440 "syscon";
0441 reg = <0x01c00000 0x1000>;
0442 };
0443
0444 dma: dma-controller@1c02000 {
0445 compatible = "allwinner,sun8i-a83t-dma";
0446 reg = <0x01c02000 0x1000>;
0447 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0448 clocks = <&ccu CLK_BUS_DMA>;
0449 resets = <&ccu RST_BUS_DMA>;
0450 #dma-cells = <1>;
0451 };
0452
0453 tcon0: lcd-controller@1c0c000 {
0454 compatible = "allwinner,sun8i-a83t-tcon-lcd";
0455 reg = <0x01c0c000 0x1000>;
0456 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0457 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
0458 clock-names = "ahb", "tcon-ch0";
0459 clock-output-names = "tcon-pixel-clock";
0460 #clock-cells = <0>;
0461 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
0462 reset-names = "lcd", "lvds";
0463
0464 ports {
0465 #address-cells = <1>;
0466 #size-cells = <0>;
0467
0468 tcon0_in: port@0 {
0469 #address-cells = <1>;
0470 #size-cells = <0>;
0471 reg = <0>;
0472
0473 tcon0_in_mixer0: endpoint@0 {
0474 reg = <0>;
0475 remote-endpoint = <&mixer0_out_tcon0>;
0476 };
0477
0478 tcon0_in_mixer1: endpoint@1 {
0479 reg = <1>;
0480 remote-endpoint = <&mixer1_out_tcon0>;
0481 };
0482 };
0483
0484 tcon0_out: port@1 {
0485 reg = <1>;
0486 };
0487 };
0488 };
0489
0490 tcon1: lcd-controller@1c0d000 {
0491 compatible = "allwinner,sun8i-a83t-tcon-tv";
0492 reg = <0x01c0d000 0x1000>;
0493 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0494 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
0495 clock-names = "ahb", "tcon-ch1";
0496 resets = <&ccu RST_BUS_TCON1>;
0497 reset-names = "lcd";
0498
0499 ports {
0500 #address-cells = <1>;
0501 #size-cells = <0>;
0502
0503 tcon1_in: port@0 {
0504 #address-cells = <1>;
0505 #size-cells = <0>;
0506 reg = <0>;
0507
0508 tcon1_in_mixer0: endpoint@0 {
0509 reg = <0>;
0510 remote-endpoint = <&mixer0_out_tcon1>;
0511 };
0512
0513 tcon1_in_mixer1: endpoint@1 {
0514 reg = <1>;
0515 remote-endpoint = <&mixer1_out_tcon1>;
0516 };
0517 };
0518
0519 tcon1_out: port@1 {
0520 #address-cells = <1>;
0521 #size-cells = <0>;
0522 reg = <1>;
0523
0524 tcon1_out_hdmi: endpoint@1 {
0525 reg = <1>;
0526 remote-endpoint = <&hdmi_in_tcon1>;
0527 };
0528 };
0529 };
0530 };
0531
0532 mmc0: mmc@1c0f000 {
0533 compatible = "allwinner,sun8i-a83t-mmc",
0534 "allwinner,sun7i-a20-mmc";
0535 reg = <0x01c0f000 0x1000>;
0536 clocks = <&ccu CLK_BUS_MMC0>,
0537 <&ccu CLK_MMC0>,
0538 <&ccu CLK_MMC0_OUTPUT>,
0539 <&ccu CLK_MMC0_SAMPLE>;
0540 clock-names = "ahb",
0541 "mmc",
0542 "output",
0543 "sample";
0544 resets = <&ccu RST_BUS_MMC0>;
0545 reset-names = "ahb";
0546 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0547 status = "disabled";
0548 #address-cells = <1>;
0549 #size-cells = <0>;
0550 };
0551
0552 mmc1: mmc@1c10000 {
0553 compatible = "allwinner,sun8i-a83t-mmc",
0554 "allwinner,sun7i-a20-mmc";
0555 reg = <0x01c10000 0x1000>;
0556 clocks = <&ccu CLK_BUS_MMC1>,
0557 <&ccu CLK_MMC1>,
0558 <&ccu CLK_MMC1_OUTPUT>,
0559 <&ccu CLK_MMC1_SAMPLE>;
0560 clock-names = "ahb",
0561 "mmc",
0562 "output",
0563 "sample";
0564 resets = <&ccu RST_BUS_MMC1>;
0565 reset-names = "ahb";
0566 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0567 pinctrl-names = "default";
0568 pinctrl-0 = <&mmc1_pins>;
0569 status = "disabled";
0570 #address-cells = <1>;
0571 #size-cells = <0>;
0572 };
0573
0574 mmc2: mmc@1c11000 {
0575 compatible = "allwinner,sun8i-a83t-emmc";
0576 reg = <0x01c11000 0x1000>;
0577 clocks = <&ccu CLK_BUS_MMC2>,
0578 <&ccu CLK_MMC2>,
0579 <&ccu CLK_MMC2_OUTPUT>,
0580 <&ccu CLK_MMC2_SAMPLE>;
0581 clock-names = "ahb",
0582 "mmc",
0583 "output",
0584 "sample";
0585 resets = <&ccu RST_BUS_MMC2>;
0586 reset-names = "ahb";
0587 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0588 status = "disabled";
0589 #address-cells = <1>;
0590 #size-cells = <0>;
0591 };
0592
0593 sid: eeprom@1c14000 {
0594 compatible = "allwinner,sun8i-a83t-sid";
0595 reg = <0x1c14000 0x400>;
0596 #address-cells = <1>;
0597 #size-cells = <1>;
0598
0599 ths_calibration: thermal-sensor-calibration@34 {
0600 reg = <0x34 8>;
0601 };
0602 };
0603
0604 crypto: crypto@1c15000 {
0605 compatible = "allwinner,sun8i-a83t-crypto";
0606 reg = <0x01c15000 0x1000>;
0607 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
0608 resets = <&ccu RST_BUS_SS>;
0609 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
0610 clock-names = "bus", "mod";
0611 };
0612
0613 msgbox: mailbox@1c17000 {
0614 compatible = "allwinner,sun8i-a83t-msgbox",
0615 "allwinner,sun6i-a31-msgbox";
0616 reg = <0x01c17000 0x1000>;
0617 clocks = <&ccu CLK_BUS_MSGBOX>;
0618 resets = <&ccu RST_BUS_MSGBOX>;
0619 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0620 #mbox-cells = <1>;
0621 };
0622
0623 usb_otg: usb@1c19000 {
0624 compatible = "allwinner,sun8i-a83t-musb",
0625 "allwinner,sun8i-a33-musb";
0626 reg = <0x01c19000 0x0400>;
0627 clocks = <&ccu CLK_BUS_OTG>;
0628 resets = <&ccu RST_BUS_OTG>;
0629 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0630 interrupt-names = "mc";
0631 phys = <&usbphy 0>;
0632 phy-names = "usb";
0633 extcon = <&usbphy 0>;
0634 dr_mode = "otg";
0635 status = "disabled";
0636 };
0637
0638 usbphy: phy@1c19400 {
0639 compatible = "allwinner,sun8i-a83t-usb-phy";
0640 reg = <0x01c19400 0x10>,
0641 <0x01c1a800 0x14>,
0642 <0x01c1b800 0x14>;
0643 reg-names = "phy_ctrl",
0644 "pmu1",
0645 "pmu2";
0646 clocks = <&ccu CLK_USB_PHY0>,
0647 <&ccu CLK_USB_PHY1>,
0648 <&ccu CLK_USB_HSIC>,
0649 <&ccu CLK_USB_HSIC_12M>;
0650 clock-names = "usb0_phy",
0651 "usb1_phy",
0652 "usb2_phy",
0653 "usb2_hsic_12M";
0654 resets = <&ccu RST_USB_PHY0>,
0655 <&ccu RST_USB_PHY1>,
0656 <&ccu RST_USB_HSIC>;
0657 reset-names = "usb0_reset",
0658 "usb1_reset",
0659 "usb2_reset";
0660 status = "disabled";
0661 #phy-cells = <1>;
0662 };
0663
0664 ehci0: usb@1c1a000 {
0665 compatible = "allwinner,sun8i-a83t-ehci",
0666 "generic-ehci";
0667 reg = <0x01c1a000 0x100>;
0668 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0669 clocks = <&ccu CLK_BUS_EHCI0>;
0670 resets = <&ccu RST_BUS_EHCI0>;
0671 phys = <&usbphy 1>;
0672 phy-names = "usb";
0673 status = "disabled";
0674 };
0675
0676 ohci0: usb@1c1a400 {
0677 compatible = "allwinner,sun8i-a83t-ohci",
0678 "generic-ohci";
0679 reg = <0x01c1a400 0x100>;
0680 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0681 clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
0682 resets = <&ccu RST_BUS_OHCI0>;
0683 phys = <&usbphy 1>;
0684 phy-names = "usb";
0685 status = "disabled";
0686 };
0687
0688 ehci1: usb@1c1b000 {
0689 compatible = "allwinner,sun8i-a83t-ehci",
0690 "generic-ehci";
0691 reg = <0x01c1b000 0x100>;
0692 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0693 clocks = <&ccu CLK_BUS_EHCI1>;
0694 resets = <&ccu RST_BUS_EHCI1>;
0695 phys = <&usbphy 2>;
0696 phy-names = "usb";
0697 status = "disabled";
0698 };
0699
0700 ccu: clock@1c20000 {
0701 compatible = "allwinner,sun8i-a83t-ccu";
0702 reg = <0x01c20000 0x400>;
0703 clocks = <&osc24M>, <&osc16Md512>;
0704 clock-names = "hosc", "losc";
0705 #clock-cells = <1>;
0706 #reset-cells = <1>;
0707 };
0708
0709 pio: pinctrl@1c20800 {
0710 compatible = "allwinner,sun8i-a83t-pinctrl";
0711 interrupt-parent = <&r_intc>;
0712 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
0713 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
0714 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
0715 reg = <0x01c20800 0x400>;
0716 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
0717 clock-names = "apb", "hosc", "losc";
0718 gpio-controller;
0719 interrupt-controller;
0720 #interrupt-cells = <3>;
0721 #gpio-cells = <3>;
0722
0723 /omit-if-no-ref/
0724 csi_8bit_parallel_pins: csi-8bit-parallel-pins {
0725 pins = "PE0", "PE2", "PE3", "PE6", "PE7",
0726 "PE8", "PE9", "PE10", "PE11",
0727 "PE12", "PE13";
0728 function = "csi";
0729 };
0730
0731 /omit-if-no-ref/
0732 csi_mclk_pin: csi-mclk-pin {
0733 pins = "PE1";
0734 function = "csi";
0735 };
0736
0737 emac_rgmii_pins: emac-rgmii-pins {
0738 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
0739 "PD11", "PD12", "PD13", "PD14", "PD18",
0740 "PD19", "PD21", "PD22", "PD23";
0741 function = "gmac";
0742 /*
0743 * data lines in RGMII mode use DDR mode
0744 * and need a higher signal drive strength
0745 */
0746 drive-strength = <40>;
0747 };
0748
0749 hdmi_pins: hdmi-pins {
0750 pins = "PH6", "PH7", "PH8";
0751 function = "hdmi";
0752 };
0753
0754 i2c0_pins: i2c0-pins {
0755 pins = "PH0", "PH1";
0756 function = "i2c0";
0757 };
0758
0759 i2c1_pins: i2c1-pins {
0760 pins = "PH2", "PH3";
0761 function = "i2c1";
0762 };
0763
0764 /omit-if-no-ref/
0765 i2c2_pe_pins: i2c2-pe-pins {
0766 pins = "PE14", "PE15";
0767 function = "i2c2";
0768 };
0769
0770 i2c2_ph_pins: i2c2-ph-pins {
0771 pins = "PH4", "PH5";
0772 function = "i2c2";
0773 };
0774
0775 i2s1_pins: i2s1-pins {
0776 /* I2S1 does not have external MCLK pin */
0777 pins = "PG10", "PG11", "PG12", "PG13";
0778 function = "i2s1";
0779 };
0780
0781 lcd_lvds_pins: lcd-lvds-pins {
0782 pins = "PD18", "PD19", "PD20", "PD21", "PD22",
0783 "PD23", "PD24", "PD25", "PD26", "PD27";
0784 function = "lvds0";
0785 };
0786
0787 mmc0_pins: mmc0-pins {
0788 pins = "PF0", "PF1", "PF2",
0789 "PF3", "PF4", "PF5";
0790 function = "mmc0";
0791 drive-strength = <30>;
0792 bias-pull-up;
0793 };
0794
0795 mmc1_pins: mmc1-pins {
0796 pins = "PG0", "PG1", "PG2",
0797 "PG3", "PG4", "PG5";
0798 function = "mmc1";
0799 drive-strength = <30>;
0800 bias-pull-up;
0801 };
0802
0803 mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
0804 pins = "PC5", "PC6", "PC8", "PC9",
0805 "PC10", "PC11", "PC12", "PC13",
0806 "PC14", "PC15", "PC16";
0807 function = "mmc2";
0808 drive-strength = <30>;
0809 bias-pull-up;
0810 };
0811
0812 pwm_pin: pwm-pin {
0813 pins = "PD28";
0814 function = "pwm";
0815 };
0816
0817 spdif_tx_pin: spdif-tx-pin {
0818 pins = "PE18";
0819 function = "spdif";
0820 };
0821
0822 uart0_pb_pins: uart0-pb-pins {
0823 pins = "PB9", "PB10";
0824 function = "uart0";
0825 };
0826
0827 uart0_pf_pins: uart0-pf-pins {
0828 pins = "PF2", "PF4";
0829 function = "uart0";
0830 };
0831
0832 uart1_pins: uart1-pins {
0833 pins = "PG6", "PG7";
0834 function = "uart1";
0835 };
0836
0837 uart1_rts_cts_pins: uart1-rts-cts-pins {
0838 pins = "PG8", "PG9";
0839 function = "uart1";
0840 };
0841
0842 /omit-if-no-ref/
0843 uart2_pb_pins: uart2-pb-pins {
0844 pins = "PB0", "PB1";
0845 function = "uart2";
0846 };
0847 };
0848
0849 timer@1c20c00 {
0850 compatible = "allwinner,sun8i-a23-timer";
0851 reg = <0x01c20c00 0xa0>;
0852 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0853 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0854 clocks = <&osc24M>;
0855 };
0856
0857 watchdog@1c20ca0 {
0858 compatible = "allwinner,sun6i-a31-wdt";
0859 reg = <0x01c20ca0 0x20>;
0860 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0861 clocks = <&osc24M>;
0862 };
0863
0864 spdif: spdif@1c21000 {
0865 #sound-dai-cells = <0>;
0866 compatible = "allwinner,sun8i-a83t-spdif",
0867 "allwinner,sun8i-h3-spdif";
0868 reg = <0x01c21000 0x400>;
0869 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0870 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
0871 resets = <&ccu RST_BUS_SPDIF>;
0872 clock-names = "apb", "spdif";
0873 dmas = <&dma 2>;
0874 dma-names = "tx";
0875 pinctrl-names = "default";
0876 pinctrl-0 = <&spdif_tx_pin>;
0877 status = "disabled";
0878 };
0879
0880 i2s0: i2s@1c22000 {
0881 #sound-dai-cells = <0>;
0882 compatible = "allwinner,sun8i-a83t-i2s";
0883 reg = <0x01c22000 0x400>;
0884 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0885 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
0886 clock-names = "apb", "mod";
0887 dmas = <&dma 3>, <&dma 3>;
0888 resets = <&ccu RST_BUS_I2S0>;
0889 dma-names = "rx", "tx";
0890 status = "disabled";
0891 };
0892
0893 i2s1: i2s@1c22400 {
0894 #sound-dai-cells = <0>;
0895 compatible = "allwinner,sun8i-a83t-i2s";
0896 reg = <0x01c22400 0x400>;
0897 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0898 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
0899 clock-names = "apb", "mod";
0900 dmas = <&dma 4>, <&dma 4>;
0901 resets = <&ccu RST_BUS_I2S1>;
0902 dma-names = "rx", "tx";
0903 pinctrl-names = "default";
0904 pinctrl-0 = <&i2s1_pins>;
0905 status = "disabled";
0906 };
0907
0908 i2s2: i2s@1c22800 {
0909 #sound-dai-cells = <0>;
0910 compatible = "allwinner,sun8i-a83t-i2s";
0911 reg = <0x01c22800 0x400>;
0912 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
0913 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
0914 clock-names = "apb", "mod";
0915 dmas = <&dma 27>;
0916 resets = <&ccu RST_BUS_I2S2>;
0917 dma-names = "tx";
0918 status = "disabled";
0919 };
0920
0921 pwm: pwm@1c21400 {
0922 compatible = "allwinner,sun8i-a83t-pwm",
0923 "allwinner,sun8i-h3-pwm";
0924 reg = <0x01c21400 0x400>;
0925 clocks = <&osc24M>;
0926 #pwm-cells = <3>;
0927 status = "disabled";
0928 };
0929
0930 uart0: serial@1c28000 {
0931 compatible = "snps,dw-apb-uart";
0932 reg = <0x01c28000 0x400>;
0933 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
0934 reg-shift = <2>;
0935 reg-io-width = <4>;
0936 clocks = <&ccu CLK_BUS_UART0>;
0937 resets = <&ccu RST_BUS_UART0>;
0938 status = "disabled";
0939 };
0940
0941 uart1: serial@1c28400 {
0942 compatible = "snps,dw-apb-uart";
0943 reg = <0x01c28400 0x400>;
0944 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0945 reg-shift = <2>;
0946 reg-io-width = <4>;
0947 clocks = <&ccu CLK_BUS_UART1>;
0948 resets = <&ccu RST_BUS_UART1>;
0949 status = "disabled";
0950 };
0951
0952 uart2: serial@1c28800 {
0953 compatible = "snps,dw-apb-uart";
0954 reg = <0x01c28800 0x400>;
0955 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0956 reg-shift = <2>;
0957 reg-io-width = <4>;
0958 clocks = <&ccu CLK_BUS_UART2>;
0959 resets = <&ccu RST_BUS_UART2>;
0960 status = "disabled";
0961 };
0962
0963 uart3: serial@1c28c00 {
0964 compatible = "snps,dw-apb-uart";
0965 reg = <0x01c28c00 0x400>;
0966 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0967 reg-shift = <2>;
0968 reg-io-width = <4>;
0969 clocks = <&ccu CLK_BUS_UART3>;
0970 resets = <&ccu RST_BUS_UART3>;
0971 status = "disabled";
0972 };
0973
0974 uart4: serial@1c29000 {
0975 compatible = "snps,dw-apb-uart";
0976 reg = <0x01c29000 0x400>;
0977 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0978 reg-shift = <2>;
0979 reg-io-width = <4>;
0980 clocks = <&ccu CLK_BUS_UART4>;
0981 resets = <&ccu RST_BUS_UART4>;
0982 status = "disabled";
0983 };
0984
0985 i2c0: i2c@1c2ac00 {
0986 compatible = "allwinner,sun8i-a83t-i2c",
0987 "allwinner,sun6i-a31-i2c";
0988 reg = <0x01c2ac00 0x400>;
0989 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0990 clocks = <&ccu CLK_BUS_I2C0>;
0991 resets = <&ccu RST_BUS_I2C0>;
0992 pinctrl-names = "default";
0993 pinctrl-0 = <&i2c0_pins>;
0994 status = "disabled";
0995 #address-cells = <1>;
0996 #size-cells = <0>;
0997 };
0998
0999 i2c1: i2c@1c2b000 {
1000 compatible = "allwinner,sun8i-a83t-i2c",
1001 "allwinner,sun6i-a31-i2c";
1002 reg = <0x01c2b000 0x400>;
1003 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1004 clocks = <&ccu CLK_BUS_I2C1>;
1005 resets = <&ccu RST_BUS_I2C1>;
1006 pinctrl-names = "default";
1007 pinctrl-0 = <&i2c1_pins>;
1008 status = "disabled";
1009 #address-cells = <1>;
1010 #size-cells = <0>;
1011 };
1012
1013 i2c2: i2c@1c2b400 {
1014 compatible = "allwinner,sun8i-a83t-i2c",
1015 "allwinner,sun6i-a31-i2c";
1016 reg = <0x01c2b400 0x400>;
1017 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1018 clocks = <&ccu CLK_BUS_I2C2>;
1019 resets = <&ccu RST_BUS_I2C2>;
1020 status = "disabled";
1021 #address-cells = <1>;
1022 #size-cells = <0>;
1023 };
1024
1025 emac: ethernet@1c30000 {
1026 compatible = "allwinner,sun8i-a83t-emac";
1027 syscon = <&syscon>;
1028 reg = <0x01c30000 0x104>;
1029 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1030 interrupt-names = "macirq";
1031 clocks = <&ccu CLK_BUS_EMAC>;
1032 clock-names = "stmmaceth";
1033 resets = <&ccu RST_BUS_EMAC>;
1034 reset-names = "stmmaceth";
1035 status = "disabled";
1036
1037 mdio: mdio {
1038 compatible = "snps,dwmac-mdio";
1039 #address-cells = <1>;
1040 #size-cells = <0>;
1041 };
1042 };
1043
1044 gic: interrupt-controller@1c81000 {
1045 compatible = "arm,gic-400";
1046 reg = <0x01c81000 0x1000>,
1047 <0x01c82000 0x2000>,
1048 <0x01c84000 0x2000>,
1049 <0x01c86000 0x2000>;
1050 interrupt-controller;
1051 #interrupt-cells = <3>;
1052 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1053 };
1054
1055 csi: camera@1cb0000 {
1056 compatible = "allwinner,sun8i-a83t-csi";
1057 reg = <0x01cb0000 0x1000>;
1058 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1059 clocks = <&ccu CLK_BUS_CSI>,
1060 <&ccu CLK_CSI_SCLK>,
1061 <&ccu CLK_DRAM_CSI>;
1062 clock-names = "bus", "mod", "ram";
1063 resets = <&ccu RST_BUS_CSI>;
1064 status = "disabled";
1065 };
1066
1067 hdmi: hdmi@1ee0000 {
1068 compatible = "allwinner,sun8i-a83t-dw-hdmi";
1069 reg = <0x01ee0000 0x10000>;
1070 reg-io-width = <1>;
1071 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1072 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
1073 <&ccu CLK_HDMI>;
1074 clock-names = "iahb", "isfr", "tmds";
1075 resets = <&ccu RST_BUS_HDMI1>;
1076 reset-names = "ctrl";
1077 phys = <&hdmi_phy>;
1078 phy-names = "phy";
1079 pinctrl-names = "default";
1080 pinctrl-0 = <&hdmi_pins>;
1081 status = "disabled";
1082
1083 ports {
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1086
1087 hdmi_in: port@0 {
1088 reg = <0>;
1089
1090 hdmi_in_tcon1: endpoint {
1091 remote-endpoint = <&tcon1_out_hdmi>;
1092 };
1093 };
1094
1095 hdmi_out: port@1 {
1096 reg = <1>;
1097 };
1098 };
1099 };
1100
1101 hdmi_phy: hdmi-phy@1ef0000 {
1102 compatible = "allwinner,sun8i-a83t-hdmi-phy";
1103 reg = <0x01ef0000 0x10000>;
1104 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
1105 clock-names = "bus", "mod";
1106 resets = <&ccu RST_BUS_HDMI0>;
1107 reset-names = "phy";
1108 #phy-cells = <0>;
1109 };
1110
1111 r_intc: interrupt-controller@1f00c00 {
1112 compatible = "allwinner,sun8i-a83t-r-intc",
1113 "allwinner,sun6i-a31-r-intc";
1114 interrupt-controller;
1115 #interrupt-cells = <3>;
1116 reg = <0x01f00c00 0x400>;
1117 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1118 };
1119
1120 r_ccu: clock@1f01400 {
1121 compatible = "allwinner,sun8i-a83t-r-ccu";
1122 reg = <0x01f01400 0x400>;
1123 clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
1124 <&ccu CLK_PLL_PERIPH>;
1125 clock-names = "hosc", "losc", "iosc", "pll-periph";
1126 #clock-cells = <1>;
1127 #reset-cells = <1>;
1128 };
1129
1130 r_cpucfg@1f01c00 {
1131 compatible = "allwinner,sun8i-a83t-r-cpucfg";
1132 reg = <0x1f01c00 0x400>;
1133 };
1134
1135 r_cir: ir@1f02000 {
1136 compatible = "allwinner,sun8i-a83t-ir",
1137 "allwinner,sun6i-a31-ir";
1138 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1139 clock-names = "apb", "ir";
1140 resets = <&r_ccu RST_APB0_IR>;
1141 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1142 reg = <0x01f02000 0x400>;
1143 pinctrl-names = "default";
1144 pinctrl-0 = <&r_cir_pin>;
1145 status = "disabled";
1146 };
1147
1148 r_lradc: lradc@1f03c00 {
1149 compatible = "allwinner,sun8i-a83t-r-lradc";
1150 reg = <0x01f03c00 0x100>;
1151 interrupt-parent = <&r_intc>;
1152 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1153 status = "disabled";
1154 };
1155
1156 r_pio: pinctrl@1f02c00 {
1157 compatible = "allwinner,sun8i-a83t-r-pinctrl";
1158 reg = <0x01f02c00 0x400>;
1159 interrupt-parent = <&r_intc>;
1160 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1161 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
1162 <&osc16Md512>;
1163 clock-names = "apb", "hosc", "losc";
1164 gpio-controller;
1165 #gpio-cells = <3>;
1166 interrupt-controller;
1167 #interrupt-cells = <3>;
1168
1169 r_cir_pin: r-cir-pin {
1170 pins = "PL12";
1171 function = "s_cir_rx";
1172 };
1173
1174 r_rsb_pins: r-rsb-pins {
1175 pins = "PL0", "PL1";
1176 function = "s_rsb";
1177 drive-strength = <20>;
1178 bias-pull-up;
1179 };
1180 };
1181
1182 r_rsb: rsb@1f03400 {
1183 compatible = "allwinner,sun8i-a83t-rsb",
1184 "allwinner,sun8i-a23-rsb";
1185 reg = <0x01f03400 0x400>;
1186 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1187 clocks = <&r_ccu CLK_APB0_RSB>;
1188 clock-frequency = <3000000>;
1189 resets = <&r_ccu RST_APB0_RSB>;
1190 pinctrl-names = "default";
1191 pinctrl-0 = <&r_rsb_pins>;
1192 status = "disabled";
1193 #address-cells = <1>;
1194 #size-cells = <0>;
1195 };
1196
1197 ths: thermal-sensor@1f04000 {
1198 compatible = "allwinner,sun8i-a83t-ths";
1199 reg = <0x01f04000 0x100>;
1200 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1201 nvmem-cells = <&ths_calibration>;
1202 nvmem-cell-names = "calibration";
1203 #thermal-sensor-cells = <1>;
1204 };
1205 };
1206
1207 thermal-zones {
1208 cpu0_thermal: cpu0-thermal {
1209 polling-delay-passive = <0>;
1210 polling-delay = <0>;
1211 thermal-sensors = <&ths 0>;
1212
1213 trips {
1214 cpu0_hot: cpu-hot {
1215 temperature = <80000>;
1216 hysteresis = <2000>;
1217 type = "passive";
1218 };
1219
1220 cpu0_very_hot: cpu-very-hot {
1221 temperature = <100000>;
1222 hysteresis = <0>;
1223 type = "critical";
1224 };
1225 };
1226
1227 cooling-maps {
1228 cpu-hot-limit {
1229 trip = <&cpu0_hot>;
1230 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1231 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1232 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1233 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1234 };
1235 };
1236 };
1237
1238 cpu1_thermal: cpu1-thermal {
1239 polling-delay-passive = <0>;
1240 polling-delay = <0>;
1241 thermal-sensors = <&ths 1>;
1242
1243 trips {
1244 cpu1_hot: cpu-hot {
1245 temperature = <80000>;
1246 hysteresis = <2000>;
1247 type = "passive";
1248 };
1249
1250 cpu1_very_hot: cpu-very-hot {
1251 temperature = <100000>;
1252 hysteresis = <0>;
1253 type = "critical";
1254 };
1255 };
1256
1257 cooling-maps {
1258 cpu-hot-limit {
1259 trip = <&cpu1_hot>;
1260 cooling-device = <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1261 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1262 <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1263 <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1264 };
1265 };
1266 };
1267
1268 gpu_thermal: gpu-thermal {
1269 polling-delay-passive = <0>;
1270 polling-delay = <0>;
1271 thermal-sensors = <&ths 2>;
1272 };
1273 };
1274 };
