0001 /*
0002 * Copyright 2014 Chen-Yu Tsai
0003 *
0004 * Chen-Yu Tsai <wens@csie.org>
0005 *
0006 * This file is dual-licensed: you can use it either under the terms
0007 * of the GPL or the X11 license, at your option. Note that this dual
0008 * licensing only applies to this file, and not this project as a
0009 * whole.
0010 *
0011 * a) This file is free software; you can redistribute it and/or
0012 * modify it under the terms of the GNU General Public License as
0013 * published by the Free Software Foundation; either version 2 of the
0014 * License, or (at your option) any later version.
0015 *
0016 * This file is distributed in the hope that it will be useful,
0017 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0019 * GNU General Public License for more details.
0020 *
0021 * Or, alternatively,
0022 *
0023 * b) Permission is hereby granted, free of charge, to any person
0024 * obtaining a copy of this software and associated documentation
0025 * files (the "Software"), to deal in the Software without
0026 * restriction, including without limitation the rights to use,
0027 * copy, modify, merge, publish, distribute, sublicense, and/or
0028 * sell copies of the Software, and to permit persons to whom the
0029 * Software is furnished to do so, subject to the following
0030 * conditions:
0031 *
0032 * The above copyright notice and this permission notice shall be
0033 * included in all copies or substantial portions of the Software.
0034 *
0035 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0036 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0037 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0038 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0039 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0040 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0041 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0042 * OTHER DEALINGS IN THE SOFTWARE.
0043 */
0044
0045 #include "sun8i-a23-a33.dtsi"
0046 #include <dt-bindings/thermal/thermal.h>
0047
0048 / {
0049 cpu0_opp_table: opp-table-cpu {
0050 compatible = "operating-points-v2";
0051 opp-shared;
0052
0053 opp-120000000 {
0054 opp-hz = /bits/ 64 <120000000>;
0055 opp-microvolt = <1040000>;
0056 clock-latency-ns = <244144>; /* 8 32k periods */
0057 };
0058
0059 opp-240000000 {
0060 opp-hz = /bits/ 64 <240000000>;
0061 opp-microvolt = <1040000>;
0062 clock-latency-ns = <244144>; /* 8 32k periods */
0063 };
0064
0065 opp-312000000 {
0066 opp-hz = /bits/ 64 <312000000>;
0067 opp-microvolt = <1040000>;
0068 clock-latency-ns = <244144>; /* 8 32k periods */
0069 };
0070
0071 opp-408000000 {
0072 opp-hz = /bits/ 64 <408000000>;
0073 opp-microvolt = <1040000>;
0074 clock-latency-ns = <244144>; /* 8 32k periods */
0075 };
0076
0077 opp-480000000 {
0078 opp-hz = /bits/ 64 <480000000>;
0079 opp-microvolt = <1040000>;
0080 clock-latency-ns = <244144>; /* 8 32k periods */
0081 };
0082
0083 opp-504000000 {
0084 opp-hz = /bits/ 64 <504000000>;
0085 opp-microvolt = <1040000>;
0086 clock-latency-ns = <244144>; /* 8 32k periods */
0087 };
0088
0089 opp-600000000 {
0090 opp-hz = /bits/ 64 <600000000>;
0091 opp-microvolt = <1040000>;
0092 clock-latency-ns = <244144>; /* 8 32k periods */
0093 };
0094
0095 opp-648000000 {
0096 opp-hz = /bits/ 64 <648000000>;
0097 opp-microvolt = <1040000>;
0098 clock-latency-ns = <244144>; /* 8 32k periods */
0099 };
0100
0101 opp-720000000 {
0102 opp-hz = /bits/ 64 <720000000>;
0103 opp-microvolt = <1100000>;
0104 clock-latency-ns = <244144>; /* 8 32k periods */
0105 };
0106
0107 opp-816000000 {
0108 opp-hz = /bits/ 64 <816000000>;
0109 opp-microvolt = <1100000>;
0110 clock-latency-ns = <244144>; /* 8 32k periods */
0111 };
0112
0113 opp-912000000 {
0114 opp-hz = /bits/ 64 <912000000>;
0115 opp-microvolt = <1200000>;
0116 clock-latency-ns = <244144>; /* 8 32k periods */
0117 };
0118
0119 opp-1008000000 {
0120 opp-hz = /bits/ 64 <1008000000>;
0121 opp-microvolt = <1200000>;
0122 clock-latency-ns = <244144>; /* 8 32k periods */
0123 };
0124 };
0125
0126 cpus {
0127 cpu@0 {
0128 clocks = <&ccu CLK_CPUX>;
0129 clock-names = "cpu";
0130 operating-points-v2 = <&cpu0_opp_table>;
0131 #cooling-cells = <2>;
0132 };
0133
0134 cpu1: cpu@1 {
0135 clocks = <&ccu CLK_CPUX>;
0136 clock-names = "cpu";
0137 operating-points-v2 = <&cpu0_opp_table>;
0138 #cooling-cells = <2>;
0139 };
0140
0141 cpu2: cpu@2 {
0142 compatible = "arm,cortex-a7";
0143 device_type = "cpu";
0144 reg = <2>;
0145 clocks = <&ccu CLK_CPUX>;
0146 clock-names = "cpu";
0147 operating-points-v2 = <&cpu0_opp_table>;
0148 #cooling-cells = <2>;
0149 };
0150
0151 cpu3: cpu@3 {
0152 compatible = "arm,cortex-a7";
0153 device_type = "cpu";
0154 reg = <3>;
0155 clocks = <&ccu CLK_CPUX>;
0156 clock-names = "cpu";
0157 operating-points-v2 = <&cpu0_opp_table>;
0158 #cooling-cells = <2>;
0159 };
0160 };
0161
0162 iio-hwmon {
0163 compatible = "iio-hwmon";
0164 io-channels = <&ths>;
0165 };
0166
0167 mali_opp_table: opp-table-gpu {
0168 compatible = "operating-points-v2";
0169
0170 opp-144000000 {
0171 opp-hz = /bits/ 64 <144000000>;
0172 };
0173
0174 opp-240000000 {
0175 opp-hz = /bits/ 64 <240000000>;
0176 };
0177
0178 opp-384000000 {
0179 opp-hz = /bits/ 64 <384000000>;
0180 };
0181 };
0182
0183 sound: sound {
0184 compatible = "simple-audio-card";
0185 simple-audio-card,name = "sun8i-a33-audio";
0186 simple-audio-card,format = "i2s";
0187 simple-audio-card,frame-master = <&link_codec>;
0188 simple-audio-card,bitclock-master = <&link_codec>;
0189 simple-audio-card,mclk-fs = <128>;
0190 simple-audio-card,aux-devs = <&codec_analog>;
0191 simple-audio-card,routing =
0192 "Left DAC", "DACL",
0193 "Right DAC", "DACR";
0194 status = "disabled";
0195
0196 simple-audio-card,cpu {
0197 sound-dai = <&dai>;
0198 };
0199
0200 link_codec: simple-audio-card,codec {
0201 sound-dai = <&codec 0>;
0202 };
0203 };
0204
0205 soc {
0206 video-codec@1c0e000 {
0207 compatible = "allwinner,sun8i-a33-video-engine";
0208 reg = <0x01c0e000 0x1000>;
0209 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
0210 <&ccu CLK_DRAM_VE>;
0211 clock-names = "ahb", "mod", "ram";
0212 resets = <&ccu RST_BUS_VE>;
0213 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
0214 allwinner,sram = <&ve_sram 1>;
0215 };
0216
0217 crypto: crypto-engine@1c15000 {
0218 compatible = "allwinner,sun8i-a33-crypto";
0219 reg = <0x01c15000 0x1000>;
0220 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
0221 clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
0222 clock-names = "ahb", "mod";
0223 resets = <&ccu RST_BUS_SS>;
0224 reset-names = "ahb";
0225 };
0226
0227 dai: dai@1c22c00 {
0228 #sound-dai-cells = <0>;
0229 compatible = "allwinner,sun6i-a31-i2s";
0230 reg = <0x01c22c00 0x200>;
0231 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0232 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
0233 clock-names = "apb", "mod";
0234 resets = <&ccu RST_BUS_CODEC>;
0235 dmas = <&dma 15>, <&dma 15>;
0236 dma-names = "rx", "tx";
0237 status = "disabled";
0238 };
0239
0240 codec: codec@1c22e00 {
0241 #sound-dai-cells = <1>;
0242 compatible = "allwinner,sun8i-a33-codec";
0243 reg = <0x01c22e00 0x400>;
0244 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0245 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
0246 clock-names = "bus", "mod";
0247 status = "disabled";
0248 };
0249
0250 ths: ths@1c25000 {
0251 compatible = "allwinner,sun8i-a33-ths";
0252 reg = <0x01c25000 0x100>;
0253 #thermal-sensor-cells = <0>;
0254 #io-channel-cells = <0>;
0255 };
0256
0257 dsi: dsi@1ca0000 {
0258 compatible = "allwinner,sun6i-a31-mipi-dsi";
0259 reg = <0x01ca0000 0x1000>;
0260 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0261 clocks = <&ccu CLK_BUS_MIPI_DSI>,
0262 <&ccu CLK_DSI_SCLK>;
0263 clock-names = "bus", "mod";
0264 resets = <&ccu RST_BUS_MIPI_DSI>;
0265 phys = <&dphy>;
0266 phy-names = "dphy";
0267 status = "disabled";
0268 #address-cells = <1>;
0269 #size-cells = <0>;
0270
0271 port {
0272 dsi_in_tcon0: endpoint {
0273 remote-endpoint = <&tcon0_out_dsi>;
0274 };
0275 };
0276 };
0277
0278 dphy: d-phy@1ca1000 {
0279 compatible = "allwinner,sun6i-a31-mipi-dphy";
0280 reg = <0x01ca1000 0x1000>;
0281 clocks = <&ccu CLK_BUS_MIPI_DSI>,
0282 <&ccu CLK_DSI_DPHY>;
0283 clock-names = "bus", "mod";
0284 resets = <&ccu RST_BUS_MIPI_DSI>;
0285 status = "disabled";
0286 #phy-cells = <0>;
0287 };
0288 };
0289
0290 thermal-zones {
0291 cpu-thermal {
0292 /* milliseconds */
0293 polling-delay-passive = <250>;
0294 polling-delay = <1000>;
0295 thermal-sensors = <&ths>;
0296
0297 cooling-maps {
0298 map0 {
0299 trip = <&cpu_alert0>;
0300 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0301 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0302 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0303 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0304 };
0305 map1 {
0306 trip = <&cpu_alert1>;
0307 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0308 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0309 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0310 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0311 };
0312
0313 map2 {
0314 trip = <&gpu_alert0>;
0315 cooling-device = <&mali 1 THERMAL_NO_LIMIT>;
0316 };
0317
0318 map3 {
0319 trip = <&gpu_alert1>;
0320 cooling-device = <&mali 2 THERMAL_NO_LIMIT>;
0321 };
0322 };
0323
0324 trips {
0325 cpu_alert0: cpu_alert0 {
0326 /* milliCelsius */
0327 temperature = <75000>;
0328 hysteresis = <2000>;
0329 type = "passive";
0330 };
0331
0332 gpu_alert0: gpu_alert0 {
0333 /* milliCelsius */
0334 temperature = <85000>;
0335 hysteresis = <2000>;
0336 type = "passive";
0337 };
0338
0339 cpu_alert1: cpu_alert1 {
0340 /* milliCelsius */
0341 temperature = <90000>;
0342 hysteresis = <2000>;
0343 type = "hot";
0344 };
0345
0346 gpu_alert1: gpu_alert1 {
0347 /* milliCelsius */
0348 temperature = <95000>;
0349 hysteresis = <2000>;
0350 type = "hot";
0351 };
0352
0353 cpu_crit: cpu_crit {
0354 /* milliCelsius */
0355 temperature = <110000>;
0356 hysteresis = <2000>;
0357 type = "critical";
0358 };
0359 };
0360 };
0361 };
0362 };
0363
0364 &be0 {
0365 compatible = "allwinner,sun8i-a33-display-backend";
0366 /* A33 has an extra "SAT" module packed inside the display backend */
0367 reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
0368 reg-names = "be", "sat";
0369 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
0370 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
0371 clock-names = "ahb", "mod",
0372 "ram", "sat";
0373 resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
0374 reset-names = "be", "sat";
0375 };
0376
0377 &ccu {
0378 compatible = "allwinner,sun8i-a33-ccu";
0379 };
0380
0381 &de {
0382 compatible = "allwinner,sun8i-a33-display-engine";
0383 };
0384
0385 &drc0 {
0386 compatible = "allwinner,sun8i-a33-drc";
0387 };
0388
0389 &fe0 {
0390 compatible = "allwinner,sun8i-a33-display-frontend";
0391 };
0392
0393 &mali {
0394 operating-points-v2 = <&mali_opp_table>;
0395 };
0396
0397 &pio {
0398 compatible = "allwinner,sun8i-a33-pinctrl";
0399 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
0400 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0401
0402 uart0_pb_pins: uart0-pb-pins {
0403 pins = "PB0", "PB1";
0404 function = "uart0";
0405 };
0406
0407 };
0408
0409 &tcon0 {
0410 compatible = "allwinner,sun8i-a33-tcon";
0411 };
0412
0413 &tcon0_out {
0414 #address-cells = <1>;
0415 #size-cells = <0>;
0416
0417 tcon0_out_dsi: endpoint@1 {
0418 reg = <1>;
0419 remote-endpoint = <&dsi_in_tcon0>;
0420 };
0421 };
0422
0423 &usb_otg {
0424 compatible = "allwinner,sun8i-a33-musb";
0425 };
0426
0427 &usbphy {
0428 compatible = "allwinner,sun8i-a33-usb-phy";
0429 reg = <0x01c19400 0x14>, <0x01c1a800 0x4>;
0430 reg-names = "phy_ctrl", "pmu1";
0431 };
