0001 /*
0002 * Copyright 2014 Chen-Yu Tsai
0003 *
0004 * Chen-Yu Tsai <wens@csie.org>
0005 *
0006 * This file is dual-licensed: you can use it either under the terms
0007 * of the GPL or the X11 license, at your option. Note that this dual
0008 * licensing only applies to this file, and not this project as a
0009 * whole.
0010 *
0011 * a) This file is free software; you can redistribute it and/or
0012 * modify it under the terms of the GNU General Public License as
0013 * published by the Free Software Foundation; either version 2 of the
0014 * License, or (at your option) any later version.
0015 *
0016 * This file is distributed in the hope that it will be useful,
0017 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0019 * GNU General Public License for more details.
0020 *
0021 * Or, alternatively,
0022 *
0023 * b) Permission is hereby granted, free of charge, to any person
0024 * obtaining a copy of this software and associated documentation
0025 * files (the "Software"), to deal in the Software without
0026 * restriction, including without limitation the rights to use,
0027 * copy, modify, merge, publish, distribute, sublicense, and/or
0028 * sell copies of the Software, and to permit persons to whom the
0029 * Software is furnished to do so, subject to the following
0030 * conditions:
0031 *
0032 * The above copyright notice and this permission notice shall be
0033 * included in all copies or substantial portions of the Software.
0034 *
0035 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0036 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0037 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0038 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0039 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0040 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0041 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0042 * OTHER DEALINGS IN THE SOFTWARE.
0043 */
0044
0045 #include <dt-bindings/interrupt-controller/arm-gic.h>
0046
0047 #include <dt-bindings/clock/sun6i-rtc.h>
0048 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
0049 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
0050
0051 / {
0052 interrupt-parent = <&gic>;
0053 #address-cells = <1>;
0054 #size-cells = <1>;
0055
0056 chosen {
0057 #address-cells = <1>;
0058 #size-cells = <1>;
0059 ranges;
0060
0061 simplefb_lcd: framebuffer-lcd0 {
0062 compatible = "allwinner,simple-framebuffer",
0063 "simple-framebuffer";
0064 allwinner,pipeline = "de_be0-lcd0";
0065 clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
0066 <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
0067 <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
0068 status = "disabled";
0069 };
0070 };
0071
0072 de: display-engine {
0073 /* compatible gets set in SoC specific dtsi file */
0074 allwinner,pipelines = <&fe0>;
0075 status = "disabled";
0076 };
0077
0078 timer {
0079 compatible = "arm,armv7-timer";
0080 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0081 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0082 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0083 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0084 clock-frequency = <24000000>;
0085 arm,cpu-registers-not-fw-configured;
0086 };
0087
0088 cpus {
0089 enable-method = "allwinner,sun8i-a23";
0090 #address-cells = <1>;
0091 #size-cells = <0>;
0092
0093 cpu0: cpu@0 {
0094 compatible = "arm,cortex-a7";
0095 device_type = "cpu";
0096 reg = <0>;
0097 };
0098
0099 cpu@1 {
0100 compatible = "arm,cortex-a7";
0101 device_type = "cpu";
0102 reg = <1>;
0103 };
0104 };
0105
0106 clocks {
0107 #address-cells = <1>;
0108 #size-cells = <1>;
0109 ranges;
0110
0111 osc24M: osc24M_clk {
0112 #clock-cells = <0>;
0113 compatible = "fixed-clock";
0114 clock-frequency = <24000000>;
0115 clock-accuracy = <50000>;
0116 clock-output-names = "osc24M";
0117 };
0118
0119 ext_osc32k: ext_osc32k_clk {
0120 #clock-cells = <0>;
0121 compatible = "fixed-clock";
0122 clock-frequency = <32768>;
0123 clock-accuracy = <50000>;
0124 clock-output-names = "ext-osc32k";
0125 };
0126 };
0127
0128 soc {
0129 compatible = "simple-bus";
0130 #address-cells = <1>;
0131 #size-cells = <1>;
0132 ranges;
0133
0134 system-control@1c00000 {
0135 compatible = "allwinner,sun8i-a23-system-control";
0136 reg = <0x01c00000 0x30>;
0137 #address-cells = <1>;
0138 #size-cells = <1>;
0139 ranges;
0140
0141 sram_c: sram@1d00000 {
0142 compatible = "mmio-sram";
0143 reg = <0x01d00000 0x80000>;
0144 #address-cells = <1>;
0145 #size-cells = <1>;
0146 ranges = <0 0x01d00000 0x80000>;
0147
0148 ve_sram: sram-section@0 {
0149 compatible = "allwinner,sun8i-a23-sram-c1",
0150 "allwinner,sun4i-a10-sram-c1";
0151 reg = <0x000000 0x80000>;
0152 };
0153 };
0154 };
0155
0156 dma: dma-controller@1c02000 {
0157 compatible = "allwinner,sun8i-a23-dma";
0158 reg = <0x01c02000 0x1000>;
0159 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0160 clocks = <&ccu CLK_BUS_DMA>;
0161 resets = <&ccu RST_BUS_DMA>;
0162 #dma-cells = <1>;
0163 };
0164
0165 nfc: nand-controller@1c03000 {
0166 compatible = "allwinner,sun8i-a23-nand-controller";
0167 reg = <0x01c03000 0x1000>;
0168 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
0169 clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
0170 clock-names = "ahb", "mod";
0171 resets = <&ccu RST_BUS_NAND>;
0172 reset-names = "ahb";
0173 dmas = <&dma 5>;
0174 dma-names = "rxtx";
0175 pinctrl-names = "default";
0176 pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
0177 status = "disabled";
0178 #address-cells = <1>;
0179 #size-cells = <0>;
0180 };
0181
0182 tcon0: lcd-controller@1c0c000 {
0183 /* compatible gets set in SoC specific dtsi file */
0184 reg = <0x01c0c000 0x1000>;
0185 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0186 dmas = <&dma 12>;
0187 clocks = <&ccu CLK_BUS_LCD>,
0188 <&ccu CLK_LCD_CH0>,
0189 <&ccu 13>;
0190 clock-names = "ahb",
0191 "tcon-ch0",
0192 "lvds-alt";
0193 clock-output-names = "tcon-pixel-clock";
0194 #clock-cells = <0>;
0195 resets = <&ccu RST_BUS_LCD>,
0196 <&ccu RST_BUS_LVDS>;
0197 reset-names = "lcd",
0198 "lvds";
0199 status = "disabled";
0200
0201 ports {
0202 #address-cells = <1>;
0203 #size-cells = <0>;
0204
0205 tcon0_in: port@0 {
0206 reg = <0>;
0207
0208 tcon0_in_drc0: endpoint {
0209 remote-endpoint = <&drc0_out_tcon0>;
0210 };
0211 };
0212
0213 tcon0_out: port@1 {
0214 reg = <1>;
0215 };
0216 };
0217 };
0218
0219 mmc0: mmc@1c0f000 {
0220 compatible = "allwinner,sun7i-a20-mmc";
0221 reg = <0x01c0f000 0x1000>;
0222 clocks = <&ccu CLK_BUS_MMC0>,
0223 <&ccu CLK_MMC0>,
0224 <&ccu CLK_MMC0_OUTPUT>,
0225 <&ccu CLK_MMC0_SAMPLE>;
0226 clock-names = "ahb",
0227 "mmc",
0228 "output",
0229 "sample";
0230 resets = <&ccu RST_BUS_MMC0>;
0231 reset-names = "ahb";
0232 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0233 pinctrl-names = "default";
0234 pinctrl-0 = <&mmc0_pins>;
0235 status = "disabled";
0236 #address-cells = <1>;
0237 #size-cells = <0>;
0238 };
0239
0240 mmc1: mmc@1c10000 {
0241 compatible = "allwinner,sun7i-a20-mmc";
0242 reg = <0x01c10000 0x1000>;
0243 clocks = <&ccu CLK_BUS_MMC1>,
0244 <&ccu CLK_MMC1>,
0245 <&ccu CLK_MMC1_OUTPUT>,
0246 <&ccu CLK_MMC1_SAMPLE>;
0247 clock-names = "ahb",
0248 "mmc",
0249 "output",
0250 "sample";
0251 resets = <&ccu RST_BUS_MMC1>;
0252 reset-names = "ahb";
0253 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0254 status = "disabled";
0255 #address-cells = <1>;
0256 #size-cells = <0>;
0257 };
0258
0259 mmc2: mmc@1c11000 {
0260 compatible = "allwinner,sun7i-a20-mmc";
0261 reg = <0x01c11000 0x1000>;
0262 clocks = <&ccu CLK_BUS_MMC2>,
0263 <&ccu CLK_MMC2>,
0264 <&ccu CLK_MMC2_OUTPUT>,
0265 <&ccu CLK_MMC2_SAMPLE>;
0266 clock-names = "ahb",
0267 "mmc",
0268 "output",
0269 "sample";
0270 resets = <&ccu RST_BUS_MMC2>;
0271 reset-names = "ahb";
0272 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0273 status = "disabled";
0274 #address-cells = <1>;
0275 #size-cells = <0>;
0276 };
0277
0278 usb_otg: usb@1c19000 {
0279 /* compatible gets set in SoC specific dtsi file */
0280 reg = <0x01c19000 0x0400>;
0281 clocks = <&ccu CLK_BUS_OTG>;
0282 resets = <&ccu RST_BUS_OTG>;
0283 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0284 interrupt-names = "mc";
0285 phys = <&usbphy 0>;
0286 phy-names = "usb";
0287 extcon = <&usbphy 0>;
0288 dr_mode = "otg";
0289 status = "disabled";
0290 };
0291
0292 usbphy: phy@1c19400 {
0293 /*
0294 * compatible and address regions get set in
0295 * SoC specific dtsi file
0296 */
0297 clocks = <&ccu CLK_USB_PHY0>,
0298 <&ccu CLK_USB_PHY1>;
0299 clock-names = "usb0_phy",
0300 "usb1_phy";
0301 resets = <&ccu RST_USB_PHY0>,
0302 <&ccu RST_USB_PHY1>;
0303 reset-names = "usb0_reset",
0304 "usb1_reset";
0305 status = "disabled";
0306 #phy-cells = <1>;
0307 };
0308
0309 ehci0: usb@1c1a000 {
0310 compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
0311 reg = <0x01c1a000 0x100>;
0312 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0313 clocks = <&ccu CLK_BUS_EHCI>;
0314 resets = <&ccu RST_BUS_EHCI>;
0315 phys = <&usbphy 1>;
0316 phy-names = "usb";
0317 status = "disabled";
0318 };
0319
0320 ohci0: usb@1c1a400 {
0321 compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
0322 reg = <0x01c1a400 0x100>;
0323 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0324 clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
0325 resets = <&ccu RST_BUS_OHCI>;
0326 phys = <&usbphy 1>;
0327 phy-names = "usb";
0328 status = "disabled";
0329 };
0330
0331 ccu: clock@1c20000 {
0332 reg = <0x01c20000 0x400>;
0333 clocks = <&osc24M>, <&rtc CLK_OSC32K>;
0334 clock-names = "hosc", "losc";
0335 #clock-cells = <1>;
0336 #reset-cells = <1>;
0337 };
0338
0339 pio: pinctrl@1c20800 {
0340 /* compatible gets set in SoC specific dtsi file */
0341 reg = <0x01c20800 0x400>;
0342 interrupt-parent = <&r_intc>;
0343 /* interrupts get set in SoC specific dtsi file */
0344 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
0345 <&rtc CLK_OSC32K>;
0346 clock-names = "apb", "hosc", "losc";
0347 gpio-controller;
0348 interrupt-controller;
0349 #interrupt-cells = <3>;
0350 #gpio-cells = <3>;
0351
0352 i2c0_pins: i2c0-pins {
0353 pins = "PH2", "PH3";
0354 function = "i2c0";
0355 };
0356
0357 i2c1_pins: i2c1-pins {
0358 pins = "PH4", "PH5";
0359 function = "i2c1";
0360 };
0361
0362 i2c2_pins: i2c2-pins {
0363 pins = "PE12", "PE13";
0364 function = "i2c2";
0365 };
0366
0367 lcd_rgb666_pins: lcd-rgb666-pins {
0368 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
0369 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
0370 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
0371 "PD24", "PD25", "PD26", "PD27";
0372 function = "lcd0";
0373 };
0374
0375 mmc0_pins: mmc0-pins {
0376 pins = "PF0", "PF1", "PF2",
0377 "PF3", "PF4", "PF5";
0378 function = "mmc0";
0379 drive-strength = <30>;
0380 bias-pull-up;
0381 };
0382
0383 mmc1_pg_pins: mmc1-pg-pins {
0384 pins = "PG0", "PG1", "PG2",
0385 "PG3", "PG4", "PG5";
0386 function = "mmc1";
0387 drive-strength = <30>;
0388 bias-pull-up;
0389 };
0390
0391 mmc2_8bit_pins: mmc2-8bit-pins {
0392 pins = "PC5", "PC6", "PC8",
0393 "PC9", "PC10", "PC11",
0394 "PC12", "PC13", "PC14",
0395 "PC15", "PC16";
0396 function = "mmc2";
0397 drive-strength = <30>;
0398 bias-pull-up;
0399 };
0400
0401 nand_pins: nand-pins {
0402 pins = "PC0", "PC1", "PC2", "PC5",
0403 "PC8", "PC9", "PC10", "PC11",
0404 "PC12", "PC13", "PC14", "PC15";
0405 function = "nand0";
0406 };
0407
0408 nand_cs0_pin: nand-cs0-pin {
0409 pins = "PC4";
0410 function = "nand0";
0411 bias-pull-up;
0412 };
0413
0414 nand_cs1_pin: nand-cs1-pin {
0415 pins = "PC3";
0416 function = "nand0";
0417 bias-pull-up;
0418 };
0419
0420 nand_rb0_pin: nand-rb0-pin {
0421 pins = "PC6";
0422 function = "nand0";
0423 bias-pull-up;
0424 };
0425
0426 nand_rb1_pin: nand-rb1-pin {
0427 pins = "PC7";
0428 function = "nand0";
0429 bias-pull-up;
0430 };
0431
0432 pwm0_pin: pwm0-pin {
0433 pins = "PH0";
0434 function = "pwm0";
0435 };
0436
0437 uart0_pf_pins: uart0-pf-pins {
0438 pins = "PF2", "PF4";
0439 function = "uart0";
0440 };
0441
0442 uart1_pg_pins: uart1-pg-pins {
0443 pins = "PG6", "PG7";
0444 function = "uart1";
0445 };
0446
0447 uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins {
0448 pins = "PG8", "PG9";
0449 function = "uart1";
0450 };
0451 };
0452
0453 timer@1c20c00 {
0454 compatible = "allwinner,sun8i-a23-timer";
0455 reg = <0x01c20c00 0xa0>;
0456 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0457 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0458 clocks = <&osc24M>;
0459 };
0460
0461 wdt0: watchdog@1c20ca0 {
0462 compatible = "allwinner,sun6i-a31-wdt";
0463 reg = <0x01c20ca0 0x20>;
0464 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0465 clocks = <&osc24M>;
0466 };
0467
0468 pwm: pwm@1c21400 {
0469 compatible = "allwinner,sun7i-a20-pwm";
0470 reg = <0x01c21400 0xc>;
0471 clocks = <&osc24M>;
0472 #pwm-cells = <3>;
0473 status = "disabled";
0474 };
0475
0476 lradc: lradc@1c22800 {
0477 compatible = "allwinner,sun4i-a10-lradc-keys";
0478 reg = <0x01c22800 0x100>;
0479 interrupt-parent = <&r_intc>;
0480 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0481 status = "disabled";
0482 };
0483
0484 uart0: serial@1c28000 {
0485 compatible = "snps,dw-apb-uart";
0486 reg = <0x01c28000 0x400>;
0487 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
0488 reg-shift = <2>;
0489 reg-io-width = <4>;
0490 clocks = <&ccu CLK_BUS_UART0>;
0491 resets = <&ccu RST_BUS_UART0>;
0492 dmas = <&dma 6>, <&dma 6>;
0493 dma-names = "rx", "tx";
0494 status = "disabled";
0495 };
0496
0497 uart1: serial@1c28400 {
0498 compatible = "snps,dw-apb-uart";
0499 reg = <0x01c28400 0x400>;
0500 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0501 reg-shift = <2>;
0502 reg-io-width = <4>;
0503 clocks = <&ccu CLK_BUS_UART1>;
0504 resets = <&ccu RST_BUS_UART1>;
0505 dmas = <&dma 7>, <&dma 7>;
0506 dma-names = "rx", "tx";
0507 status = "disabled";
0508 };
0509
0510 uart2: serial@1c28800 {
0511 compatible = "snps,dw-apb-uart";
0512 reg = <0x01c28800 0x400>;
0513 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0514 reg-shift = <2>;
0515 reg-io-width = <4>;
0516 clocks = <&ccu CLK_BUS_UART2>;
0517 resets = <&ccu RST_BUS_UART2>;
0518 dmas = <&dma 8>, <&dma 8>;
0519 dma-names = "rx", "tx";
0520 status = "disabled";
0521 };
0522
0523 uart3: serial@1c28c00 {
0524 compatible = "snps,dw-apb-uart";
0525 reg = <0x01c28c00 0x400>;
0526 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0527 reg-shift = <2>;
0528 reg-io-width = <4>;
0529 clocks = <&ccu CLK_BUS_UART3>;
0530 resets = <&ccu RST_BUS_UART3>;
0531 dmas = <&dma 9>, <&dma 9>;
0532 dma-names = "rx", "tx";
0533 status = "disabled";
0534 };
0535
0536 uart4: serial@1c29000 {
0537 compatible = "snps,dw-apb-uart";
0538 reg = <0x01c29000 0x400>;
0539 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0540 reg-shift = <2>;
0541 reg-io-width = <4>;
0542 clocks = <&ccu CLK_BUS_UART4>;
0543 resets = <&ccu RST_BUS_UART4>;
0544 dmas = <&dma 10>, <&dma 10>;
0545 dma-names = "rx", "tx";
0546 status = "disabled";
0547 };
0548
0549 i2c0: i2c@1c2ac00 {
0550 compatible = "allwinner,sun6i-a31-i2c";
0551 reg = <0x01c2ac00 0x400>;
0552 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0553 clocks = <&ccu CLK_BUS_I2C0>;
0554 resets = <&ccu RST_BUS_I2C0>;
0555 pinctrl-names = "default";
0556 pinctrl-0 = <&i2c0_pins>;
0557 status = "disabled";
0558 #address-cells = <1>;
0559 #size-cells = <0>;
0560 };
0561
0562 i2c1: i2c@1c2b000 {
0563 compatible = "allwinner,sun6i-a31-i2c";
0564 reg = <0x01c2b000 0x400>;
0565 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0566 clocks = <&ccu CLK_BUS_I2C1>;
0567 resets = <&ccu RST_BUS_I2C1>;
0568 pinctrl-names = "default";
0569 pinctrl-0 = <&i2c1_pins>;
0570 status = "disabled";
0571 #address-cells = <1>;
0572 #size-cells = <0>;
0573 };
0574
0575 i2c2: i2c@1c2b400 {
0576 compatible = "allwinner,sun6i-a31-i2c";
0577 reg = <0x01c2b400 0x400>;
0578 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0579 clocks = <&ccu CLK_BUS_I2C2>;
0580 resets = <&ccu RST_BUS_I2C2>;
0581 pinctrl-names = "default";
0582 pinctrl-0 = <&i2c2_pins>;
0583 status = "disabled";
0584 #address-cells = <1>;
0585 #size-cells = <0>;
0586 };
0587
0588 mali: gpu@1c40000 {
0589 compatible = "allwinner,sun8i-a23-mali",
0590 "allwinner,sun7i-a20-mali", "arm,mali-400";
0591 reg = <0x01c40000 0x10000>;
0592 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
0593 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
0594 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
0595 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
0596 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
0597 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
0598 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
0599 interrupt-names = "gp",
0600 "gpmmu",
0601 "pp0",
0602 "ppmmu0",
0603 "pp1",
0604 "ppmmu1",
0605 "pmu";
0606 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
0607 clock-names = "bus", "core";
0608 resets = <&ccu RST_BUS_GPU>;
0609 #cooling-cells = <2>;
0610
0611 assigned-clocks = <&ccu CLK_GPU>;
0612 assigned-clock-rates = <384000000>;
0613 };
0614
0615 gic: interrupt-controller@1c81000 {
0616 compatible = "arm,gic-400";
0617 reg = <0x01c81000 0x1000>,
0618 <0x01c82000 0x2000>,
0619 <0x01c84000 0x2000>,
0620 <0x01c86000 0x2000>;
0621 interrupt-controller;
0622 #interrupt-cells = <3>;
0623 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0624 };
0625
0626 fe0: display-frontend@1e00000 {
0627 /* compatible gets set in SoC specific dtsi file */
0628 reg = <0x01e00000 0x20000>;
0629 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
0630 clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
0631 <&ccu CLK_DRAM_DE_FE>;
0632 clock-names = "ahb", "mod",
0633 "ram";
0634 resets = <&ccu RST_BUS_DE_FE>;
0635
0636 ports {
0637 #address-cells = <1>;
0638 #size-cells = <0>;
0639
0640 fe0_out: port@1 {
0641 reg = <1>;
0642
0643 fe0_out_be0: endpoint {
0644 remote-endpoint = <&be0_in_fe0>;
0645 };
0646 };
0647 };
0648 };
0649
0650 be0: display-backend@1e60000 {
0651 /* compatible gets set in SoC specific dtsi file */
0652 reg = <0x01e60000 0x10000>;
0653 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
0654 clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
0655 <&ccu CLK_DRAM_DE_BE>;
0656 clock-names = "ahb", "mod",
0657 "ram";
0658 resets = <&ccu RST_BUS_DE_BE>;
0659
0660 ports {
0661 #address-cells = <1>;
0662 #size-cells = <0>;
0663
0664 be0_in: port@0 {
0665 reg = <0>;
0666
0667 be0_in_fe0: endpoint {
0668 remote-endpoint = <&fe0_out_be0>;
0669 };
0670 };
0671
0672 be0_out: port@1 {
0673 reg = <1>;
0674
0675 be0_out_drc0: endpoint {
0676 remote-endpoint = <&drc0_in_be0>;
0677 };
0678 };
0679 };
0680 };
0681
0682 drc0: drc@1e70000 {
0683 /* compatible gets set in SoC specific dtsi file */
0684 reg = <0x01e70000 0x10000>;
0685 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0686 clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
0687 <&ccu CLK_DRAM_DRC>;
0688 clock-names = "ahb", "mod", "ram";
0689 resets = <&ccu RST_BUS_DRC>;
0690
0691 ports {
0692 #address-cells = <1>;
0693 #size-cells = <0>;
0694
0695 drc0_in: port@0 {
0696 reg = <0>;
0697
0698 drc0_in_be0: endpoint {
0699 remote-endpoint = <&be0_out_drc0>;
0700 };
0701 };
0702
0703 drc0_out: port@1 {
0704 reg = <1>;
0705
0706 drc0_out_tcon0: endpoint {
0707 remote-endpoint = <&tcon0_in_drc0>;
0708 };
0709 };
0710 };
0711 };
0712
0713 rtc: rtc@1f00000 {
0714 compatible = "allwinner,sun8i-a23-rtc";
0715 reg = <0x01f00000 0x400>;
0716 interrupt-parent = <&r_intc>;
0717 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
0718 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
0719 clock-output-names = "osc32k", "osc32k-out";
0720 clocks = <&ext_osc32k>;
0721 #clock-cells = <1>;
0722 };
0723
0724 r_intc: interrupt-controller@1f00c00 {
0725 compatible = "allwinner,sun6i-a31-r-intc";
0726 interrupt-controller;
0727 #interrupt-cells = <3>;
0728 reg = <0x01f00c00 0x400>;
0729 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0730 };
0731
0732 prcm@1f01400 {
0733 compatible = "allwinner,sun8i-a23-prcm";
0734 reg = <0x01f01400 0x200>;
0735
0736 ar100: ar100_clk {
0737 compatible = "fixed-factor-clock";
0738 #clock-cells = <0>;
0739 clock-div = <1>;
0740 clock-mult = <1>;
0741 clocks = <&osc24M>;
0742 clock-output-names = "ar100";
0743 };
0744
0745 ahb0: ahb0_clk {
0746 compatible = "fixed-factor-clock";
0747 #clock-cells = <0>;
0748 clock-div = <1>;
0749 clock-mult = <1>;
0750 clocks = <&ar100>;
0751 clock-output-names = "ahb0";
0752 };
0753
0754 apb0: apb0_clk {
0755 compatible = "allwinner,sun8i-a23-apb0-clk";
0756 #clock-cells = <0>;
0757 clocks = <&ahb0>;
0758 clock-output-names = "apb0";
0759 };
0760
0761 apb0_gates: apb0_gates_clk {
0762 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
0763 #clock-cells = <1>;
0764 clocks = <&apb0>;
0765 clock-output-names = "apb0_pio", "apb0_timer",
0766 "apb0_rsb", "apb0_uart",
0767 "apb0_i2c";
0768 };
0769
0770 apb0_rst: apb0_rst {
0771 compatible = "allwinner,sun6i-a31-clock-reset";
0772 #reset-cells = <1>;
0773 };
0774
0775 codec_analog: codec-analog {
0776 compatible = "allwinner,sun8i-a23-codec-analog";
0777 };
0778 };
0779
0780 cpucfg@1f01c00 {
0781 compatible = "allwinner,sun8i-a23-cpuconfig";
0782 reg = <0x01f01c00 0x300>;
0783 };
0784
0785 r_uart: serial@1f02800 {
0786 compatible = "snps,dw-apb-uart";
0787 reg = <0x01f02800 0x400>;
0788 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0789 reg-shift = <2>;
0790 reg-io-width = <4>;
0791 clocks = <&apb0_gates 4>;
0792 resets = <&apb0_rst 4>;
0793 status = "disabled";
0794 };
0795
0796 r_i2c: i2c@1f02400 {
0797 compatible = "allwinner,sun8i-a23-i2c",
0798 "allwinner,sun6i-a31-i2c";
0799 reg = <0x01f02400 0x400>;
0800 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
0801 pinctrl-names = "default";
0802 pinctrl-0 = <&r_i2c_pins>;
0803 clocks = <&apb0_gates 6>;
0804 resets = <&apb0_rst 6>;
0805 status = "disabled";
0806 #address-cells = <1>;
0807 #size-cells = <0>;
0808 };
0809
0810 r_pio: pinctrl@1f02c00 {
0811 compatible = "allwinner,sun8i-a23-r-pinctrl";
0812 reg = <0x01f02c00 0x400>;
0813 interrupt-parent = <&r_intc>;
0814 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0815 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>;
0816 clock-names = "apb", "hosc", "losc";
0817 gpio-controller;
0818 interrupt-controller;
0819 #interrupt-cells = <3>;
0820 #gpio-cells = <3>;
0821
0822 r_i2c_pins: r-i2c-pins {
0823 pins = "PL0", "PL1";
0824 function = "s_i2c";
0825 bias-pull-up;
0826 };
0827
0828 r_rsb_pins: r-rsb-pins {
0829 pins = "PL0", "PL1";
0830 function = "s_rsb";
0831 drive-strength = <20>;
0832 bias-pull-up;
0833 };
0834
0835 r_uart_pins_a: r-uart-pins {
0836 pins = "PL2", "PL3";
0837 function = "s_uart";
0838 };
0839 };
0840
0841 r_rsb: rsb@1f03400 {
0842 compatible = "allwinner,sun8i-a23-rsb";
0843 reg = <0x01f03400 0x400>;
0844 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
0845 clocks = <&apb0_gates 3>;
0846 clock-frequency = <3000000>;
0847 resets = <&apb0_rst 3>;
0848 pinctrl-names = "default";
0849 pinctrl-0 = <&r_rsb_pins>;
0850 status = "disabled";
0851 #address-cells = <1>;
0852 #size-cells = <0>;
0853 };
0854 };
0855 };
