0001 /*
0002 * Copyright 2013 Maxime Ripard
0003 *
0004 * Maxime Ripard <maxime.ripard@free-electrons.com>
0005 *
0006 * This file is dual-licensed: you can use it either under the terms
0007 * of the GPL or the X11 license, at your option. Note that this dual
0008 * licensing only applies to this file, and not this project as a
0009 * whole.
0010 *
0011 * a) This file is free software; you can redistribute it and/or
0012 * modify it under the terms of the GNU General Public License as
0013 * published by the Free Software Foundation; either version 2 of the
0014 * License, or (at your option) any later version.
0015 *
0016 * This file is distributed in the hope that it will be useful,
0017 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0019 * GNU General Public License for more details.
0020 *
0021 * Or, alternatively,
0022 *
0023 * b) Permission is hereby granted, free of charge, to any person
0024 * obtaining a copy of this software and associated documentation
0025 * files (the "Software"), to deal in the Software without
0026 * restriction, including without limitation the rights to use,
0027 * copy, modify, merge, publish, distribute, sublicense, and/or
0028 * sell copies of the Software, and to permit persons to whom the
0029 * Software is furnished to do so, subject to the following
0030 * conditions:
0031 *
0032 * The above copyright notice and this permission notice shall be
0033 * included in all copies or substantial portions of the Software.
0034 *
0035 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0036 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0037 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0038 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0039 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0040 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0041 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0042 * OTHER DEALINGS IN THE SOFTWARE.
0043 */
0044
0045 #include <dt-bindings/interrupt-controller/arm-gic.h>
0046 #include <dt-bindings/thermal/thermal.h>
0047 #include <dt-bindings/dma/sun4i-a10.h>
0048 #include <dt-bindings/clock/sun7i-a20-ccu.h>
0049 #include <dt-bindings/reset/sun4i-a10-ccu.h>
0050 #include <dt-bindings/pinctrl/sun4i-a10.h>
0051
0052 / {
0053 interrupt-parent = <&gic>;
0054 #address-cells = <1>;
0055 #size-cells = <1>;
0056
0057 aliases {
0058 ethernet0 = &gmac;
0059 };
0060
0061 chosen {
0062 #address-cells = <1>;
0063 #size-cells = <1>;
0064 ranges;
0065
0066 framebuffer-lcd0-hdmi {
0067 compatible = "allwinner,simple-framebuffer",
0068 "simple-framebuffer";
0069 allwinner,pipeline = "de_be0-lcd0-hdmi";
0070 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
0071 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
0072 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
0073 <&ccu CLK_HDMI>;
0074 status = "disabled";
0075 };
0076
0077 framebuffer-lcd0 {
0078 compatible = "allwinner,simple-framebuffer",
0079 "simple-framebuffer";
0080 allwinner,pipeline = "de_be0-lcd0";
0081 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
0082 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
0083 <&ccu CLK_DRAM_DE_BE0>;
0084 status = "disabled";
0085 };
0086
0087 framebuffer-lcd0-tve0 {
0088 compatible = "allwinner,simple-framebuffer",
0089 "simple-framebuffer";
0090 allwinner,pipeline = "de_be0-lcd0-tve0";
0091 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
0092 <&ccu CLK_AHB_DE_BE0>,
0093 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
0094 <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
0095 status = "disabled";
0096 };
0097 };
0098
0099 cpus {
0100 #address-cells = <1>;
0101 #size-cells = <0>;
0102
0103 cpu0: cpu@0 {
0104 compatible = "arm,cortex-a7";
0105 device_type = "cpu";
0106 reg = <0>;
0107 clocks = <&ccu CLK_CPU>;
0108 clock-latency = <244144>; /* 8 32k periods */
0109 operating-points =
0110 /* kHz uV */
0111 <960000 1400000>,
0112 <912000 1400000>,
0113 <864000 1300000>,
0114 <720000 1200000>,
0115 <528000 1100000>,
0116 <312000 1000000>,
0117 <144000 1000000>;
0118 #cooling-cells = <2>;
0119 };
0120
0121 cpu1: cpu@1 {
0122 compatible = "arm,cortex-a7";
0123 device_type = "cpu";
0124 reg = <1>;
0125 clocks = <&ccu CLK_CPU>;
0126 clock-latency = <244144>; /* 8 32k periods */
0127 operating-points =
0128 /* kHz uV */
0129 <960000 1400000>,
0130 <912000 1400000>,
0131 <864000 1300000>,
0132 <720000 1200000>,
0133 <528000 1100000>,
0134 <312000 1000000>,
0135 <144000 1000000>;
0136 #cooling-cells = <2>;
0137 };
0138 };
0139
0140 thermal-zones {
0141 cpu-thermal {
0142 /* milliseconds */
0143 polling-delay-passive = <250>;
0144 polling-delay = <1000>;
0145 thermal-sensors = <&rtp>;
0146
0147 cooling-maps {
0148 map0 {
0149 trip = <&cpu_alert0>;
0150 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0151 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0152 };
0153 };
0154
0155 trips {
0156 cpu_alert0: cpu_alert0 {
0157 /* milliCelsius */
0158 temperature = <75000>;
0159 hysteresis = <2000>;
0160 type = "passive";
0161 };
0162
0163 cpu_crit: cpu_crit {
0164 /* milliCelsius */
0165 temperature = <100000>;
0166 hysteresis = <2000>;
0167 type = "critical";
0168 };
0169 };
0170 };
0171 };
0172
0173 reserved-memory {
0174 #address-cells = <1>;
0175 #size-cells = <1>;
0176 ranges;
0177
0178 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
0179 default-pool {
0180 compatible = "shared-dma-pool";
0181 size = <0x6000000>;
0182 alloc-ranges = <0x40000000 0x10000000>;
0183 reusable;
0184 linux,cma-default;
0185 };
0186 };
0187
0188 timer {
0189 compatible = "arm,armv7-timer";
0190 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0191 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0192 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0193 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0194 };
0195
0196 pmu {
0197 compatible = "arm,cortex-a7-pmu";
0198 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
0199 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
0200 };
0201
0202 clocks {
0203 #address-cells = <1>;
0204 #size-cells = <1>;
0205 ranges;
0206
0207 osc24M: clk-24M {
0208 #clock-cells = <0>;
0209 compatible = "fixed-clock";
0210 clock-frequency = <24000000>;
0211 clock-output-names = "osc24M";
0212 };
0213
0214 osc32k: clk-32k {
0215 #clock-cells = <0>;
0216 compatible = "fixed-clock";
0217 clock-frequency = <32768>;
0218 clock-output-names = "osc32k";
0219 };
0220
0221 /*
0222 * The following two are dummy clocks, placeholders
0223 * used in the gmac_tx clock. The gmac driver will
0224 * choose one parent depending on the PHY interface
0225 * mode, using clk_set_rate auto-reparenting.
0226 *
0227 * The actual TX clock rate is not controlled by the
0228 * gmac_tx clock.
0229 */
0230 mii_phy_tx_clk: clk-mii-phy-tx {
0231 #clock-cells = <0>;
0232 compatible = "fixed-clock";
0233 clock-frequency = <25000000>;
0234 clock-output-names = "mii_phy_tx";
0235 };
0236
0237 gmac_int_tx_clk: clk-gmac-int-tx {
0238 #clock-cells = <0>;
0239 compatible = "fixed-clock";
0240 clock-frequency = <125000000>;
0241 clock-output-names = "gmac_int_tx";
0242 };
0243
0244 gmac_tx_clk: clk@1c20164 {
0245 #clock-cells = <0>;
0246 compatible = "allwinner,sun7i-a20-gmac-clk";
0247 reg = <0x01c20164 0x4>;
0248 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
0249 clock-output-names = "gmac_tx";
0250 };
0251 };
0252
0253
0254 de: display-engine {
0255 compatible = "allwinner,sun7i-a20-display-engine";
0256 allwinner,pipelines = <&fe0>, <&fe1>;
0257 status = "disabled";
0258 };
0259
0260 soc {
0261 compatible = "simple-bus";
0262 #address-cells = <1>;
0263 #size-cells = <1>;
0264 ranges;
0265
0266 system-control@1c00000 {
0267 compatible = "allwinner,sun7i-a20-system-control",
0268 "allwinner,sun4i-a10-system-control";
0269 reg = <0x01c00000 0x30>;
0270 #address-cells = <1>;
0271 #size-cells = <1>;
0272 ranges;
0273
0274 sram_a: sram@0 {
0275 compatible = "mmio-sram";
0276 reg = <0x00000000 0xc000>;
0277 #address-cells = <1>;
0278 #size-cells = <1>;
0279 ranges = <0 0x00000000 0xc000>;
0280
0281 emac_sram: sram-section@8000 {
0282 compatible = "allwinner,sun7i-a20-sram-a3-a4",
0283 "allwinner,sun4i-a10-sram-a3-a4";
0284 reg = <0x8000 0x4000>;
0285 status = "disabled";
0286 };
0287 };
0288
0289 sram_d: sram@10000 {
0290 compatible = "mmio-sram";
0291 reg = <0x00010000 0x1000>;
0292 #address-cells = <1>;
0293 #size-cells = <1>;
0294 ranges = <0 0x00010000 0x1000>;
0295
0296 otg_sram: sram-section@0 {
0297 compatible = "allwinner,sun7i-a20-sram-d",
0298 "allwinner,sun4i-a10-sram-d";
0299 reg = <0x0000 0x1000>;
0300 status = "disabled";
0301 };
0302 };
0303
0304 sram_c: sram@1d00000 {
0305 compatible = "mmio-sram";
0306 reg = <0x01d00000 0xd0000>;
0307 #address-cells = <1>;
0308 #size-cells = <1>;
0309 ranges = <0 0x01d00000 0xd0000>;
0310
0311 ve_sram: sram-section@0 {
0312 compatible = "allwinner,sun7i-a20-sram-c1",
0313 "allwinner,sun4i-a10-sram-c1";
0314 reg = <0x000000 0x80000>;
0315 };
0316 };
0317 };
0318
0319 nmi_intc: interrupt-controller@1c00030 {
0320 compatible = "allwinner,sun7i-a20-sc-nmi";
0321 interrupt-controller;
0322 #interrupt-cells = <2>;
0323 reg = <0x01c00030 0x0c>;
0324 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
0325 };
0326
0327 dma: dma-controller@1c02000 {
0328 compatible = "allwinner,sun4i-a10-dma";
0329 reg = <0x01c02000 0x1000>;
0330 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0331 clocks = <&ccu CLK_AHB_DMA>;
0332 #dma-cells = <2>;
0333 };
0334
0335 nfc: nand-controller@1c03000 {
0336 compatible = "allwinner,sun4i-a10-nand";
0337 reg = <0x01c03000 0x1000>;
0338 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
0339 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
0340 clock-names = "ahb", "mod";
0341 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
0342 dma-names = "rxtx";
0343 status = "disabled";
0344 #address-cells = <1>;
0345 #size-cells = <0>;
0346 };
0347
0348 spi0: spi@1c05000 {
0349 compatible = "allwinner,sun4i-a10-spi";
0350 reg = <0x01c05000 0x1000>;
0351 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0352 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
0353 clock-names = "ahb", "mod";
0354 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
0355 <&dma SUN4I_DMA_DEDICATED 26>;
0356 dma-names = "rx", "tx";
0357 status = "disabled";
0358 #address-cells = <1>;
0359 #size-cells = <0>;
0360 num-cs = <4>;
0361 };
0362
0363 spi1: spi@1c06000 {
0364 compatible = "allwinner,sun4i-a10-spi";
0365 reg = <0x01c06000 0x1000>;
0366 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0367 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
0368 clock-names = "ahb", "mod";
0369 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
0370 <&dma SUN4I_DMA_DEDICATED 8>;
0371 dma-names = "rx", "tx";
0372 status = "disabled";
0373 #address-cells = <1>;
0374 #size-cells = <0>;
0375 num-cs = <1>;
0376 };
0377
0378 csi0: csi@1c09000 {
0379 compatible = "allwinner,sun7i-a20-csi0";
0380 reg = <0x01c09000 0x1000>;
0381 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0382 clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
0383 clock-names = "bus", "isp", "ram";
0384 resets = <&ccu RST_CSI0>;
0385 status = "disabled";
0386 };
0387
0388 emac: ethernet@1c0b000 {
0389 compatible = "allwinner,sun4i-a10-emac";
0390 reg = <0x01c0b000 0x1000>;
0391 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0392 clocks = <&ccu CLK_AHB_EMAC>;
0393 allwinner,sram = <&emac_sram 1>;
0394 status = "disabled";
0395 };
0396
0397 mdio: mdio@1c0b080 {
0398 compatible = "allwinner,sun4i-a10-mdio";
0399 reg = <0x01c0b080 0x14>;
0400 status = "disabled";
0401 #address-cells = <1>;
0402 #size-cells = <0>;
0403 };
0404
0405 tcon0: lcd-controller@1c0c000 {
0406 compatible = "allwinner,sun7i-a20-tcon0",
0407 "allwinner,sun7i-a20-tcon";
0408 reg = <0x01c0c000 0x1000>;
0409 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
0410 resets = <&ccu RST_TCON0>, <&ccu RST_LVDS>;
0411 reset-names = "lcd", "lvds";
0412 clocks = <&ccu CLK_AHB_LCD0>,
0413 <&ccu CLK_TCON0_CH0>,
0414 <&ccu CLK_TCON0_CH1>;
0415 clock-names = "ahb",
0416 "tcon-ch0",
0417 "tcon-ch1";
0418 clock-output-names = "tcon0-pixel-clock";
0419 #clock-cells = <0>;
0420 dmas = <&dma SUN4I_DMA_DEDICATED 14>;
0421
0422 ports {
0423 #address-cells = <1>;
0424 #size-cells = <0>;
0425
0426 tcon0_in: port@0 {
0427 #address-cells = <1>;
0428 #size-cells = <0>;
0429 reg = <0>;
0430
0431 tcon0_in_be0: endpoint@0 {
0432 reg = <0>;
0433 remote-endpoint = <&be0_out_tcon0>;
0434 };
0435
0436 tcon0_in_be1: endpoint@1 {
0437 reg = <1>;
0438 remote-endpoint = <&be1_out_tcon0>;
0439 };
0440 };
0441
0442 tcon0_out: port@1 {
0443 #address-cells = <1>;
0444 #size-cells = <0>;
0445 reg = <1>;
0446
0447 tcon0_out_hdmi: endpoint@1 {
0448 reg = <1>;
0449 remote-endpoint = <&hdmi_in_tcon0>;
0450 allwinner,tcon-channel = <1>;
0451 };
0452 };
0453 };
0454 };
0455
0456 tcon1: lcd-controller@1c0d000 {
0457 compatible = "allwinner,sun7i-a20-tcon1",
0458 "allwinner,sun7i-a20-tcon";
0459 reg = <0x01c0d000 0x1000>;
0460 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0461 resets = <&ccu RST_TCON1>;
0462 reset-names = "lcd";
0463 clocks = <&ccu CLK_AHB_LCD1>,
0464 <&ccu CLK_TCON1_CH0>,
0465 <&ccu CLK_TCON1_CH1>;
0466 clock-names = "ahb",
0467 "tcon-ch0",
0468 "tcon-ch1";
0469 clock-output-names = "tcon1-pixel-clock";
0470 #clock-cells = <0>;
0471 dmas = <&dma SUN4I_DMA_DEDICATED 15>;
0472
0473 ports {
0474 #address-cells = <1>;
0475 #size-cells = <0>;
0476
0477 tcon1_in: port@0 {
0478 #address-cells = <1>;
0479 #size-cells = <0>;
0480 reg = <0>;
0481
0482 tcon1_in_be0: endpoint@0 {
0483 reg = <0>;
0484 remote-endpoint = <&be0_out_tcon1>;
0485 };
0486
0487 tcon1_in_be1: endpoint@1 {
0488 reg = <1>;
0489 remote-endpoint = <&be1_out_tcon1>;
0490 };
0491 };
0492
0493 tcon1_out: port@1 {
0494 #address-cells = <1>;
0495 #size-cells = <0>;
0496 reg = <1>;
0497
0498 tcon1_out_hdmi: endpoint@1 {
0499 reg = <1>;
0500 remote-endpoint = <&hdmi_in_tcon1>;
0501 allwinner,tcon-channel = <1>;
0502 };
0503 };
0504 };
0505 };
0506
0507 video-codec@1c0e000 {
0508 compatible = "allwinner,sun7i-a20-video-engine";
0509 reg = <0x01c0e000 0x1000>;
0510 clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
0511 <&ccu CLK_DRAM_VE>;
0512 clock-names = "ahb", "mod", "ram";
0513 resets = <&ccu RST_VE>;
0514 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
0515 allwinner,sram = <&ve_sram 1>;
0516 };
0517
0518 mmc0: mmc@1c0f000 {
0519 compatible = "allwinner,sun7i-a20-mmc";
0520 reg = <0x01c0f000 0x1000>;
0521 clocks = <&ccu CLK_AHB_MMC0>,
0522 <&ccu CLK_MMC0>,
0523 <&ccu CLK_MMC0_OUTPUT>,
0524 <&ccu CLK_MMC0_SAMPLE>;
0525 clock-names = "ahb",
0526 "mmc",
0527 "output",
0528 "sample";
0529 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0530 pinctrl-names = "default";
0531 pinctrl-0 = <&mmc0_pins>;
0532 status = "disabled";
0533 #address-cells = <1>;
0534 #size-cells = <0>;
0535 };
0536
0537 mmc1: mmc@1c10000 {
0538 compatible = "allwinner,sun7i-a20-mmc";
0539 reg = <0x01c10000 0x1000>;
0540 clocks = <&ccu CLK_AHB_MMC1>,
0541 <&ccu CLK_MMC1>,
0542 <&ccu CLK_MMC1_OUTPUT>,
0543 <&ccu CLK_MMC1_SAMPLE>;
0544 clock-names = "ahb",
0545 "mmc",
0546 "output",
0547 "sample";
0548 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
0549 status = "disabled";
0550 #address-cells = <1>;
0551 #size-cells = <0>;
0552 };
0553
0554 mmc2: mmc@1c11000 {
0555 compatible = "allwinner,sun7i-a20-mmc";
0556 reg = <0x01c11000 0x1000>;
0557 clocks = <&ccu CLK_AHB_MMC2>,
0558 <&ccu CLK_MMC2>,
0559 <&ccu CLK_MMC2_OUTPUT>,
0560 <&ccu CLK_MMC2_SAMPLE>;
0561 clock-names = "ahb",
0562 "mmc",
0563 "output",
0564 "sample";
0565 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0566 pinctrl-names = "default";
0567 pinctrl-0 = <&mmc2_pins>;
0568 status = "disabled";
0569 #address-cells = <1>;
0570 #size-cells = <0>;
0571 };
0572
0573 mmc3: mmc@1c12000 {
0574 compatible = "allwinner,sun7i-a20-mmc";
0575 reg = <0x01c12000 0x1000>;
0576 clocks = <&ccu CLK_AHB_MMC3>,
0577 <&ccu CLK_MMC3>,
0578 <&ccu CLK_MMC3_OUTPUT>,
0579 <&ccu CLK_MMC3_SAMPLE>;
0580 clock-names = "ahb",
0581 "mmc",
0582 "output",
0583 "sample";
0584 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0585 pinctrl-names = "default";
0586 pinctrl-0 = <&mmc3_pins>;
0587 status = "disabled";
0588 #address-cells = <1>;
0589 #size-cells = <0>;
0590 };
0591
0592 usb_otg: usb@1c13000 {
0593 compatible = "allwinner,sun4i-a10-musb";
0594 reg = <0x01c13000 0x0400>;
0595 clocks = <&ccu CLK_AHB_OTG>;
0596 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0597 interrupt-names = "mc";
0598 phys = <&usbphy 0>;
0599 phy-names = "usb";
0600 extcon = <&usbphy 0>;
0601 allwinner,sram = <&otg_sram 1>;
0602 dr_mode = "otg";
0603 status = "disabled";
0604 };
0605
0606 usbphy: phy@1c13400 {
0607 #phy-cells = <1>;
0608 compatible = "allwinner,sun7i-a20-usb-phy";
0609 reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
0610 reg-names = "phy_ctrl", "pmu1", "pmu2";
0611 clocks = <&ccu CLK_USB_PHY>;
0612 clock-names = "usb_phy";
0613 resets = <&ccu RST_USB_PHY0>,
0614 <&ccu RST_USB_PHY1>,
0615 <&ccu RST_USB_PHY2>;
0616 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
0617 status = "disabled";
0618 };
0619
0620 ehci0: usb@1c14000 {
0621 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
0622 reg = <0x01c14000 0x100>;
0623 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
0624 clocks = <&ccu CLK_AHB_EHCI0>;
0625 phys = <&usbphy 1>;
0626 phy-names = "usb";
0627 status = "disabled";
0628 };
0629
0630 ohci0: usb@1c14400 {
0631 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
0632 reg = <0x01c14400 0x100>;
0633 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
0634 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
0635 phys = <&usbphy 1>;
0636 phy-names = "usb";
0637 status = "disabled";
0638 };
0639
0640 crypto: crypto-engine@1c15000 {
0641 compatible = "allwinner,sun7i-a20-crypto",
0642 "allwinner,sun4i-a10-crypto";
0643 reg = <0x01c15000 0x1000>;
0644 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0645 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
0646 clock-names = "ahb", "mod";
0647 };
0648
0649 hdmi: hdmi@1c16000 {
0650 compatible = "allwinner,sun7i-a20-hdmi",
0651 "allwinner,sun5i-a10s-hdmi";
0652 reg = <0x01c16000 0x1000>;
0653 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
0654 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
0655 <&ccu CLK_PLL_VIDEO0_2X>,
0656 <&ccu CLK_PLL_VIDEO1_2X>;
0657 clock-names = "ahb", "mod", "pll-0", "pll-1";
0658 dmas = <&dma SUN4I_DMA_NORMAL 16>,
0659 <&dma SUN4I_DMA_NORMAL 16>,
0660 <&dma SUN4I_DMA_DEDICATED 24>;
0661 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
0662 status = "disabled";
0663
0664 ports {
0665 #address-cells = <1>;
0666 #size-cells = <0>;
0667
0668 hdmi_in: port@0 {
0669 #address-cells = <1>;
0670 #size-cells = <0>;
0671 reg = <0>;
0672
0673 hdmi_in_tcon0: endpoint@0 {
0674 reg = <0>;
0675 remote-endpoint = <&tcon0_out_hdmi>;
0676 };
0677
0678 hdmi_in_tcon1: endpoint@1 {
0679 reg = <1>;
0680 remote-endpoint = <&tcon1_out_hdmi>;
0681 };
0682 };
0683
0684 hdmi_out: port@1 {
0685 reg = <1>;
0686 };
0687 };
0688 };
0689
0690 spi2: spi@1c17000 {
0691 compatible = "allwinner,sun4i-a10-spi";
0692 reg = <0x01c17000 0x1000>;
0693 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0694 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
0695 clock-names = "ahb", "mod";
0696 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
0697 <&dma SUN4I_DMA_DEDICATED 28>;
0698 dma-names = "rx", "tx";
0699 status = "disabled";
0700 #address-cells = <1>;
0701 #size-cells = <0>;
0702 num-cs = <1>;
0703 };
0704
0705 ahci: sata@1c18000 {
0706 compatible = "allwinner,sun4i-a10-ahci";
0707 reg = <0x01c18000 0x1000>;
0708 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0709 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
0710 status = "disabled";
0711 };
0712
0713 ehci1: usb@1c1c000 {
0714 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
0715 reg = <0x01c1c000 0x100>;
0716 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
0717 clocks = <&ccu CLK_AHB_EHCI1>;
0718 phys = <&usbphy 2>;
0719 phy-names = "usb";
0720 status = "disabled";
0721 };
0722
0723 ohci1: usb@1c1c400 {
0724 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
0725 reg = <0x01c1c400 0x100>;
0726 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0727 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
0728 phys = <&usbphy 2>;
0729 phy-names = "usb";
0730 status = "disabled";
0731 };
0732
0733 csi1: csi@1c1d000 {
0734 compatible = "allwinner,sun7i-a20-csi1",
0735 "allwinner,sun4i-a10-csi1";
0736 reg = <0x01c1d000 0x1000>;
0737 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
0738 clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
0739 clock-names = "bus", "ram";
0740 resets = <&ccu RST_CSI1>;
0741 status = "disabled";
0742 };
0743
0744 spi3: spi@1c1f000 {
0745 compatible = "allwinner,sun4i-a10-spi";
0746 reg = <0x01c1f000 0x1000>;
0747 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0748 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
0749 clock-names = "ahb", "mod";
0750 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
0751 <&dma SUN4I_DMA_DEDICATED 30>;
0752 dma-names = "rx", "tx";
0753 status = "disabled";
0754 #address-cells = <1>;
0755 #size-cells = <0>;
0756 num-cs = <1>;
0757 };
0758
0759 ccu: clock@1c20000 {
0760 compatible = "allwinner,sun7i-a20-ccu";
0761 reg = <0x01c20000 0x400>;
0762 clocks = <&osc24M>, <&osc32k>;
0763 clock-names = "hosc", "losc";
0764 #clock-cells = <1>;
0765 #reset-cells = <1>;
0766 };
0767
0768 pio: pinctrl@1c20800 {
0769 compatible = "allwinner,sun7i-a20-pinctrl";
0770 reg = <0x01c20800 0x400>;
0771 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0772 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
0773 clock-names = "apb", "hosc", "losc";
0774 gpio-controller;
0775 interrupt-controller;
0776 #interrupt-cells = <3>;
0777 #gpio-cells = <3>;
0778
0779 /omit-if-no-ref/
0780 can_pa_pins: can-pa-pins {
0781 pins = "PA16", "PA17";
0782 function = "can";
0783 };
0784
0785 /omit-if-no-ref/
0786 can_ph_pins: can-ph-pins {
0787 pins = "PH20", "PH21";
0788 function = "can";
0789 };
0790
0791 /omit-if-no-ref/
0792 clk_out_a_pin: clk-out-a-pin {
0793 pins = "PI12";
0794 function = "clk_out_a";
0795 };
0796
0797 /omit-if-no-ref/
0798 clk_out_b_pin: clk-out-b-pin {
0799 pins = "PI13";
0800 function = "clk_out_b";
0801 };
0802
0803 /omit-if-no-ref/
0804 csi0_8bits_pins: csi-8bits-pins {
0805 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
0806 "PE6", "PE7", "PE8", "PE9", "PE10",
0807 "PE11";
0808 function = "csi0";
0809 };
0810
0811 /omit-if-no-ref/
0812 csi0_clk_pin: csi-clk-pin {
0813 pins = "PE1";
0814 function = "csi0";
0815 };
0816
0817 /omit-if-no-ref/
0818 csi1_8bits_pg_pins: csi1-8bits-pg-pins {
0819 pins = "PG0", "PG2", "PG3", "PG4", "PG5",
0820 "PG6", "PG7", "PG8", "PG9", "PG10",
0821 "PG11";
0822 function = "csi1";
0823 };
0824
0825 /omit-if-no-ref/
0826 csi1_24bits_ph_pins: csi1-24bits-ph-pins {
0827 pins = "PH0", "PH1", "PH2", "PH3", "PH4",
0828 "PH5", "PH6", "PH7", "PH8", "PH9",
0829 "PH10", "PH11", "PH12", "PH13", "PH14",
0830 "PH15", "PH16", "PH17", "PH18", "PH19",
0831 "PH20", "PH21", "PH22", "PH23", "PH24",
0832 "PH25", "PH26", "PH27";
0833 function = "csi1";
0834 };
0835
0836 /omit-if-no-ref/
0837 csi1_clk_pg_pin: csi1-clk-pg-pin {
0838 pins = "PG1";
0839 function = "csi1";
0840 };
0841
0842 /omit-if-no-ref/
0843 emac_pa_pins: emac-pa-pins {
0844 pins = "PA0", "PA1", "PA2",
0845 "PA3", "PA4", "PA5", "PA6",
0846 "PA7", "PA8", "PA9", "PA10",
0847 "PA11", "PA12", "PA13", "PA14",
0848 "PA15", "PA16";
0849 function = "emac";
0850 };
0851
0852 /omit-if-no-ref/
0853 emac_ph_pins: emac-ph-pins {
0854 pins = "PH8", "PH9", "PH10", "PH11",
0855 "PH14", "PH15", "PH16", "PH17",
0856 "PH18", "PH19", "PH20", "PH21",
0857 "PH22", "PH23", "PH24", "PH25",
0858 "PH26";
0859 function = "emac";
0860 };
0861
0862 /omit-if-no-ref/
0863 gmac_mii_pins: gmac-mii-pins {
0864 pins = "PA0", "PA1", "PA2",
0865 "PA3", "PA4", "PA5", "PA6",
0866 "PA7", "PA8", "PA9", "PA10",
0867 "PA11", "PA12", "PA13", "PA14",
0868 "PA15", "PA16";
0869 function = "gmac";
0870 };
0871
0872 /omit-if-no-ref/
0873 gmac_rgmii_pins: gmac-rgmii-pins {
0874 pins = "PA0", "PA1", "PA2",
0875 "PA3", "PA4", "PA5", "PA6",
0876 "PA7", "PA8", "PA10",
0877 "PA11", "PA12", "PA13",
0878 "PA15", "PA16";
0879 function = "gmac";
0880 /*
0881 * data lines in RGMII mode use DDR mode
0882 * and need a higher signal drive strength
0883 */
0884 drive-strength = <40>;
0885 };
0886
0887 /omit-if-no-ref/
0888 i2c0_pins: i2c0-pins {
0889 pins = "PB0", "PB1";
0890 function = "i2c0";
0891 };
0892
0893 /omit-if-no-ref/
0894 i2c1_pins: i2c1-pins {
0895 pins = "PB18", "PB19";
0896 function = "i2c1";
0897 };
0898
0899 /omit-if-no-ref/
0900 i2c2_pins: i2c2-pins {
0901 pins = "PB20", "PB21";
0902 function = "i2c2";
0903 };
0904
0905 /omit-if-no-ref/
0906 i2c3_pins: i2c3-pins {
0907 pins = "PI0", "PI1";
0908 function = "i2c3";
0909 };
0910
0911 /omit-if-no-ref/
0912 ir0_rx_pin: ir0-rx-pin {
0913 pins = "PB4";
0914 function = "ir0";
0915 };
0916
0917 /omit-if-no-ref/
0918 ir0_tx_pin: ir0-tx-pin {
0919 pins = "PB3";
0920 function = "ir0";
0921 };
0922
0923 /omit-if-no-ref/
0924 ir1_rx_pin: ir1-rx-pin {
0925 pins = "PB23";
0926 function = "ir1";
0927 };
0928
0929 /omit-if-no-ref/
0930 ir1_tx_pin: ir1-tx-pin {
0931 pins = "PB22";
0932 function = "ir1";
0933 };
0934
0935 /omit-if-no-ref/
0936 lcd_lvds0_pins: lcd-lvds0-pins {
0937 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
0938 "PD5", "PD6", "PD7", "PD8", "PD9";
0939 function = "lvds0";
0940 };
0941
0942 /omit-if-no-ref/
0943 lcd_lvds1_pins: lcd-lvds1-pins {
0944 pins = "PD10", "PD11", "PD12", "PD13", "PD14",
0945 "PD15", "PD16", "PD17", "PD18", "PD19";
0946 function = "lvds1";
0947 };
0948
0949 /omit-if-no-ref/
0950 mmc0_pins: mmc0-pins {
0951 pins = "PF0", "PF1", "PF2",
0952 "PF3", "PF4", "PF5";
0953 function = "mmc0";
0954 drive-strength = <30>;
0955 bias-pull-up;
0956 };
0957
0958 /omit-if-no-ref/
0959 mmc2_pins: mmc2-pins {
0960 pins = "PC6", "PC7", "PC8",
0961 "PC9", "PC10", "PC11";
0962 function = "mmc2";
0963 drive-strength = <30>;
0964 bias-pull-up;
0965 };
0966
0967 /omit-if-no-ref/
0968 mmc3_pins: mmc3-pins {
0969 pins = "PI4", "PI5", "PI6",
0970 "PI7", "PI8", "PI9";
0971 function = "mmc3";
0972 drive-strength = <30>;
0973 bias-pull-up;
0974 };
0975
0976 /omit-if-no-ref/
0977 ps2_0_pins: ps2-0-pins {
0978 pins = "PI20", "PI21";
0979 function = "ps2";
0980 };
0981
0982 /omit-if-no-ref/
0983 ps2_1_ph_pins: ps2-1-ph-pins {
0984 pins = "PH12", "PH13";
0985 function = "ps2";
0986 };
0987
0988 /omit-if-no-ref/
0989 pwm0_pin: pwm0-pin {
0990 pins = "PB2";
0991 function = "pwm";
0992 };
0993
0994 /omit-if-no-ref/
0995 pwm1_pin: pwm1-pin {
0996 pins = "PI3";
0997 function = "pwm";
0998 };
0999
1000 /omit-if-no-ref/
1001 spdif_tx_pin: spdif-tx-pin {
1002 pins = "PB13";
1003 function = "spdif";
1004 bias-pull-up;
1005 };
1006
1007 /omit-if-no-ref/
1008 spi0_pi_pins: spi0-pi-pins {
1009 pins = "PI11", "PI12", "PI13";
1010 function = "spi0";
1011 };
1012
1013 /omit-if-no-ref/
1014 spi0_cs0_pi_pin: spi0-cs0-pi-pin {
1015 pins = "PI10";
1016 function = "spi0";
1017 };
1018
1019 /omit-if-no-ref/
1020 spi0_cs1_pi_pin: spi0-cs1-pi-pin {
1021 pins = "PI14";
1022 function = "spi0";
1023 };
1024
1025 /omit-if-no-ref/
1026 spi1_pi_pins: spi1-pi-pins {
1027 pins = "PI17", "PI18", "PI19";
1028 function = "spi1";
1029 };
1030
1031 /omit-if-no-ref/
1032 spi1_cs0_pi_pin: spi1-cs0-pi-pin {
1033 pins = "PI16";
1034 function = "spi1";
1035 };
1036
1037 /omit-if-no-ref/
1038 spi2_pb_pins: spi2-pb-pins {
1039 pins = "PB15", "PB16", "PB17";
1040 function = "spi2";
1041 };
1042
1043 /omit-if-no-ref/
1044 spi2_cs0_pb_pin: spi2-cs0-pb-pin {
1045 pins = "PB14";
1046 function = "spi2";
1047 };
1048
1049 /omit-if-no-ref/
1050 spi2_pc_pins: spi2-pc-pins {
1051 pins = "PC20", "PC21", "PC22";
1052 function = "spi2";
1053 };
1054
1055 /omit-if-no-ref/
1056 spi2_cs0_pc_pin: spi2-cs0-pc-pin {
1057 pins = "PC19";
1058 function = "spi2";
1059 };
1060
1061 /omit-if-no-ref/
1062 uart0_pb_pins: uart0-pb-pins {
1063 pins = "PB22", "PB23";
1064 function = "uart0";
1065 };
1066
1067 /omit-if-no-ref/
1068 uart0_pf_pins: uart0-pf-pins {
1069 pins = "PF2", "PF4";
1070 function = "uart0";
1071 };
1072
1073 /omit-if-no-ref/
1074 uart1_pa_pins: uart1-pa-pins {
1075 pins = "PA10", "PA11";
1076 function = "uart1";
1077 };
1078
1079 /omit-if-no-ref/
1080 uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins {
1081 pins = "PA12", "PA13";
1082 function = "uart1";
1083 };
1084
1085 /omit-if-no-ref/
1086 uart2_pa_pins: uart2-pa-pins {
1087 pins = "PA2", "PA3";
1088 function = "uart2";
1089 };
1090
1091 /omit-if-no-ref/
1092 uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins {
1093 pins = "PA0", "PA1";
1094 function = "uart2";
1095 };
1096
1097 /omit-if-no-ref/
1098 uart2_pi_pins: uart2-pi-pins {
1099 pins = "PI18", "PI19";
1100 function = "uart2";
1101 };
1102
1103 /omit-if-no-ref/
1104 uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins {
1105 pins = "PI16", "PI17";
1106 function = "uart2";
1107 };
1108
1109 /omit-if-no-ref/
1110 uart3_pg_pins: uart3-pg-pins {
1111 pins = "PG6", "PG7";
1112 function = "uart3";
1113 };
1114
1115 /omit-if-no-ref/
1116 uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
1117 pins = "PG8", "PG9";
1118 function = "uart3";
1119 };
1120
1121 /omit-if-no-ref/
1122 uart3_ph_pins: uart3-ph-pins {
1123 pins = "PH0", "PH1";
1124 function = "uart3";
1125 };
1126
1127 /omit-if-no-ref/
1128 uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins {
1129 pins = "PH2", "PH3";
1130 function = "uart3";
1131 };
1132
1133 /omit-if-no-ref/
1134 uart4_pg_pins: uart4-pg-pins {
1135 pins = "PG10", "PG11";
1136 function = "uart4";
1137 };
1138
1139 /omit-if-no-ref/
1140 uart4_ph_pins: uart4-ph-pins {
1141 pins = "PH4", "PH5";
1142 function = "uart4";
1143 };
1144
1145 /omit-if-no-ref/
1146 uart5_ph_pins: uart5-ph-pins {
1147 pins = "PH6", "PH7";
1148 function = "uart5";
1149 };
1150
1151 /omit-if-no-ref/
1152 uart5_pi_pins: uart5-pi-pins {
1153 pins = "PI10", "PI11";
1154 function = "uart5";
1155 };
1156
1157 /omit-if-no-ref/
1158 uart6_pa_pins: uart6-pa-pins {
1159 pins = "PA12", "PA13";
1160 function = "uart6";
1161 };
1162
1163 /omit-if-no-ref/
1164 uart6_pi_pins: uart6-pi-pins {
1165 pins = "PI12", "PI13";
1166 function = "uart6";
1167 };
1168
1169 /omit-if-no-ref/
1170 uart7_pa_pins: uart7-pa-pins {
1171 pins = "PA14", "PA15";
1172 function = "uart7";
1173 };
1174
1175 /omit-if-no-ref/
1176 uart7_pi_pins: uart7-pi-pins {
1177 pins = "PI20", "PI21";
1178 function = "uart7";
1179 };
1180 };
1181
1182 timer@1c20c00 {
1183 compatible = "allwinner,sun4i-a10-timer";
1184 reg = <0x01c20c00 0x90>;
1185 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1186 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1187 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1188 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1189 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1190 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1191 clocks = <&osc24M>;
1192 };
1193
1194 wdt: watchdog@1c20c90 {
1195 compatible = "allwinner,sun4i-a10-wdt";
1196 reg = <0x01c20c90 0x10>;
1197 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1198 clocks = <&osc24M>;
1199 };
1200
1201 rtc: rtc@1c20d00 {
1202 compatible = "allwinner,sun7i-a20-rtc";
1203 reg = <0x01c20d00 0x20>;
1204 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1205 };
1206
1207 pwm: pwm@1c20e00 {
1208 compatible = "allwinner,sun7i-a20-pwm";
1209 reg = <0x01c20e00 0xc>;
1210 clocks = <&osc24M>;
1211 #pwm-cells = <3>;
1212 status = "disabled";
1213 };
1214
1215 spdif: spdif@1c21000 {
1216 #sound-dai-cells = <0>;
1217 compatible = "allwinner,sun4i-a10-spdif";
1218 reg = <0x01c21000 0x400>;
1219 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1220 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
1221 clock-names = "apb", "spdif";
1222 dmas = <&dma SUN4I_DMA_NORMAL 2>,
1223 <&dma SUN4I_DMA_NORMAL 2>;
1224 dma-names = "rx", "tx";
1225 status = "disabled";
1226 };
1227
1228 ir0: ir@1c21800 {
1229 compatible = "allwinner,sun4i-a10-ir";
1230 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
1231 clock-names = "apb", "ir";
1232 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1233 reg = <0x01c21800 0x40>;
1234 status = "disabled";
1235 };
1236
1237 ir1: ir@1c21c00 {
1238 compatible = "allwinner,sun4i-a10-ir";
1239 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
1240 clock-names = "apb", "ir";
1241 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1242 reg = <0x01c21c00 0x40>;
1243 status = "disabled";
1244 };
1245
1246 i2s1: i2s@1c22000 {
1247 #sound-dai-cells = <0>;
1248 compatible = "allwinner,sun4i-a10-i2s";
1249 reg = <0x01c22000 0x400>;
1250 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1251 clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
1252 clock-names = "apb", "mod";
1253 dmas = <&dma SUN4I_DMA_NORMAL 4>,
1254 <&dma SUN4I_DMA_NORMAL 4>;
1255 dma-names = "rx", "tx";
1256 status = "disabled";
1257 };
1258
1259 i2s0: i2s@1c22400 {
1260 #sound-dai-cells = <0>;
1261 compatible = "allwinner,sun4i-a10-i2s";
1262 reg = <0x01c22400 0x400>;
1263 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1264 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
1265 clock-names = "apb", "mod";
1266 dmas = <&dma SUN4I_DMA_NORMAL 3>,
1267 <&dma SUN4I_DMA_NORMAL 3>;
1268 dma-names = "rx", "tx";
1269 status = "disabled";
1270 };
1271
1272 lradc: lradc@1c22800 {
1273 compatible = "allwinner,sun4i-a10-lradc-keys";
1274 reg = <0x01c22800 0x100>;
1275 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1276 status = "disabled";
1277 };
1278
1279 codec: codec@1c22c00 {
1280 #sound-dai-cells = <0>;
1281 compatible = "allwinner,sun7i-a20-codec";
1282 reg = <0x01c22c00 0x40>;
1283 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1284 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
1285 clock-names = "apb", "codec";
1286 dmas = <&dma SUN4I_DMA_NORMAL 19>,
1287 <&dma SUN4I_DMA_NORMAL 19>;
1288 dma-names = "rx", "tx";
1289 status = "disabled";
1290 };
1291
1292 sid: eeprom@1c23800 {
1293 compatible = "allwinner,sun7i-a20-sid";
1294 reg = <0x01c23800 0x200>;
1295 };
1296
1297 i2s2: i2s@1c24400 {
1298 #sound-dai-cells = <0>;
1299 compatible = "allwinner,sun4i-a10-i2s";
1300 reg = <0x01c24400 0x400>;
1301 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1302 clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
1303 clock-names = "apb", "mod";
1304 dmas = <&dma SUN4I_DMA_NORMAL 6>,
1305 <&dma SUN4I_DMA_NORMAL 6>;
1306 dma-names = "rx", "tx";
1307 status = "disabled";
1308 };
1309
1310 rtp: rtp@1c25000 {
1311 compatible = "allwinner,sun5i-a13-ts";
1312 reg = <0x01c25000 0x100>;
1313 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1314 #thermal-sensor-cells = <0>;
1315 };
1316
1317 uart0: serial@1c28000 {
1318 compatible = "snps,dw-apb-uart";
1319 reg = <0x01c28000 0x400>;
1320 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1321 reg-shift = <2>;
1322 reg-io-width = <4>;
1323 clocks = <&ccu CLK_APB1_UART0>;
1324 status = "disabled";
1325 };
1326
1327 uart1: serial@1c28400 {
1328 compatible = "snps,dw-apb-uart";
1329 reg = <0x01c28400 0x400>;
1330 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1331 reg-shift = <2>;
1332 reg-io-width = <4>;
1333 clocks = <&ccu CLK_APB1_UART1>;
1334 status = "disabled";
1335 };
1336
1337 uart2: serial@1c28800 {
1338 compatible = "snps,dw-apb-uart";
1339 reg = <0x01c28800 0x400>;
1340 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1341 reg-shift = <2>;
1342 reg-io-width = <4>;
1343 clocks = <&ccu CLK_APB1_UART2>;
1344 status = "disabled";
1345 };
1346
1347 uart3: serial@1c28c00 {
1348 compatible = "snps,dw-apb-uart";
1349 reg = <0x01c28c00 0x400>;
1350 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1351 reg-shift = <2>;
1352 reg-io-width = <4>;
1353 clocks = <&ccu CLK_APB1_UART3>;
1354 status = "disabled";
1355 };
1356
1357 uart4: serial@1c29000 {
1358 compatible = "snps,dw-apb-uart";
1359 reg = <0x01c29000 0x400>;
1360 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1361 reg-shift = <2>;
1362 reg-io-width = <4>;
1363 clocks = <&ccu CLK_APB1_UART4>;
1364 status = "disabled";
1365 };
1366
1367 uart5: serial@1c29400 {
1368 compatible = "snps,dw-apb-uart";
1369 reg = <0x01c29400 0x400>;
1370 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1371 reg-shift = <2>;
1372 reg-io-width = <4>;
1373 clocks = <&ccu CLK_APB1_UART5>;
1374 status = "disabled";
1375 };
1376
1377 uart6: serial@1c29800 {
1378 compatible = "snps,dw-apb-uart";
1379 reg = <0x01c29800 0x400>;
1380 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1381 reg-shift = <2>;
1382 reg-io-width = <4>;
1383 clocks = <&ccu CLK_APB1_UART6>;
1384 status = "disabled";
1385 };
1386
1387 uart7: serial@1c29c00 {
1388 compatible = "snps,dw-apb-uart";
1389 reg = <0x01c29c00 0x400>;
1390 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1391 reg-shift = <2>;
1392 reg-io-width = <4>;
1393 clocks = <&ccu CLK_APB1_UART7>;
1394 status = "disabled";
1395 };
1396
1397 ps20: ps2@1c2a000 {
1398 compatible = "allwinner,sun4i-a10-ps2";
1399 reg = <0x01c2a000 0x400>;
1400 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1401 clocks = <&ccu CLK_APB1_PS20>;
1402 status = "disabled";
1403 };
1404
1405 ps21: ps2@1c2a400 {
1406 compatible = "allwinner,sun4i-a10-ps2";
1407 reg = <0x01c2a400 0x400>;
1408 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1409 clocks = <&ccu CLK_APB1_PS21>;
1410 status = "disabled";
1411 };
1412
1413 i2c0: i2c@1c2ac00 {
1414 compatible = "allwinner,sun7i-a20-i2c",
1415 "allwinner,sun4i-a10-i2c";
1416 reg = <0x01c2ac00 0x400>;
1417 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1418 clocks = <&ccu CLK_APB1_I2C0>;
1419 pinctrl-names = "default";
1420 pinctrl-0 = <&i2c0_pins>;
1421 status = "disabled";
1422 #address-cells = <1>;
1423 #size-cells = <0>;
1424 };
1425
1426 i2c1: i2c@1c2b000 {
1427 compatible = "allwinner,sun7i-a20-i2c",
1428 "allwinner,sun4i-a10-i2c";
1429 reg = <0x01c2b000 0x400>;
1430 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1431 clocks = <&ccu CLK_APB1_I2C1>;
1432 pinctrl-names = "default";
1433 pinctrl-0 = <&i2c1_pins>;
1434 status = "disabled";
1435 #address-cells = <1>;
1436 #size-cells = <0>;
1437 };
1438
1439 i2c2: i2c@1c2b400 {
1440 compatible = "allwinner,sun7i-a20-i2c",
1441 "allwinner,sun4i-a10-i2c";
1442 reg = <0x01c2b400 0x400>;
1443 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1444 clocks = <&ccu CLK_APB1_I2C2>;
1445 pinctrl-names = "default";
1446 pinctrl-0 = <&i2c2_pins>;
1447 status = "disabled";
1448 #address-cells = <1>;
1449 #size-cells = <0>;
1450 };
1451
1452 i2c3: i2c@1c2b800 {
1453 compatible = "allwinner,sun7i-a20-i2c",
1454 "allwinner,sun4i-a10-i2c";
1455 reg = <0x01c2b800 0x400>;
1456 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1457 clocks = <&ccu CLK_APB1_I2C3>;
1458 pinctrl-names = "default";
1459 pinctrl-0 = <&i2c3_pins>;
1460 status = "disabled";
1461 #address-cells = <1>;
1462 #size-cells = <0>;
1463 };
1464
1465 can0: can@1c2bc00 {
1466 compatible = "allwinner,sun7i-a20-can",
1467 "allwinner,sun4i-a10-can";
1468 reg = <0x01c2bc00 0x400>;
1469 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1470 clocks = <&ccu CLK_APB1_CAN>;
1471 status = "disabled";
1472 };
1473
1474 i2c4: i2c@1c2c000 {
1475 compatible = "allwinner,sun7i-a20-i2c",
1476 "allwinner,sun4i-a10-i2c";
1477 reg = <0x01c2c000 0x400>;
1478 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1479 clocks = <&ccu CLK_APB1_I2C4>;
1480 status = "disabled";
1481 #address-cells = <1>;
1482 #size-cells = <0>;
1483 };
1484
1485 mali: gpu@1c40000 {
1486 compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
1487 reg = <0x01c40000 0x10000>;
1488 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1489 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1490 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1491 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1492 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
1493 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1494 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1495 interrupt-names = "gp",
1496 "gpmmu",
1497 "pp0",
1498 "ppmmu0",
1499 "pp1",
1500 "ppmmu1",
1501 "pmu";
1502 clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1503 clock-names = "bus", "core";
1504 resets = <&ccu RST_GPU>;
1505
1506 assigned-clocks = <&ccu CLK_GPU>;
1507 assigned-clock-rates = <384000000>;
1508 };
1509
1510 gmac: ethernet@1c50000 {
1511 compatible = "allwinner,sun7i-a20-gmac";
1512 reg = <0x01c50000 0x10000>;
1513 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1514 interrupt-names = "macirq";
1515 clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
1516 clock-names = "stmmaceth", "allwinner_gmac_tx";
1517 snps,pbl = <2>;
1518 snps,fixed-burst;
1519 snps,force_sf_dma_mode;
1520 status = "disabled";
1521
1522 gmac_mdio: mdio {
1523 compatible = "snps,dwmac-mdio";
1524 #address-cells = <1>;
1525 #size-cells = <0>;
1526 };
1527 };
1528
1529 hstimer@1c60000 {
1530 compatible = "allwinner,sun7i-a20-hstimer";
1531 reg = <0x01c60000 0x1000>;
1532 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1536 clocks = <&ccu CLK_AHB_HSTIMER>;
1537 };
1538
1539 gic: interrupt-controller@1c81000 {
1540 compatible = "arm,gic-400";
1541 reg = <0x01c81000 0x1000>,
1542 <0x01c82000 0x2000>,
1543 <0x01c84000 0x2000>,
1544 <0x01c86000 0x2000>;
1545 interrupt-controller;
1546 #interrupt-cells = <3>;
1547 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1548 };
1549
1550 fe0: display-frontend@1e00000 {
1551 compatible = "allwinner,sun7i-a20-display-frontend";
1552 reg = <0x01e00000 0x20000>;
1553 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1554 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1555 <&ccu CLK_DRAM_DE_FE0>;
1556 clock-names = "ahb", "mod",
1557 "ram";
1558 resets = <&ccu RST_DE_FE0>;
1559
1560 ports {
1561 #address-cells = <1>;
1562 #size-cells = <0>;
1563
1564 fe0_out: port@1 {
1565 #address-cells = <1>;
1566 #size-cells = <0>;
1567 reg = <1>;
1568
1569 fe0_out_be0: endpoint@0 {
1570 reg = <0>;
1571 remote-endpoint = <&be0_in_fe0>;
1572 };
1573
1574 fe0_out_be1: endpoint@1 {
1575 reg = <1>;
1576 remote-endpoint = <&be1_in_fe0>;
1577 };
1578 };
1579 };
1580 };
1581
1582 fe1: display-frontend@1e20000 {
1583 compatible = "allwinner,sun7i-a20-display-frontend";
1584 reg = <0x01e20000 0x20000>;
1585 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1586 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1587 <&ccu CLK_DRAM_DE_FE1>;
1588 clock-names = "ahb", "mod",
1589 "ram";
1590 resets = <&ccu RST_DE_FE1>;
1591
1592 ports {
1593 #address-cells = <1>;
1594 #size-cells = <0>;
1595
1596 fe1_out: port@1 {
1597 #address-cells = <1>;
1598 #size-cells = <0>;
1599 reg = <1>;
1600
1601 fe1_out_be0: endpoint@0 {
1602 reg = <0>;
1603 remote-endpoint = <&be0_in_fe1>;
1604 };
1605
1606 fe1_out_be1: endpoint@1 {
1607 reg = <1>;
1608 remote-endpoint = <&be1_in_fe1>;
1609 };
1610 };
1611 };
1612 };
1613
1614 be1: display-backend@1e40000 {
1615 compatible = "allwinner,sun7i-a20-display-backend";
1616 reg = <0x01e40000 0x10000>;
1617 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1618 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1619 <&ccu CLK_DRAM_DE_BE1>;
1620 clock-names = "ahb", "mod",
1621 "ram";
1622 resets = <&ccu RST_DE_BE1>;
1623
1624 ports {
1625 #address-cells = <1>;
1626 #size-cells = <0>;
1627
1628 be1_in: port@0 {
1629 #address-cells = <1>;
1630 #size-cells = <0>;
1631 reg = <0>;
1632
1633 be1_in_fe0: endpoint@0 {
1634 reg = <0>;
1635 remote-endpoint = <&fe0_out_be1>;
1636 };
1637
1638 be1_in_fe1: endpoint@1 {
1639 reg = <1>;
1640 remote-endpoint = <&fe1_out_be1>;
1641 };
1642 };
1643
1644 be1_out: port@1 {
1645 #address-cells = <1>;
1646 #size-cells = <0>;
1647 reg = <1>;
1648
1649 be1_out_tcon0: endpoint@0 {
1650 reg = <0>;
1651 remote-endpoint = <&tcon0_in_be1>;
1652 };
1653
1654 be1_out_tcon1: endpoint@1 {
1655 reg = <1>;
1656 remote-endpoint = <&tcon1_in_be1>;
1657 };
1658 };
1659 };
1660 };
1661
1662 be0: display-backend@1e60000 {
1663 compatible = "allwinner,sun7i-a20-display-backend";
1664 reg = <0x01e60000 0x10000>;
1665 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1666 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1667 <&ccu CLK_DRAM_DE_BE0>;
1668 clock-names = "ahb", "mod",
1669 "ram";
1670 resets = <&ccu RST_DE_BE0>;
1671
1672 ports {
1673 #address-cells = <1>;
1674 #size-cells = <0>;
1675
1676 be0_in: port@0 {
1677 #address-cells = <1>;
1678 #size-cells = <0>;
1679 reg = <0>;
1680
1681 be0_in_fe0: endpoint@0 {
1682 reg = <0>;
1683 remote-endpoint = <&fe0_out_be0>;
1684 };
1685
1686 be0_in_fe1: endpoint@1 {
1687 reg = <1>;
1688 remote-endpoint = <&fe1_out_be0>;
1689 };
1690 };
1691
1692 be0_out: port@1 {
1693 #address-cells = <1>;
1694 #size-cells = <0>;
1695 reg = <1>;
1696
1697 be0_out_tcon0: endpoint@0 {
1698 reg = <0>;
1699 remote-endpoint = <&tcon0_in_be0>;
1700 };
1701
1702 be0_out_tcon1: endpoint@1 {
1703 reg = <1>;
1704 remote-endpoint = <&tcon1_in_be0>;
1705 };
1706 };
1707 };
1708 };
1709 };
1710 };
