0001 /*
0002 * Copyright 2013 Maxime Ripard
0003 *
0004 * Maxime Ripard <maxime.ripard@free-electrons.com>
0005 *
0006 * This file is dual-licensed: you can use it either under the terms
0007 * of the GPL or the X11 license, at your option. Note that this dual
0008 * licensing only applies to this file, and not this project as a
0009 * whole.
0010 *
0011 * a) This file is free software; you can redistribute it and/or
0012 * modify it under the terms of the GNU General Public License as
0013 * published by the Free Software Foundation; either version 2 of the
0014 * License, or (at your option) any later version.
0015 *
0016 * This file is distributed in the hope that it will be useful,
0017 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0019 * GNU General Public License for more details.
0020 *
0021 * Or, alternatively,
0022 *
0023 * b) Permission is hereby granted, free of charge, to any person
0024 * obtaining a copy of this software and associated documentation
0025 * files (the "Software"), to deal in the Software without
0026 * restriction, including without limitation the rights to use,
0027 * copy, modify, merge, publish, distribute, sublicense, and/or
0028 * sell copies of the Software, and to permit persons to whom the
0029 * Software is furnished to do so, subject to the following
0030 * conditions:
0031 *
0032 * The above copyright notice and this permission notice shall be
0033 * included in all copies or substantial portions of the Software.
0034 *
0035 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0036 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0037 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0038 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0039 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0040 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0041 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0042 * OTHER DEALINGS IN THE SOFTWARE.
0043 */
0044
0045 #include <dt-bindings/interrupt-controller/arm-gic.h>
0046 #include <dt-bindings/thermal/thermal.h>
0047
0048 #include <dt-bindings/clock/sun6i-a31-ccu.h>
0049 #include <dt-bindings/clock/sun6i-rtc.h>
0050 #include <dt-bindings/reset/sun6i-a31-ccu.h>
0051
0052 / {
0053 interrupt-parent = <&gic>;
0054 #address-cells = <1>;
0055 #size-cells = <1>;
0056
0057 aliases {
0058 ethernet0 = &gmac;
0059 };
0060
0061 chosen {
0062 #address-cells = <1>;
0063 #size-cells = <1>;
0064 ranges;
0065
0066 simplefb_hdmi: framebuffer-lcd0-hdmi {
0067 compatible = "allwinner,simple-framebuffer",
0068 "simple-framebuffer";
0069 allwinner,pipeline = "de_be0-lcd0-hdmi";
0070 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
0071 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
0072 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
0073 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
0074 status = "disabled";
0075 };
0076
0077 simplefb_lcd: framebuffer-lcd0 {
0078 compatible = "allwinner,simple-framebuffer",
0079 "simple-framebuffer";
0080 allwinner,pipeline = "de_be0-lcd0";
0081 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
0082 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
0083 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
0084 status = "disabled";
0085 };
0086 };
0087
0088 timer {
0089 compatible = "arm,armv7-timer";
0090 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0091 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0092 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
0093 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0094 clock-frequency = <24000000>;
0095 arm,cpu-registers-not-fw-configured;
0096 };
0097
0098 cpus {
0099 enable-method = "allwinner,sun6i-a31";
0100 #address-cells = <1>;
0101 #size-cells = <0>;
0102
0103 cpu0: cpu@0 {
0104 compatible = "arm,cortex-a7";
0105 device_type = "cpu";
0106 reg = <0>;
0107 clocks = <&ccu CLK_CPU>;
0108 clock-latency = <244144>; /* 8 32k periods */
0109 operating-points =
0110 /* kHz uV */
0111 <1008000 1200000>,
0112 <864000 1200000>,
0113 <720000 1100000>,
0114 <480000 1000000>;
0115 #cooling-cells = <2>;
0116 };
0117
0118 cpu1: cpu@1 {
0119 compatible = "arm,cortex-a7";
0120 device_type = "cpu";
0121 reg = <1>;
0122 clocks = <&ccu CLK_CPU>;
0123 clock-latency = <244144>; /* 8 32k periods */
0124 operating-points =
0125 /* kHz uV */
0126 <1008000 1200000>,
0127 <864000 1200000>,
0128 <720000 1100000>,
0129 <480000 1000000>;
0130 #cooling-cells = <2>;
0131 };
0132
0133 cpu2: cpu@2 {
0134 compatible = "arm,cortex-a7";
0135 device_type = "cpu";
0136 reg = <2>;
0137 clocks = <&ccu CLK_CPU>;
0138 clock-latency = <244144>; /* 8 32k periods */
0139 operating-points =
0140 /* kHz uV */
0141 <1008000 1200000>,
0142 <864000 1200000>,
0143 <720000 1100000>,
0144 <480000 1000000>;
0145 #cooling-cells = <2>;
0146 };
0147
0148 cpu3: cpu@3 {
0149 compatible = "arm,cortex-a7";
0150 device_type = "cpu";
0151 reg = <3>;
0152 clocks = <&ccu CLK_CPU>;
0153 clock-latency = <244144>; /* 8 32k periods */
0154 operating-points =
0155 /* kHz uV */
0156 <1008000 1200000>,
0157 <864000 1200000>,
0158 <720000 1100000>,
0159 <480000 1000000>;
0160 #cooling-cells = <2>;
0161 };
0162 };
0163
0164 thermal-zones {
0165 cpu-thermal {
0166 /* milliseconds */
0167 polling-delay-passive = <250>;
0168 polling-delay = <1000>;
0169 thermal-sensors = <&rtp>;
0170
0171 cooling-maps {
0172 map0 {
0173 trip = <&cpu_alert0>;
0174 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0175 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0176 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
0177 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0178 };
0179 };
0180
0181 trips {
0182 cpu_alert0: cpu_alert0 {
0183 /* milliCelsius */
0184 temperature = <70000>;
0185 hysteresis = <2000>;
0186 type = "passive";
0187 };
0188
0189 cpu_crit: cpu_crit {
0190 /* milliCelsius */
0191 temperature = <100000>;
0192 hysteresis = <2000>;
0193 type = "critical";
0194 };
0195 };
0196 };
0197 };
0198
0199 pmu {
0200 compatible = "arm,cortex-a7-pmu";
0201 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
0202 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
0203 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
0204 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
0205 };
0206
0207 clocks {
0208 #address-cells = <1>;
0209 #size-cells = <1>;
0210 ranges;
0211
0212 osc24M: clk-24M {
0213 #clock-cells = <0>;
0214 compatible = "fixed-clock";
0215 clock-frequency = <24000000>;
0216 clock-accuracy = <50000>;
0217 clock-output-names = "osc24M";
0218 };
0219
0220 osc32k: clk-32k {
0221 #clock-cells = <0>;
0222 compatible = "fixed-clock";
0223 clock-frequency = <32768>;
0224 clock-accuracy = <50000>;
0225 clock-output-names = "ext_osc32k";
0226 };
0227
0228 /*
0229 * The following two are dummy clocks, placeholders
0230 * used in the gmac_tx clock. The gmac driver will
0231 * choose one parent depending on the PHY interface
0232 * mode, using clk_set_rate auto-reparenting.
0233 *
0234 * The actual TX clock rate is not controlled by the
0235 * gmac_tx clock.
0236 */
0237 mii_phy_tx_clk: clk-mii-phy-tx {
0238 #clock-cells = <0>;
0239 compatible = "fixed-clock";
0240 clock-frequency = <25000000>;
0241 clock-output-names = "mii_phy_tx";
0242 };
0243
0244 gmac_int_tx_clk: clk-gmac-int-tx {
0245 #clock-cells = <0>;
0246 compatible = "fixed-clock";
0247 clock-frequency = <125000000>;
0248 clock-output-names = "gmac_int_tx";
0249 };
0250
0251 gmac_tx_clk: clk@1c200d0 {
0252 #clock-cells = <0>;
0253 compatible = "allwinner,sun7i-a20-gmac-clk";
0254 reg = <0x01c200d0 0x4>;
0255 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
0256 clock-output-names = "gmac_tx";
0257 };
0258 };
0259
0260 de: display-engine {
0261 compatible = "allwinner,sun6i-a31-display-engine";
0262 allwinner,pipelines = <&fe0>, <&fe1>;
0263 status = "disabled";
0264 };
0265
0266 soc {
0267 compatible = "simple-bus";
0268 #address-cells = <1>;
0269 #size-cells = <1>;
0270 ranges;
0271
0272 dma: dma-controller@1c02000 {
0273 compatible = "allwinner,sun6i-a31-dma";
0274 reg = <0x01c02000 0x1000>;
0275 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0276 clocks = <&ccu CLK_AHB1_DMA>;
0277 resets = <&ccu RST_AHB1_DMA>;
0278 #dma-cells = <1>;
0279 };
0280
0281 tcon0: lcd-controller@1c0c000 {
0282 compatible = "allwinner,sun6i-a31-tcon";
0283 reg = <0x01c0c000 0x1000>;
0284 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0285 dmas = <&dma 11>;
0286 resets = <&ccu RST_AHB1_LCD0>,
0287 <&ccu RST_AHB1_LVDS>;
0288 reset-names = "lcd",
0289 "lvds";
0290 clocks = <&ccu CLK_AHB1_LCD0>,
0291 <&ccu CLK_LCD0_CH0>,
0292 <&ccu CLK_LCD0_CH1>,
0293 <&ccu 15>;
0294 clock-names = "ahb",
0295 "tcon-ch0",
0296 "tcon-ch1",
0297 "lvds-alt";
0298 clock-output-names = "tcon0-pixel-clock";
0299 #clock-cells = <0>;
0300
0301 ports {
0302 #address-cells = <1>;
0303 #size-cells = <0>;
0304
0305 tcon0_in: port@0 {
0306 #address-cells = <1>;
0307 #size-cells = <0>;
0308 reg = <0>;
0309
0310 tcon0_in_drc0: endpoint@0 {
0311 reg = <0>;
0312 remote-endpoint = <&drc0_out_tcon0>;
0313 };
0314
0315 tcon0_in_drc1: endpoint@1 {
0316 reg = <1>;
0317 remote-endpoint = <&drc1_out_tcon0>;
0318 };
0319 };
0320
0321 tcon0_out: port@1 {
0322 #address-cells = <1>;
0323 #size-cells = <0>;
0324 reg = <1>;
0325
0326 tcon0_out_hdmi: endpoint@1 {
0327 reg = <1>;
0328 remote-endpoint = <&hdmi_in_tcon0>;
0329 allwinner,tcon-channel = <1>;
0330 };
0331 };
0332 };
0333 };
0334
0335 tcon1: lcd-controller@1c0d000 {
0336 compatible = "allwinner,sun6i-a31-tcon";
0337 reg = <0x01c0d000 0x1000>;
0338 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0339 dmas = <&dma 12>;
0340 resets = <&ccu RST_AHB1_LCD1>,
0341 <&ccu RST_AHB1_LVDS>;
0342 reset-names = "lcd", "lvds";
0343 clocks = <&ccu CLK_AHB1_LCD1>,
0344 <&ccu CLK_LCD1_CH0>,
0345 <&ccu CLK_LCD1_CH1>,
0346 <&ccu 15>;
0347 clock-names = "ahb",
0348 "tcon-ch0",
0349 "tcon-ch1",
0350 "lvds-alt";
0351 clock-output-names = "tcon1-pixel-clock";
0352 #clock-cells = <0>;
0353
0354 ports {
0355 #address-cells = <1>;
0356 #size-cells = <0>;
0357
0358 tcon1_in: port@0 {
0359 #address-cells = <1>;
0360 #size-cells = <0>;
0361 reg = <0>;
0362
0363 tcon1_in_drc0: endpoint@0 {
0364 reg = <0>;
0365 remote-endpoint = <&drc0_out_tcon1>;
0366 };
0367
0368 tcon1_in_drc1: endpoint@1 {
0369 reg = <1>;
0370 remote-endpoint = <&drc1_out_tcon1>;
0371 };
0372 };
0373
0374 tcon1_out: port@1 {
0375 #address-cells = <1>;
0376 #size-cells = <0>;
0377 reg = <1>;
0378
0379 tcon1_out_hdmi: endpoint@1 {
0380 reg = <1>;
0381 remote-endpoint = <&hdmi_in_tcon1>;
0382 allwinner,tcon-channel = <1>;
0383 };
0384 };
0385 };
0386 };
0387
0388 mmc0: mmc@1c0f000 {
0389 compatible = "allwinner,sun7i-a20-mmc";
0390 reg = <0x01c0f000 0x1000>;
0391 clocks = <&ccu CLK_AHB1_MMC0>,
0392 <&ccu CLK_MMC0>,
0393 <&ccu CLK_MMC0_OUTPUT>,
0394 <&ccu CLK_MMC0_SAMPLE>;
0395 clock-names = "ahb",
0396 "mmc",
0397 "output",
0398 "sample";
0399 resets = <&ccu RST_AHB1_MMC0>;
0400 reset-names = "ahb";
0401 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0402 pinctrl-names = "default";
0403 pinctrl-0 = <&mmc0_pins>;
0404 status = "disabled";
0405 #address-cells = <1>;
0406 #size-cells = <0>;
0407 };
0408
0409 mmc1: mmc@1c10000 {
0410 compatible = "allwinner,sun7i-a20-mmc";
0411 reg = <0x01c10000 0x1000>;
0412 clocks = <&ccu CLK_AHB1_MMC1>,
0413 <&ccu CLK_MMC1>,
0414 <&ccu CLK_MMC1_OUTPUT>,
0415 <&ccu CLK_MMC1_SAMPLE>;
0416 clock-names = "ahb",
0417 "mmc",
0418 "output",
0419 "sample";
0420 resets = <&ccu RST_AHB1_MMC1>;
0421 reset-names = "ahb";
0422 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0423 pinctrl-names = "default";
0424 pinctrl-0 = <&mmc1_pins>;
0425 status = "disabled";
0426 #address-cells = <1>;
0427 #size-cells = <0>;
0428 };
0429
0430 mmc2: mmc@1c11000 {
0431 compatible = "allwinner,sun7i-a20-mmc";
0432 reg = <0x01c11000 0x1000>;
0433 clocks = <&ccu CLK_AHB1_MMC2>,
0434 <&ccu CLK_MMC2>,
0435 <&ccu CLK_MMC2_OUTPUT>,
0436 <&ccu CLK_MMC2_SAMPLE>;
0437 clock-names = "ahb",
0438 "mmc",
0439 "output",
0440 "sample";
0441 resets = <&ccu RST_AHB1_MMC2>;
0442 reset-names = "ahb";
0443 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
0444 status = "disabled";
0445 #address-cells = <1>;
0446 #size-cells = <0>;
0447 };
0448
0449 mmc3: mmc@1c12000 {
0450 compatible = "allwinner,sun7i-a20-mmc";
0451 reg = <0x01c12000 0x1000>;
0452 clocks = <&ccu CLK_AHB1_MMC3>,
0453 <&ccu CLK_MMC3>,
0454 <&ccu CLK_MMC3_OUTPUT>,
0455 <&ccu CLK_MMC3_SAMPLE>;
0456 clock-names = "ahb",
0457 "mmc",
0458 "output",
0459 "sample";
0460 resets = <&ccu RST_AHB1_MMC3>;
0461 reset-names = "ahb";
0462 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0463 status = "disabled";
0464 #address-cells = <1>;
0465 #size-cells = <0>;
0466 };
0467
0468 hdmi: hdmi@1c16000 {
0469 compatible = "allwinner,sun6i-a31-hdmi";
0470 reg = <0x01c16000 0x1000>;
0471 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
0472 clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
0473 <&ccu CLK_HDMI_DDC>,
0474 <&ccu CLK_PLL_VIDEO0_2X>,
0475 <&ccu CLK_PLL_VIDEO1_2X>;
0476 clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
0477 resets = <&ccu RST_AHB1_HDMI>;
0478 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
0479 dmas = <&dma 13>, <&dma 13>, <&dma 14>;
0480 status = "disabled";
0481
0482 ports {
0483 #address-cells = <1>;
0484 #size-cells = <0>;
0485
0486 hdmi_in: port@0 {
0487 #address-cells = <1>;
0488 #size-cells = <0>;
0489 reg = <0>;
0490
0491 hdmi_in_tcon0: endpoint@0 {
0492 reg = <0>;
0493 remote-endpoint = <&tcon0_out_hdmi>;
0494 };
0495
0496 hdmi_in_tcon1: endpoint@1 {
0497 reg = <1>;
0498 remote-endpoint = <&tcon1_out_hdmi>;
0499 };
0500 };
0501
0502 hdmi_out: port@1 {
0503 reg = <1>;
0504 };
0505 };
0506 };
0507
0508 usb_otg: usb@1c19000 {
0509 compatible = "allwinner,sun6i-a31-musb";
0510 reg = <0x01c19000 0x0400>;
0511 clocks = <&ccu CLK_AHB1_OTG>;
0512 resets = <&ccu RST_AHB1_OTG>;
0513 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0514 interrupt-names = "mc";
0515 phys = <&usbphy 0>;
0516 phy-names = "usb";
0517 extcon = <&usbphy 0>;
0518 dr_mode = "otg";
0519 status = "disabled";
0520 };
0521
0522 usbphy: phy@1c19400 {
0523 compatible = "allwinner,sun6i-a31-usb-phy";
0524 reg = <0x01c19400 0x10>,
0525 <0x01c1a800 0x4>,
0526 <0x01c1b800 0x4>;
0527 reg-names = "phy_ctrl",
0528 "pmu1",
0529 "pmu2";
0530 clocks = <&ccu CLK_USB_PHY0>,
0531 <&ccu CLK_USB_PHY1>,
0532 <&ccu CLK_USB_PHY2>;
0533 clock-names = "usb0_phy",
0534 "usb1_phy",
0535 "usb2_phy";
0536 resets = <&ccu RST_USB_PHY0>,
0537 <&ccu RST_USB_PHY1>,
0538 <&ccu RST_USB_PHY2>;
0539 reset-names = "usb0_reset",
0540 "usb1_reset",
0541 "usb2_reset";
0542 status = "disabled";
0543 #phy-cells = <1>;
0544 };
0545
0546 ehci0: usb@1c1a000 {
0547 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
0548 reg = <0x01c1a000 0x100>;
0549 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0550 clocks = <&ccu CLK_AHB1_EHCI0>;
0551 resets = <&ccu RST_AHB1_EHCI0>;
0552 phys = <&usbphy 1>;
0553 phy-names = "usb";
0554 status = "disabled";
0555 };
0556
0557 ohci0: usb@1c1a400 {
0558 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
0559 reg = <0x01c1a400 0x100>;
0560 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0561 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
0562 resets = <&ccu RST_AHB1_OHCI0>;
0563 phys = <&usbphy 1>;
0564 phy-names = "usb";
0565 status = "disabled";
0566 };
0567
0568 ehci1: usb@1c1b000 {
0569 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
0570 reg = <0x01c1b000 0x100>;
0571 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0572 clocks = <&ccu CLK_AHB1_EHCI1>;
0573 resets = <&ccu RST_AHB1_EHCI1>;
0574 phys = <&usbphy 2>;
0575 phy-names = "usb";
0576 status = "disabled";
0577 };
0578
0579 ohci1: usb@1c1b400 {
0580 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
0581 reg = <0x01c1b400 0x100>;
0582 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0583 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
0584 resets = <&ccu RST_AHB1_OHCI1>;
0585 phys = <&usbphy 2>;
0586 phy-names = "usb";
0587 status = "disabled";
0588 };
0589
0590 ohci2: usb@1c1c400 {
0591 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
0592 reg = <0x01c1c400 0x100>;
0593 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0594 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
0595 resets = <&ccu RST_AHB1_OHCI2>;
0596 status = "disabled";
0597 };
0598
0599 ccu: clock@1c20000 {
0600 compatible = "allwinner,sun6i-a31-ccu";
0601 reg = <0x01c20000 0x400>;
0602 clocks = <&osc24M>, <&rtc CLK_OSC32K>;
0603 clock-names = "hosc", "losc";
0604 #clock-cells = <1>;
0605 #reset-cells = <1>;
0606 };
0607
0608 pio: pinctrl@1c20800 {
0609 compatible = "allwinner,sun6i-a31-pinctrl";
0610 reg = <0x01c20800 0x400>;
0611 interrupt-parent = <&r_intc>;
0612 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0613 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
0614 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
0615 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
0616 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>,
0617 <&rtc CLK_OSC32K>;
0618 clock-names = "apb", "hosc", "losc";
0619 gpio-controller;
0620 interrupt-controller;
0621 #interrupt-cells = <3>;
0622 #gpio-cells = <3>;
0623
0624 gmac_gmii_pins: gmac-gmii-pins {
0625 pins = "PA0", "PA1", "PA2", "PA3",
0626 "PA4", "PA5", "PA6", "PA7",
0627 "PA8", "PA9", "PA10", "PA11",
0628 "PA12", "PA13", "PA14", "PA15",
0629 "PA16", "PA17", "PA18", "PA19",
0630 "PA20", "PA21", "PA22", "PA23",
0631 "PA24", "PA25", "PA26", "PA27";
0632 function = "gmac";
0633 /*
0634 * data lines in GMII mode run at 125MHz and
0635 * might need a higher signal drive strength
0636 */
0637 drive-strength = <30>;
0638 };
0639
0640 gmac_mii_pins: gmac-mii-pins {
0641 pins = "PA0", "PA1", "PA2", "PA3",
0642 "PA8", "PA9", "PA11",
0643 "PA12", "PA13", "PA14", "PA19",
0644 "PA20", "PA21", "PA22", "PA23",
0645 "PA24", "PA26", "PA27";
0646 function = "gmac";
0647 };
0648
0649 gmac_rgmii_pins: gmac-rgmii-pins {
0650 pins = "PA0", "PA1", "PA2", "PA3",
0651 "PA9", "PA10", "PA11",
0652 "PA12", "PA13", "PA14", "PA19",
0653 "PA20", "PA25", "PA26", "PA27";
0654 function = "gmac";
0655 /*
0656 * data lines in RGMII mode use DDR mode
0657 * and need a higher signal drive strength
0658 */
0659 drive-strength = <40>;
0660 };
0661
0662 i2c0_pins: i2c0-pins {
0663 pins = "PH14", "PH15";
0664 function = "i2c0";
0665 };
0666
0667 i2c1_pins: i2c1-pins {
0668 pins = "PH16", "PH17";
0669 function = "i2c1";
0670 };
0671
0672 i2c2_pins: i2c2-pins {
0673 pins = "PH18", "PH19";
0674 function = "i2c2";
0675 };
0676
0677 lcd0_rgb888_pins: lcd0-rgb888-pins {
0678 pins = "PD0", "PD1", "PD2", "PD3",
0679 "PD4", "PD5", "PD6", "PD7",
0680 "PD8", "PD9", "PD10", "PD11",
0681 "PD12", "PD13", "PD14", "PD15",
0682 "PD16", "PD17", "PD18", "PD19",
0683 "PD20", "PD21", "PD22", "PD23",
0684 "PD24", "PD25", "PD26", "PD27";
0685 function = "lcd0";
0686 };
0687
0688 mmc0_pins: mmc0-pins {
0689 pins = "PF0", "PF1", "PF2",
0690 "PF3", "PF4", "PF5";
0691 function = "mmc0";
0692 drive-strength = <30>;
0693 bias-pull-up;
0694 };
0695
0696 mmc1_pins: mmc1-pins {
0697 pins = "PG0", "PG1", "PG2", "PG3",
0698 "PG4", "PG5";
0699 function = "mmc1";
0700 drive-strength = <30>;
0701 bias-pull-up;
0702 };
0703
0704 mmc2_4bit_pins: mmc2-4bit-pins {
0705 pins = "PC6", "PC7", "PC8", "PC9",
0706 "PC10", "PC11";
0707 function = "mmc2";
0708 drive-strength = <30>;
0709 bias-pull-up;
0710 };
0711
0712 mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
0713 pins = "PC6", "PC7", "PC8", "PC9",
0714 "PC10", "PC11", "PC12",
0715 "PC13", "PC14", "PC15",
0716 "PC24";
0717 function = "mmc2";
0718 drive-strength = <30>;
0719 bias-pull-up;
0720 };
0721
0722 mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins {
0723 pins = "PC6", "PC7", "PC8", "PC9",
0724 "PC10", "PC11", "PC12",
0725 "PC13", "PC14", "PC15",
0726 "PC24";
0727 function = "mmc3";
0728 drive-strength = <40>;
0729 bias-pull-up;
0730 };
0731
0732 spdif_tx_pin: spdif-tx-pin {
0733 pins = "PH28";
0734 function = "spdif";
0735 };
0736
0737 uart0_ph_pins: uart0-ph-pins {
0738 pins = "PH20", "PH21";
0739 function = "uart0";
0740 };
0741 };
0742
0743 timer@1c20c00 {
0744 compatible = "allwinner,sun4i-a10-timer";
0745 reg = <0x01c20c00 0xa0>;
0746 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0747 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0748 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
0749 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
0750 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
0751 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0752 clocks = <&osc24M>;
0753 };
0754
0755 wdt1: watchdog@1c20ca0 {
0756 compatible = "allwinner,sun6i-a31-wdt";
0757 reg = <0x01c20ca0 0x20>;
0758 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0759 clocks = <&osc24M>;
0760 };
0761
0762 spdif: spdif@1c21000 {
0763 #sound-dai-cells = <0>;
0764 compatible = "allwinner,sun6i-a31-spdif";
0765 reg = <0x01c21000 0x400>;
0766 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0767 clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
0768 resets = <&ccu RST_APB1_SPDIF>;
0769 clock-names = "apb", "spdif";
0770 dmas = <&dma 2>, <&dma 2>;
0771 dma-names = "rx", "tx";
0772 status = "disabled";
0773 };
0774
0775 i2s0: i2s@1c22000 {
0776 #sound-dai-cells = <0>;
0777 compatible = "allwinner,sun6i-a31-i2s";
0778 reg = <0x01c22000 0x400>;
0779 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0780 clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
0781 resets = <&ccu RST_APB1_DAUDIO0>;
0782 clock-names = "apb", "mod";
0783 dmas = <&dma 3>, <&dma 3>;
0784 dma-names = "rx", "tx";
0785 status = "disabled";
0786 };
0787
0788 i2s1: i2s@1c22400 {
0789 #sound-dai-cells = <0>;
0790 compatible = "allwinner,sun6i-a31-i2s";
0791 reg = <0x01c22400 0x400>;
0792 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0793 clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
0794 resets = <&ccu RST_APB1_DAUDIO1>;
0795 clock-names = "apb", "mod";
0796 dmas = <&dma 4>, <&dma 4>;
0797 dma-names = "rx", "tx";
0798 status = "disabled";
0799 };
0800
0801 lradc: lradc@1c22800 {
0802 compatible = "allwinner,sun4i-a10-lradc-keys";
0803 reg = <0x01c22800 0x100>;
0804 interrupt-parent = <&r_intc>;
0805 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
0806 status = "disabled";
0807 };
0808
0809 rtp: rtp@1c25000 {
0810 compatible = "allwinner,sun6i-a31-ts";
0811 reg = <0x01c25000 0x100>;
0812 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
0813 #thermal-sensor-cells = <0>;
0814 };
0815
0816 uart0: serial@1c28000 {
0817 compatible = "snps,dw-apb-uart";
0818 reg = <0x01c28000 0x400>;
0819 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
0820 reg-shift = <2>;
0821 reg-io-width = <4>;
0822 clocks = <&ccu CLK_APB2_UART0>;
0823 resets = <&ccu RST_APB2_UART0>;
0824 dmas = <&dma 6>, <&dma 6>;
0825 dma-names = "rx", "tx";
0826 status = "disabled";
0827 };
0828
0829 uart1: serial@1c28400 {
0830 compatible = "snps,dw-apb-uart";
0831 reg = <0x01c28400 0x400>;
0832 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0833 reg-shift = <2>;
0834 reg-io-width = <4>;
0835 clocks = <&ccu CLK_APB2_UART1>;
0836 resets = <&ccu RST_APB2_UART1>;
0837 dmas = <&dma 7>, <&dma 7>;
0838 dma-names = "rx", "tx";
0839 status = "disabled";
0840 };
0841
0842 uart2: serial@1c28800 {
0843 compatible = "snps,dw-apb-uart";
0844 reg = <0x01c28800 0x400>;
0845 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0846 reg-shift = <2>;
0847 reg-io-width = <4>;
0848 clocks = <&ccu CLK_APB2_UART2>;
0849 resets = <&ccu RST_APB2_UART2>;
0850 dmas = <&dma 8>, <&dma 8>;
0851 dma-names = "rx", "tx";
0852 status = "disabled";
0853 };
0854
0855 uart3: serial@1c28c00 {
0856 compatible = "snps,dw-apb-uart";
0857 reg = <0x01c28c00 0x400>;
0858 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0859 reg-shift = <2>;
0860 reg-io-width = <4>;
0861 clocks = <&ccu CLK_APB2_UART3>;
0862 resets = <&ccu RST_APB2_UART3>;
0863 dmas = <&dma 9>, <&dma 9>;
0864 dma-names = "rx", "tx";
0865 status = "disabled";
0866 };
0867
0868 uart4: serial@1c29000 {
0869 compatible = "snps,dw-apb-uart";
0870 reg = <0x01c29000 0x400>;
0871 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0872 reg-shift = <2>;
0873 reg-io-width = <4>;
0874 clocks = <&ccu CLK_APB2_UART4>;
0875 resets = <&ccu RST_APB2_UART4>;
0876 dmas = <&dma 10>, <&dma 10>;
0877 dma-names = "rx", "tx";
0878 status = "disabled";
0879 };
0880
0881 uart5: serial@1c29400 {
0882 compatible = "snps,dw-apb-uart";
0883 reg = <0x01c29400 0x400>;
0884 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
0885 reg-shift = <2>;
0886 reg-io-width = <4>;
0887 clocks = <&ccu CLK_APB2_UART5>;
0888 resets = <&ccu RST_APB2_UART5>;
0889 dmas = <&dma 22>, <&dma 22>;
0890 dma-names = "rx", "tx";
0891 status = "disabled";
0892 };
0893
0894 i2c0: i2c@1c2ac00 {
0895 compatible = "allwinner,sun6i-a31-i2c";
0896 reg = <0x01c2ac00 0x400>;
0897 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0898 clocks = <&ccu CLK_APB2_I2C0>;
0899 resets = <&ccu RST_APB2_I2C0>;
0900 pinctrl-names = "default";
0901 pinctrl-0 = <&i2c0_pins>;
0902 status = "disabled";
0903 #address-cells = <1>;
0904 #size-cells = <0>;
0905 };
0906
0907 i2c1: i2c@1c2b000 {
0908 compatible = "allwinner,sun6i-a31-i2c";
0909 reg = <0x01c2b000 0x400>;
0910 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0911 clocks = <&ccu CLK_APB2_I2C1>;
0912 resets = <&ccu RST_APB2_I2C1>;
0913 pinctrl-names = "default";
0914 pinctrl-0 = <&i2c1_pins>;
0915 status = "disabled";
0916 #address-cells = <1>;
0917 #size-cells = <0>;
0918 };
0919
0920 i2c2: i2c@1c2b400 {
0921 compatible = "allwinner,sun6i-a31-i2c";
0922 reg = <0x01c2b400 0x400>;
0923 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0924 clocks = <&ccu CLK_APB2_I2C2>;
0925 resets = <&ccu RST_APB2_I2C2>;
0926 pinctrl-names = "default";
0927 pinctrl-0 = <&i2c2_pins>;
0928 status = "disabled";
0929 #address-cells = <1>;
0930 #size-cells = <0>;
0931 };
0932
0933 i2c3: i2c@1c2b800 {
0934 compatible = "allwinner,sun6i-a31-i2c";
0935 reg = <0x01c2b800 0x400>;
0936 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0937 clocks = <&ccu CLK_APB2_I2C3>;
0938 resets = <&ccu RST_APB2_I2C3>;
0939 status = "disabled";
0940 #address-cells = <1>;
0941 #size-cells = <0>;
0942 };
0943
0944 gmac: ethernet@1c30000 {
0945 compatible = "allwinner,sun7i-a20-gmac";
0946 reg = <0x01c30000 0x1054>;
0947 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0948 interrupt-names = "macirq";
0949 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
0950 clock-names = "stmmaceth", "allwinner_gmac_tx";
0951 resets = <&ccu RST_AHB1_EMAC>;
0952 reset-names = "stmmaceth";
0953 snps,pbl = <2>;
0954 snps,fixed-burst;
0955 snps,force_sf_dma_mode;
0956 status = "disabled";
0957
0958 mdio: mdio {
0959 compatible = "snps,dwmac-mdio";
0960 #address-cells = <1>;
0961 #size-cells = <0>;
0962 };
0963 };
0964
0965 crypto: crypto-engine@1c15000 {
0966 compatible = "allwinner,sun6i-a31-crypto",
0967 "allwinner,sun4i-a10-crypto";
0968 reg = <0x01c15000 0x1000>;
0969 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
0970 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
0971 clock-names = "ahb", "mod";
0972 resets = <&ccu RST_AHB1_SS>;
0973 reset-names = "ahb";
0974 };
0975
0976 codec: codec@1c22c00 {
0977 #sound-dai-cells = <0>;
0978 compatible = "allwinner,sun6i-a31-codec";
0979 reg = <0x01c22c00 0x400>;
0980 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
0981 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
0982 clock-names = "apb", "codec";
0983 resets = <&ccu RST_APB1_CODEC>;
0984 dmas = <&dma 15>, <&dma 15>;
0985 dma-names = "rx", "tx";
0986 status = "disabled";
0987 };
0988
0989 timer@1c60000 {
0990 compatible = "allwinner,sun6i-a31-hstimer",
0991 "allwinner,sun7i-a20-hstimer";
0992 reg = <0x01c60000 0x1000>;
0993 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
0994 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
0995 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
0996 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
0997 clocks = <&ccu CLK_AHB1_HSTIMER>;
0998 resets = <&ccu RST_AHB1_HSTIMER>;
0999 };
1000
1001 spi0: spi@1c68000 {
1002 compatible = "allwinner,sun6i-a31-spi";
1003 reg = <0x01c68000 0x1000>;
1004 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1005 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
1006 clock-names = "ahb", "mod";
1007 dmas = <&dma 23>, <&dma 23>;
1008 dma-names = "rx", "tx";
1009 resets = <&ccu RST_AHB1_SPI0>;
1010 status = "disabled";
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1013 };
1014
1015 spi1: spi@1c69000 {
1016 compatible = "allwinner,sun6i-a31-spi";
1017 reg = <0x01c69000 0x1000>;
1018 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1019 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
1020 clock-names = "ahb", "mod";
1021 dmas = <&dma 24>, <&dma 24>;
1022 dma-names = "rx", "tx";
1023 resets = <&ccu RST_AHB1_SPI1>;
1024 status = "disabled";
1025 #address-cells = <1>;
1026 #size-cells = <0>;
1027 };
1028
1029 spi2: spi@1c6a000 {
1030 compatible = "allwinner,sun6i-a31-spi";
1031 reg = <0x01c6a000 0x1000>;
1032 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1033 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
1034 clock-names = "ahb", "mod";
1035 dmas = <&dma 25>, <&dma 25>;
1036 dma-names = "rx", "tx";
1037 resets = <&ccu RST_AHB1_SPI2>;
1038 status = "disabled";
1039 #address-cells = <1>;
1040 #size-cells = <0>;
1041 };
1042
1043 spi3: spi@1c6b000 {
1044 compatible = "allwinner,sun6i-a31-spi";
1045 reg = <0x01c6b000 0x1000>;
1046 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1047 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
1048 clock-names = "ahb", "mod";
1049 dmas = <&dma 26>, <&dma 26>;
1050 dma-names = "rx", "tx";
1051 resets = <&ccu RST_AHB1_SPI3>;
1052 status = "disabled";
1053 #address-cells = <1>;
1054 #size-cells = <0>;
1055 };
1056
1057 gic: interrupt-controller@1c81000 {
1058 compatible = "arm,gic-400";
1059 reg = <0x01c81000 0x1000>,
1060 <0x01c82000 0x2000>,
1061 <0x01c84000 0x2000>,
1062 <0x01c86000 0x2000>;
1063 interrupt-controller;
1064 #interrupt-cells = <3>;
1065 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1066 };
1067
1068 fe0: display-frontend@1e00000 {
1069 compatible = "allwinner,sun6i-a31-display-frontend";
1070 reg = <0x01e00000 0x20000>;
1071 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1072 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
1073 <&ccu CLK_DRAM_FE0>;
1074 clock-names = "ahb", "mod",
1075 "ram";
1076 resets = <&ccu RST_AHB1_FE0>;
1077
1078 ports {
1079 #address-cells = <1>;
1080 #size-cells = <0>;
1081
1082 fe0_out: port@1 {
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1085 reg = <1>;
1086
1087 fe0_out_be0: endpoint@0 {
1088 reg = <0>;
1089 remote-endpoint = <&be0_in_fe0>;
1090 };
1091
1092 fe0_out_be1: endpoint@1 {
1093 reg = <1>;
1094 remote-endpoint = <&be1_in_fe0>;
1095 };
1096 };
1097 };
1098 };
1099
1100 fe1: display-frontend@1e20000 {
1101 compatible = "allwinner,sun6i-a31-display-frontend";
1102 reg = <0x01e20000 0x20000>;
1103 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1104 clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
1105 <&ccu CLK_DRAM_FE1>;
1106 clock-names = "ahb", "mod",
1107 "ram";
1108 resets = <&ccu RST_AHB1_FE1>;
1109
1110 ports {
1111 #address-cells = <1>;
1112 #size-cells = <0>;
1113
1114 fe1_out: port@1 {
1115 #address-cells = <1>;
1116 #size-cells = <0>;
1117 reg = <1>;
1118
1119 fe1_out_be0: endpoint@0 {
1120 reg = <0>;
1121 remote-endpoint = <&be0_in_fe1>;
1122 };
1123
1124 fe1_out_be1: endpoint@1 {
1125 reg = <1>;
1126 remote-endpoint = <&be1_in_fe1>;
1127 };
1128 };
1129 };
1130 };
1131
1132 be1: display-backend@1e40000 {
1133 compatible = "allwinner,sun6i-a31-display-backend";
1134 reg = <0x01e40000 0x10000>;
1135 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1136 clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
1137 <&ccu CLK_DRAM_BE1>;
1138 clock-names = "ahb", "mod",
1139 "ram";
1140 resets = <&ccu RST_AHB1_BE1>;
1141
1142 ports {
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1145
1146 be1_in: port@0 {
1147 #address-cells = <1>;
1148 #size-cells = <0>;
1149 reg = <0>;
1150
1151 be1_in_fe0: endpoint@0 {
1152 reg = <0>;
1153 remote-endpoint = <&fe0_out_be1>;
1154 };
1155
1156 be1_in_fe1: endpoint@1 {
1157 reg = <1>;
1158 remote-endpoint = <&fe1_out_be1>;
1159 };
1160 };
1161
1162 be1_out: port@1 {
1163 #address-cells = <1>;
1164 #size-cells = <0>;
1165 reg = <1>;
1166
1167 be1_out_drc1: endpoint@1 {
1168 reg = <1>;
1169 remote-endpoint = <&drc1_in_be1>;
1170 };
1171 };
1172 };
1173 };
1174
1175 drc1: drc@1e50000 {
1176 compatible = "allwinner,sun6i-a31-drc";
1177 reg = <0x01e50000 0x10000>;
1178 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1179 clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
1180 <&ccu CLK_DRAM_DRC1>;
1181 clock-names = "ahb", "mod",
1182 "ram";
1183 resets = <&ccu RST_AHB1_DRC1>;
1184
1185 ports {
1186 #address-cells = <1>;
1187 #size-cells = <0>;
1188
1189 drc1_in: port@0 {
1190 #address-cells = <1>;
1191 #size-cells = <0>;
1192 reg = <0>;
1193
1194 drc1_in_be1: endpoint@1 {
1195 reg = <1>;
1196 remote-endpoint = <&be1_out_drc1>;
1197 };
1198 };
1199
1200 drc1_out: port@1 {
1201 #address-cells = <1>;
1202 #size-cells = <0>;
1203 reg = <1>;
1204
1205 drc1_out_tcon0: endpoint@0 {
1206 reg = <0>;
1207 remote-endpoint = <&tcon0_in_drc1>;
1208 };
1209
1210 drc1_out_tcon1: endpoint@1 {
1211 reg = <1>;
1212 remote-endpoint = <&tcon1_in_drc1>;
1213 };
1214 };
1215 };
1216 };
1217
1218 be0: display-backend@1e60000 {
1219 compatible = "allwinner,sun6i-a31-display-backend";
1220 reg = <0x01e60000 0x10000>;
1221 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1222 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
1223 <&ccu CLK_DRAM_BE0>;
1224 clock-names = "ahb", "mod",
1225 "ram";
1226 resets = <&ccu RST_AHB1_BE0>;
1227
1228 ports {
1229 #address-cells = <1>;
1230 #size-cells = <0>;
1231
1232 be0_in: port@0 {
1233 #address-cells = <1>;
1234 #size-cells = <0>;
1235 reg = <0>;
1236
1237 be0_in_fe0: endpoint@0 {
1238 reg = <0>;
1239 remote-endpoint = <&fe0_out_be0>;
1240 };
1241
1242 be0_in_fe1: endpoint@1 {
1243 reg = <1>;
1244 remote-endpoint = <&fe1_out_be0>;
1245 };
1246 };
1247
1248 be0_out: port@1 {
1249 reg = <1>;
1250
1251 be0_out_drc0: endpoint {
1252 remote-endpoint = <&drc0_in_be0>;
1253 };
1254 };
1255 };
1256 };
1257
1258 drc0: drc@1e70000 {
1259 compatible = "allwinner,sun6i-a31-drc";
1260 reg = <0x01e70000 0x10000>;
1261 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1262 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
1263 <&ccu CLK_DRAM_DRC0>;
1264 clock-names = "ahb", "mod",
1265 "ram";
1266 resets = <&ccu RST_AHB1_DRC0>;
1267
1268 ports {
1269 #address-cells = <1>;
1270 #size-cells = <0>;
1271
1272 drc0_in: port@0 {
1273 reg = <0>;
1274
1275 drc0_in_be0: endpoint {
1276 remote-endpoint = <&be0_out_drc0>;
1277 };
1278 };
1279
1280 drc0_out: port@1 {
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1283 reg = <1>;
1284
1285 drc0_out_tcon0: endpoint@0 {
1286 reg = <0>;
1287 remote-endpoint = <&tcon0_in_drc0>;
1288 };
1289
1290 drc0_out_tcon1: endpoint@1 {
1291 reg = <1>;
1292 remote-endpoint = <&tcon1_in_drc0>;
1293 };
1294 };
1295 };
1296 };
1297
1298 rtc: rtc@1f00000 {
1299 #clock-cells = <1>;
1300 compatible = "allwinner,sun6i-a31-rtc";
1301 reg = <0x01f00000 0x54>;
1302 interrupt-parent = <&r_intc>;
1303 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1304 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1305 clocks = <&osc32k>;
1306 clock-output-names = "osc32k";
1307 };
1308
1309 r_intc: interrupt-controller@1f00c00 {
1310 compatible = "allwinner,sun6i-a31-r-intc";
1311 interrupt-controller;
1312 #interrupt-cells = <3>;
1313 reg = <0x01f00c00 0x400>;
1314 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1315 };
1316
1317 prcm@1f01400 {
1318 compatible = "allwinner,sun6i-a31-prcm";
1319 reg = <0x01f01400 0x200>;
1320
1321 ar100: ar100_clk {
1322 compatible = "allwinner,sun6i-a31-ar100-clk";
1323 #clock-cells = <0>;
1324 clocks = <&rtc CLK_OSC32K>, <&osc24M>,
1325 <&ccu CLK_PLL_PERIPH>,
1326 <&ccu CLK_PLL_PERIPH>;
1327 clock-output-names = "ar100";
1328 };
1329
1330 ahb0: ahb0_clk {
1331 compatible = "fixed-factor-clock";
1332 #clock-cells = <0>;
1333 clock-div = <1>;
1334 clock-mult = <1>;
1335 clocks = <&ar100>;
1336 clock-output-names = "ahb0";
1337 };
1338
1339 apb0: apb0_clk {
1340 compatible = "allwinner,sun6i-a31-apb0-clk";
1341 #clock-cells = <0>;
1342 clocks = <&ahb0>;
1343 clock-output-names = "apb0";
1344 };
1345
1346 apb0_gates: apb0_gates_clk {
1347 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1348 #clock-cells = <1>;
1349 clocks = <&apb0>;
1350 clock-output-names = "apb0_pio", "apb0_ir",
1351 "apb0_timer", "apb0_p2wi",
1352 "apb0_uart", "apb0_1wire",
1353 "apb0_i2c";
1354 };
1355
1356 ir_clk: ir_clk {
1357 #clock-cells = <0>;
1358 compatible = "allwinner,sun4i-a10-mod0-clk";
1359 clocks = <&rtc CLK_OSC32K>, <&osc24M>;
1360 clock-output-names = "ir";
1361 };
1362
1363 apb0_rst: apb0_rst {
1364 compatible = "allwinner,sun6i-a31-clock-reset";
1365 #reset-cells = <1>;
1366 };
1367 };
1368
1369 cpucfg@1f01c00 {
1370 compatible = "allwinner,sun6i-a31-cpuconfig";
1371 reg = <0x01f01c00 0x300>;
1372 };
1373
1374 ir: ir@1f02000 {
1375 compatible = "allwinner,sun6i-a31-ir";
1376 clocks = <&apb0_gates 1>, <&ir_clk>;
1377 clock-names = "apb", "ir";
1378 resets = <&apb0_rst 1>;
1379 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1380 reg = <0x01f02000 0x40>;
1381 status = "disabled";
1382 };
1383
1384 r_pio: pinctrl@1f02c00 {
1385 compatible = "allwinner,sun6i-a31-r-pinctrl";
1386 reg = <0x01f02c00 0x400>;
1387 interrupt-parent = <&r_intc>;
1388 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1389 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1390 clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>;
1391 clock-names = "apb", "hosc", "losc";
1392 gpio-controller;
1393 interrupt-controller;
1394 #interrupt-cells = <3>;
1395 #gpio-cells = <3>;
1396
1397 s_ir_rx_pin: s-ir-rx-pin {
1398 pins = "PL4";
1399 function = "s_ir";
1400 };
1401
1402 s_p2wi_pins: s-p2wi-pins {
1403 pins = "PL0", "PL1";
1404 function = "s_p2wi";
1405 };
1406 };
1407
1408 p2wi: i2c@1f03400 {
1409 compatible = "allwinner,sun6i-a31-p2wi";
1410 reg = <0x01f03400 0x400>;
1411 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1412 clocks = <&apb0_gates 3>;
1413 clock-frequency = <100000>;
1414 resets = <&apb0_rst 3>;
1415 pinctrl-names = "default";
1416 pinctrl-0 = <&s_p2wi_pins>;
1417 status = "disabled";
1418 #address-cells = <1>;
1419 #size-cells = <0>;
1420 };
1421 };
1422 };
