0001 /*
0002 * Copyright 2012-2015 Maxime Ripard
0003 *
0004 * Maxime Ripard <maxime.ripard@free-electrons.com>
0005 *
0006 * This file is dual-licensed: you can use it either under the terms
0007 * of the GPL or the X11 license, at your option. Note that this dual
0008 * licensing only applies to this file, and not this project as a
0009 * whole.
0010 *
0011 * a) This library is free software; you can redistribute it and/or
0012 * modify it under the terms of the GNU General Public License as
0013 * published by the Free Software Foundation; either version 2 of the
0014 * License, or (at your option) any later version.
0015 *
0016 * This library is distributed in the hope that it will be useful,
0017 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0019 * GNU General Public License for more details.
0020 *
0021 * Or, alternatively,
0022 *
0023 * b) Permission is hereby granted, free of charge, to any person
0024 * obtaining a copy of this software and associated documentation
0025 * files (the "Software"), to deal in the Software without
0026 * restriction, including without limitation the rights to use,
0027 * copy, modify, merge, publish, distribute, sublicense, and/or
0028 * sell copies of the Software, and to permit persons to whom the
0029 * Software is furnished to do so, subject to the following
0030 * conditions:
0031 *
0032 * The above copyright notice and this permission notice shall be
0033 * included in all copies or substantial portions of the Software.
0034 *
0035 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0036 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0037 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0038 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0039 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0040 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0041 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0042 * OTHER DEALINGS IN THE SOFTWARE.
0043 */
0044
0045 #include <dt-bindings/clock/sun5i-ccu.h>
0046 #include <dt-bindings/dma/sun4i-a10.h>
0047 #include <dt-bindings/reset/sun5i-ccu.h>
0048
0049 / {
0050 interrupt-parent = <&intc>;
0051 #address-cells = <1>;
0052 #size-cells = <1>;
0053
0054 cpus {
0055 #address-cells = <1>;
0056 #size-cells = <0>;
0057
0058 cpu0: cpu@0 {
0059 device_type = "cpu";
0060 compatible = "arm,cortex-a8";
0061 reg = <0x0>;
0062 clocks = <&ccu CLK_CPU>;
0063 };
0064 };
0065
0066 chosen {
0067 #address-cells = <1>;
0068 #size-cells = <1>;
0069 ranges;
0070
0071 framebuffer-lcd0 {
0072 compatible = "allwinner,simple-framebuffer",
0073 "simple-framebuffer";
0074 allwinner,pipeline = "de_be0-lcd0";
0075 clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
0076 <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
0077 status = "disabled";
0078 };
0079
0080 framebuffer-lcd0-tve0 {
0081 compatible = "allwinner,simple-framebuffer",
0082 "simple-framebuffer";
0083 allwinner,pipeline = "de_be0-lcd0-tve0";
0084 clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
0085 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
0086 <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
0087 status = "disabled";
0088 };
0089 };
0090
0091 clocks {
0092 #address-cells = <1>;
0093 #size-cells = <1>;
0094 ranges;
0095
0096 osc24M: clk-24M {
0097 #clock-cells = <0>;
0098 compatible = "fixed-clock";
0099 clock-frequency = <24000000>;
0100 clock-output-names = "osc24M";
0101 };
0102
0103 osc32k: clk-32k {
0104 #clock-cells = <0>;
0105 compatible = "fixed-clock";
0106 clock-frequency = <32768>;
0107 clock-output-names = "osc32k";
0108 };
0109 };
0110
0111 reserved-memory {
0112 #address-cells = <1>;
0113 #size-cells = <1>;
0114 ranges;
0115
0116 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
0117 default-pool {
0118 compatible = "shared-dma-pool";
0119 size = <0x6000000>;
0120 alloc-ranges = <0x40000000 0x10000000>;
0121 reusable;
0122 linux,cma-default;
0123 };
0124 };
0125
0126 soc {
0127 compatible = "simple-bus";
0128 #address-cells = <1>;
0129 #size-cells = <1>;
0130 dma-ranges;
0131 ranges;
0132
0133 system-control@1c00000 {
0134 compatible = "allwinner,sun5i-a13-system-control";
0135 reg = <0x01c00000 0x30>;
0136 #address-cells = <1>;
0137 #size-cells = <1>;
0138 ranges;
0139
0140 sram_a: sram@0 {
0141 compatible = "mmio-sram";
0142 reg = <0x00000000 0xc000>;
0143 #address-cells = <1>;
0144 #size-cells = <1>;
0145 ranges = <0 0x00000000 0xc000>;
0146
0147 emac_sram: sram-section@8000 {
0148 compatible = "allwinner,sun5i-a13-sram-a3-a4",
0149 "allwinner,sun4i-a10-sram-a3-a4";
0150 reg = <0x8000 0x4000>;
0151 status = "disabled";
0152 };
0153 };
0154
0155 sram_d: sram@10000 {
0156 compatible = "mmio-sram";
0157 reg = <0x00010000 0x1000>;
0158 #address-cells = <1>;
0159 #size-cells = <1>;
0160 ranges = <0 0x00010000 0x1000>;
0161
0162 otg_sram: sram-section@0 {
0163 compatible = "allwinner,sun5i-a13-sram-d",
0164 "allwinner,sun4i-a10-sram-d";
0165 reg = <0x0000 0x1000>;
0166 status = "disabled";
0167 };
0168 };
0169
0170 sram_c: sram@1d00000 {
0171 compatible = "mmio-sram";
0172 reg = <0x01d00000 0xd0000>;
0173 #address-cells = <1>;
0174 #size-cells = <1>;
0175 ranges = <0 0x01d00000 0xd0000>;
0176
0177 ve_sram: sram-section@0 {
0178 compatible = "allwinner,sun5i-a13-sram-c1",
0179 "allwinner,sun4i-a10-sram-c1";
0180 reg = <0x000000 0x80000>;
0181 };
0182 };
0183 };
0184
0185 mbus: dram-controller@1c01000 {
0186 compatible = "allwinner,sun5i-a13-mbus";
0187 reg = <0x01c01000 0x1000>;
0188 clocks = <&ccu CLK_MBUS>;
0189 #address-cells = <1>;
0190 #size-cells = <1>;
0191 dma-ranges = <0x00000000 0x40000000 0x20000000>;
0192 #interconnect-cells = <1>;
0193 };
0194
0195 dma: dma-controller@1c02000 {
0196 compatible = "allwinner,sun4i-a10-dma";
0197 reg = <0x01c02000 0x1000>;
0198 interrupts = <27>;
0199 clocks = <&ccu CLK_AHB_DMA>;
0200 #dma-cells = <2>;
0201 };
0202
0203 nfc: nand-controller@1c03000 {
0204 compatible = "allwinner,sun4i-a10-nand";
0205 reg = <0x01c03000 0x1000>;
0206 interrupts = <37>;
0207 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
0208 clock-names = "ahb", "mod";
0209 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
0210 dma-names = "rxtx";
0211 status = "disabled";
0212 #address-cells = <1>;
0213 #size-cells = <0>;
0214 };
0215
0216 spi0: spi@1c05000 {
0217 compatible = "allwinner,sun4i-a10-spi";
0218 reg = <0x01c05000 0x1000>;
0219 interrupts = <10>;
0220 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
0221 clock-names = "ahb", "mod";
0222 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
0223 <&dma SUN4I_DMA_DEDICATED 26>;
0224 dma-names = "rx", "tx";
0225 status = "disabled";
0226 #address-cells = <1>;
0227 #size-cells = <0>;
0228 };
0229
0230 spi1: spi@1c06000 {
0231 compatible = "allwinner,sun4i-a10-spi";
0232 reg = <0x01c06000 0x1000>;
0233 interrupts = <11>;
0234 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
0235 clock-names = "ahb", "mod";
0236 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
0237 <&dma SUN4I_DMA_DEDICATED 8>;
0238 dma-names = "rx", "tx";
0239 status = "disabled";
0240 #address-cells = <1>;
0241 #size-cells = <0>;
0242 };
0243
0244 tve0: tv-encoder@1c0a000 {
0245 compatible = "allwinner,sun4i-a10-tv-encoder";
0246 reg = <0x01c0a000 0x1000>;
0247 clocks = <&ccu CLK_AHB_TVE>;
0248 resets = <&ccu RST_TVE>;
0249 status = "disabled";
0250
0251 port {
0252
0253 tve0_in_tcon0: endpoint {
0254 remote-endpoint = <&tcon0_out_tve0>;
0255 };
0256 };
0257 };
0258
0259 emac: ethernet@1c0b000 {
0260 compatible = "allwinner,sun4i-a10-emac";
0261 reg = <0x01c0b000 0x1000>;
0262 interrupts = <55>;
0263 clocks = <&ccu CLK_AHB_EMAC>;
0264 allwinner,sram = <&emac_sram 1>;
0265 status = "disabled";
0266 };
0267
0268 mdio: mdio@1c0b080 {
0269 compatible = "allwinner,sun4i-a10-mdio";
0270 reg = <0x01c0b080 0x14>;
0271 status = "disabled";
0272 #address-cells = <1>;
0273 #size-cells = <0>;
0274 };
0275
0276 tcon0: lcd-controller@1c0c000 {
0277 compatible = "allwinner,sun5i-a13-tcon";
0278 reg = <0x01c0c000 0x1000>;
0279 interrupts = <44>;
0280 dmas = <&dma SUN4I_DMA_DEDICATED 14>;
0281 resets = <&ccu RST_LCD>;
0282 reset-names = "lcd";
0283 clocks = <&ccu CLK_AHB_LCD>,
0284 <&ccu CLK_TCON_CH0>,
0285 <&ccu CLK_TCON_CH1>;
0286 clock-names = "ahb",
0287 "tcon-ch0",
0288 "tcon-ch1";
0289 clock-output-names = "tcon-pixel-clock";
0290 #clock-cells = <0>;
0291 status = "disabled";
0292
0293 ports {
0294 #address-cells = <1>;
0295 #size-cells = <0>;
0296
0297 tcon0_in: port@0 {
0298 reg = <0>;
0299
0300 tcon0_in_be0: endpoint {
0301 remote-endpoint = <&be0_out_tcon0>;
0302 };
0303 };
0304
0305 tcon0_out: port@1 {
0306 #address-cells = <1>;
0307 #size-cells = <0>;
0308 reg = <1>;
0309
0310 tcon0_out_tve0: endpoint@1 {
0311 reg = <1>;
0312 remote-endpoint = <&tve0_in_tcon0>;
0313 allwinner,tcon-channel = <1>;
0314 };
0315 };
0316 };
0317 };
0318
0319 video-codec@1c0e000 {
0320 compatible = "allwinner,sun5i-a13-video-engine";
0321 reg = <0x01c0e000 0x1000>;
0322 clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
0323 <&ccu CLK_DRAM_VE>;
0324 clock-names = "ahb", "mod", "ram";
0325 resets = <&ccu RST_VE>;
0326 interrupts = <53>;
0327 allwinner,sram = <&ve_sram 1>;
0328 };
0329
0330 mmc0: mmc@1c0f000 {
0331 compatible = "allwinner,sun5i-a13-mmc";
0332 reg = <0x01c0f000 0x1000>;
0333 clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
0334 clock-names = "ahb", "mmc";
0335 interrupts = <32>;
0336 pinctrl-names = "default";
0337 pinctrl-0 = <&mmc0_pins>;
0338 status = "disabled";
0339 #address-cells = <1>;
0340 #size-cells = <0>;
0341 };
0342
0343 mmc1: mmc@1c10000 {
0344 compatible = "allwinner,sun5i-a13-mmc";
0345 reg = <0x01c10000 0x1000>;
0346 clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
0347 clock-names = "ahb", "mmc";
0348 interrupts = <33>;
0349 status = "disabled";
0350 #address-cells = <1>;
0351 #size-cells = <0>;
0352 };
0353
0354 mmc2: mmc@1c11000 {
0355 compatible = "allwinner,sun5i-a13-mmc";
0356 reg = <0x01c11000 0x1000>;
0357 clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
0358 clock-names = "ahb", "mmc";
0359 interrupts = <34>;
0360 status = "disabled";
0361 #address-cells = <1>;
0362 #size-cells = <0>;
0363 };
0364
0365 usb_otg: usb@1c13000 {
0366 compatible = "allwinner,sun4i-a10-musb";
0367 reg = <0x01c13000 0x0400>;
0368 clocks = <&ccu CLK_AHB_OTG>;
0369 interrupts = <38>;
0370 interrupt-names = "mc";
0371 phys = <&usbphy 0>;
0372 phy-names = "usb";
0373 extcon = <&usbphy 0>;
0374 allwinner,sram = <&otg_sram 1>;
0375 dr_mode = "otg";
0376 status = "disabled";
0377 };
0378
0379 usbphy: phy@1c13400 {
0380 #phy-cells = <1>;
0381 compatible = "allwinner,sun5i-a13-usb-phy";
0382 reg = <0x01c13400 0x10>, <0x01c14800 0x4>;
0383 reg-names = "phy_ctrl", "pmu1";
0384 clocks = <&ccu CLK_USB_PHY0>;
0385 clock-names = "usb_phy";
0386 resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
0387 reset-names = "usb0_reset", "usb1_reset";
0388 status = "disabled";
0389 };
0390
0391 ehci0: usb@1c14000 {
0392 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
0393 reg = <0x01c14000 0x100>;
0394 interrupts = <39>;
0395 clocks = <&ccu CLK_AHB_EHCI>;
0396 phys = <&usbphy 1>;
0397 phy-names = "usb";
0398 status = "disabled";
0399 };
0400
0401 ohci0: usb@1c14400 {
0402 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
0403 reg = <0x01c14400 0x100>;
0404 interrupts = <40>;
0405 clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
0406 phys = <&usbphy 1>;
0407 phy-names = "usb";
0408 status = "disabled";
0409 };
0410
0411 crypto: crypto-engine@1c15000 {
0412 compatible = "allwinner,sun5i-a13-crypto",
0413 "allwinner,sun4i-a10-crypto";
0414 reg = <0x01c15000 0x1000>;
0415 interrupts = <54>;
0416 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
0417 clock-names = "ahb", "mod";
0418 };
0419
0420 spi2: spi@1c17000 {
0421 compatible = "allwinner,sun4i-a10-spi";
0422 reg = <0x01c17000 0x1000>;
0423 interrupts = <12>;
0424 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
0425 clock-names = "ahb", "mod";
0426 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
0427 <&dma SUN4I_DMA_DEDICATED 28>;
0428 dma-names = "rx", "tx";
0429 status = "disabled";
0430 #address-cells = <1>;
0431 #size-cells = <0>;
0432 };
0433
0434 ccu: clock@1c20000 {
0435 reg = <0x01c20000 0x400>;
0436 clocks = <&osc24M>, <&osc32k>;
0437 clock-names = "hosc", "losc";
0438 #clock-cells = <1>;
0439 #reset-cells = <1>;
0440 };
0441
0442 intc: interrupt-controller@1c20400 {
0443 compatible = "allwinner,sun4i-a10-ic";
0444 reg = <0x01c20400 0x400>;
0445 interrupt-controller;
0446 #interrupt-cells = <1>;
0447 };
0448
0449 pio: pinctrl@1c20800 {
0450 reg = <0x01c20800 0x400>;
0451 interrupts = <28>;
0452 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
0453 clock-names = "apb", "hosc", "losc";
0454 gpio-controller;
0455 interrupt-controller;
0456 #interrupt-cells = <3>;
0457 #gpio-cells = <3>;
0458
0459 emac_pd_pins: emac-pd-pins {
0460 pins = "PD6", "PD7", "PD10",
0461 "PD11", "PD12", "PD13", "PD14",
0462 "PD15", "PD18", "PD19", "PD20",
0463 "PD21", "PD22", "PD23", "PD24",
0464 "PD25", "PD26", "PD27";
0465 function = "emac";
0466 };
0467
0468 i2c0_pins: i2c0-pins {
0469 pins = "PB0", "PB1";
0470 function = "i2c0";
0471 };
0472
0473 i2c1_pins: i2c1-pins {
0474 pins = "PB15", "PB16";
0475 function = "i2c1";
0476 };
0477
0478 i2c2_pins: i2c2-pins {
0479 pins = "PB17", "PB18";
0480 function = "i2c2";
0481 };
0482
0483 ir0_rx_pin: ir0-rx-pin {
0484 pins = "PB4";
0485 function = "ir0";
0486 };
0487
0488 lcd_rgb565_pins: lcd-rgb565-pins {
0489 pins = "PD3", "PD4", "PD5", "PD6", "PD7",
0490 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
0491 "PD19", "PD20", "PD21", "PD22", "PD23",
0492 "PD24", "PD25", "PD26", "PD27";
0493 function = "lcd0";
0494 };
0495
0496 lcd_rgb666_pins: lcd-rgb666-pins {
0497 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
0498 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
0499 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
0500 "PD24", "PD25", "PD26", "PD27";
0501 function = "lcd0";
0502 };
0503
0504 mmc0_pins: mmc0-pins {
0505 pins = "PF0", "PF1", "PF2", "PF3",
0506 "PF4", "PF5";
0507 function = "mmc0";
0508 drive-strength = <30>;
0509 bias-pull-up;
0510 };
0511
0512 mmc2_4bit_pc_pins: mmc2-4bit-pc-pins {
0513 pins = "PC6", "PC7", "PC8", "PC9",
0514 "PC10", "PC11";
0515 function = "mmc2";
0516 drive-strength = <30>;
0517 bias-pull-up;
0518 };
0519
0520 mmc2_8bit_pins: mmc2-8bit-pins {
0521 pins = "PC6", "PC7", "PC8", "PC9",
0522 "PC10", "PC11", "PC12", "PC13",
0523 "PC14", "PC15";
0524 function = "mmc2";
0525 drive-strength = <30>;
0526 bias-pull-up;
0527 };
0528
0529 nand_pins: nand-pins {
0530 pins = "PC0", "PC1", "PC2",
0531 "PC5", "PC8", "PC9", "PC10",
0532 "PC11", "PC12", "PC13", "PC14",
0533 "PC15";
0534 function = "nand0";
0535 };
0536
0537 nand_cs0_pin: nand-cs0-pin {
0538 pins = "PC4";
0539 function = "nand0";
0540 };
0541
0542 nand_rb0_pin: nand-rb0-pin {
0543 pins = "PC6";
0544 function = "nand0";
0545 };
0546
0547 pwm0_pin: pwm0-pin {
0548 pins = "PB2";
0549 function = "pwm";
0550 };
0551
0552 spi2_pe_pins: spi2-pe-pins {
0553 pins = "PE1", "PE2", "PE3";
0554 function = "spi2";
0555 };
0556
0557 spi2_cs0_pe_pin: spi2-cs0-pe-pin {
0558 pins = "PE0";
0559 function = "spi2";
0560 };
0561
0562 uart1_pe_pins: uart1-pe-pins {
0563 pins = "PE10", "PE11";
0564 function = "uart1";
0565 };
0566
0567 uart1_pg_pins: uart1-pg-pins {
0568 pins = "PG3", "PG4";
0569 function = "uart1";
0570 };
0571
0572 uart2_pd_pins: uart2-pd-pins {
0573 pins = "PD2", "PD3";
0574 function = "uart2";
0575 };
0576
0577 uart2_cts_rts_pd_pins: uart2-cts-rts-pd-pins {
0578 pins = "PD4", "PD5";
0579 function = "uart2";
0580 };
0581
0582 uart3_pg_pins: uart3-pg-pins {
0583 pins = "PG9", "PG10";
0584 function = "uart3";
0585 };
0586
0587 uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
0588 pins = "PG11", "PG12";
0589 function = "uart3";
0590 };
0591 };
0592
0593 timer@1c20c00 {
0594 compatible = "allwinner,sun4i-a10-timer";
0595 reg = <0x01c20c00 0x90>;
0596 interrupts = <22>,
0597 <23>,
0598 <24>,
0599 <25>,
0600 <67>,
0601 <68>;
0602 clocks = <&ccu CLK_HOSC>;
0603 };
0604
0605 wdt: watchdog@1c20c90 {
0606 compatible = "allwinner,sun4i-a10-wdt";
0607 reg = <0x01c20c90 0x10>;
0608 interrupts = <24>;
0609 clocks = <&osc24M>;
0610 };
0611
0612 ir0: ir@1c21800 {
0613 compatible = "allwinner,sun4i-a10-ir";
0614 clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
0615 clock-names = "apb", "ir";
0616 interrupts = <5>;
0617 reg = <0x01c21800 0x40>;
0618 status = "disabled";
0619 };
0620
0621 lradc: lradc@1c22800 {
0622 compatible = "allwinner,sun4i-a10-lradc-keys";
0623 reg = <0x01c22800 0x100>;
0624 interrupts = <31>;
0625 status = "disabled";
0626 };
0627
0628 codec: codec@1c22c00 {
0629 #sound-dai-cells = <0>;
0630 compatible = "allwinner,sun4i-a10-codec";
0631 reg = <0x01c22c00 0x40>;
0632 interrupts = <30>;
0633 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
0634 clock-names = "apb", "codec";
0635 dmas = <&dma SUN4I_DMA_NORMAL 19>,
0636 <&dma SUN4I_DMA_NORMAL 19>;
0637 dma-names = "rx", "tx";
0638 status = "disabled";
0639 };
0640
0641 sid: eeprom@1c23800 {
0642 compatible = "allwinner,sun4i-a10-sid";
0643 reg = <0x01c23800 0x10>;
0644 };
0645
0646 rtp: rtp@1c25000 {
0647 compatible = "allwinner,sun5i-a13-ts";
0648 reg = <0x01c25000 0x100>;
0649 interrupts = <29>;
0650 #thermal-sensor-cells = <0>;
0651 };
0652
0653 uart0: serial@1c28000 {
0654 compatible = "snps,dw-apb-uart";
0655 reg = <0x01c28000 0x400>;
0656 interrupts = <1>;
0657 reg-shift = <2>;
0658 reg-io-width = <4>;
0659 clocks = <&ccu CLK_APB1_UART0>;
0660 status = "disabled";
0661 };
0662
0663 uart1: serial@1c28400 {
0664 compatible = "snps,dw-apb-uart";
0665 reg = <0x01c28400 0x400>;
0666 interrupts = <2>;
0667 reg-shift = <2>;
0668 reg-io-width = <4>;
0669 clocks = <&ccu CLK_APB1_UART1>;
0670 status = "disabled";
0671 };
0672
0673 uart2: serial@1c28800 {
0674 compatible = "snps,dw-apb-uart";
0675 reg = <0x01c28800 0x400>;
0676 interrupts = <3>;
0677 reg-shift = <2>;
0678 reg-io-width = <4>;
0679 clocks = <&ccu CLK_APB1_UART2>;
0680 status = "disabled";
0681 };
0682
0683 uart3: serial@1c28c00 {
0684 compatible = "snps,dw-apb-uart";
0685 reg = <0x01c28c00 0x400>;
0686 interrupts = <4>;
0687 reg-shift = <2>;
0688 reg-io-width = <4>;
0689 clocks = <&ccu CLK_APB1_UART3>;
0690 status = "disabled";
0691 };
0692
0693 i2c0: i2c@1c2ac00 {
0694 compatible = "allwinner,sun4i-a10-i2c";
0695 reg = <0x01c2ac00 0x400>;
0696 interrupts = <7>;
0697 clocks = <&ccu CLK_APB1_I2C0>;
0698 pinctrl-names = "default";
0699 pinctrl-0 = <&i2c0_pins>;
0700 status = "disabled";
0701 #address-cells = <1>;
0702 #size-cells = <0>;
0703 };
0704
0705 i2c1: i2c@1c2b000 {
0706 compatible = "allwinner,sun4i-a10-i2c";
0707 reg = <0x01c2b000 0x400>;
0708 interrupts = <8>;
0709 clocks = <&ccu CLK_APB1_I2C1>;
0710 pinctrl-names = "default";
0711 pinctrl-0 = <&i2c1_pins>;
0712 status = "disabled";
0713 #address-cells = <1>;
0714 #size-cells = <0>;
0715 };
0716
0717 i2c2: i2c@1c2b400 {
0718 compatible = "allwinner,sun4i-a10-i2c";
0719 reg = <0x01c2b400 0x400>;
0720 interrupts = <9>;
0721 clocks = <&ccu CLK_APB1_I2C2>;
0722 pinctrl-names = "default";
0723 pinctrl-0 = <&i2c2_pins>;
0724 status = "disabled";
0725 #address-cells = <1>;
0726 #size-cells = <0>;
0727 };
0728
0729 mali: gpu@1c40000 {
0730 compatible = "allwinner,sun4i-a10-mali", "arm,mali-400";
0731 reg = <0x01c40000 0x10000>;
0732 interrupts = <69>, <70>, <71>, <72>, <73>;
0733 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pmu";
0734 clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
0735 clock-names = "bus", "core";
0736 resets = <&ccu RST_GPU>;
0737 assigned-clocks = <&ccu CLK_GPU>;
0738 assigned-clock-rates = <320000000>;
0739 };
0740
0741 timer@1c60000 {
0742 compatible = "allwinner,sun5i-a13-hstimer";
0743 reg = <0x01c60000 0x1000>;
0744 interrupts = <82>, <83>;
0745 clocks = <&ccu CLK_AHB_HSTIMER>;
0746 };
0747
0748 fe0: display-frontend@1e00000 {
0749 compatible = "allwinner,sun5i-a13-display-frontend";
0750 reg = <0x01e00000 0x20000>;
0751 interrupts = <47>;
0752 clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
0753 <&ccu CLK_DRAM_DE_FE>;
0754 clock-names = "ahb", "mod",
0755 "ram";
0756 resets = <&ccu RST_DE_FE>;
0757 interconnects = <&mbus 19>;
0758 interconnect-names = "dma-mem";
0759 status = "disabled";
0760
0761 ports {
0762 #address-cells = <1>;
0763 #size-cells = <0>;
0764
0765 fe0_out: port@1 {
0766 reg = <1>;
0767
0768 fe0_out_be0: endpoint {
0769 remote-endpoint = <&be0_in_fe0>;
0770 };
0771 };
0772 };
0773 };
0774
0775 be0: display-backend@1e60000 {
0776 compatible = "allwinner,sun5i-a13-display-backend";
0777 reg = <0x01e60000 0x10000>;
0778 interrupts = <47>;
0779 clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
0780 <&ccu CLK_DRAM_DE_BE>;
0781 clock-names = "ahb", "mod",
0782 "ram";
0783 resets = <&ccu RST_DE_BE>;
0784 interconnects = <&mbus 18>;
0785 interconnect-names = "dma-mem";
0786 status = "disabled";
0787
0788 ports {
0789 #address-cells = <1>;
0790 #size-cells = <0>;
0791
0792 be0_in: port@0 {
0793 reg = <0>;
0794
0795 be0_in_fe0: endpoint {
0796 remote-endpoint = <&fe0_out_be0>;
0797 };
0798 };
0799
0800 be0_out: port@1 {
0801 reg = <1>;
0802
0803 be0_out_tcon0: endpoint {
0804 remote-endpoint = <&tcon0_in_be0>;
0805 };
0806 };
0807 };
0808 };
0809 };
0810 };
