0001 /*
0002 * Copyright 2012 Stefan Roese
0003 * Stefan Roese <sr@denx.de>
0004 *
0005 * This file is dual-licensed: you can use it either under the terms
0006 * of the GPL or the X11 license, at your option. Note that this dual
0007 * licensing only applies to this file, and not this project as a
0008 * whole.
0009 *
0010 * a) This library is free software; you can redistribute it and/or
0011 * modify it under the terms of the GNU General Public License as
0012 * published by the Free Software Foundation; either version 2 of the
0013 * License, or (at your option) any later version.
0014 *
0015 * This library is distributed in the hope that it will be useful,
0016 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0017 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0018 * GNU General Public License for more details.
0019 *
0020 * Or, alternatively,
0021 *
0022 * b) Permission is hereby granted, free of charge, to any person
0023 * obtaining a copy of this software and associated documentation
0024 * files (the "Software"), to deal in the Software without
0025 * restriction, including without limitation the rights to use,
0026 * copy, modify, merge, publish, distribute, sublicense, and/or
0027 * sell copies of the Software, and to permit persons to whom the
0028 * Software is furnished to do so, subject to the following
0029 * conditions:
0030 *
0031 * The above copyright notice and this permission notice shall be
0032 * included in all copies or substantial portions of the Software.
0033 *
0034 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0035 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0036 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0037 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0038 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0039 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0040 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0041 * OTHER DEALINGS IN THE SOFTWARE.
0042 */
0043
0044 #include <dt-bindings/thermal/thermal.h>
0045 #include <dt-bindings/dma/sun4i-a10.h>
0046 #include <dt-bindings/clock/sun4i-a10-ccu.h>
0047 #include <dt-bindings/reset/sun4i-a10-ccu.h>
0048
0049 / {
0050 #address-cells = <1>;
0051 #size-cells = <1>;
0052 interrupt-parent = <&intc>;
0053
0054 aliases {
0055 ethernet0 = &emac;
0056 };
0057
0058 chosen {
0059 #address-cells = <1>;
0060 #size-cells = <1>;
0061 ranges;
0062
0063 framebuffer-lcd0-hdmi {
0064 compatible = "allwinner,simple-framebuffer",
0065 "simple-framebuffer";
0066 allwinner,pipeline = "de_be0-lcd0-hdmi";
0067 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
0068 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
0069 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>;
0070 status = "disabled";
0071 };
0072
0073 framebuffer-fe0-lcd0-hdmi {
0074 compatible = "allwinner,simple-framebuffer",
0075 "simple-framebuffer";
0076 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
0077 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
0078 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
0079 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
0080 <&ccu CLK_TCON0_CH1>, <&ccu CLK_HDMI>,
0081 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
0082 status = "disabled";
0083 };
0084
0085 framebuffer-fe0-lcd0 {
0086 compatible = "allwinner,simple-framebuffer",
0087 "simple-framebuffer";
0088 allwinner,pipeline = "de_fe0-de_be0-lcd0";
0089 clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
0090 <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_BE0>,
0091 <&ccu CLK_DE_FE0>, <&ccu CLK_TCON0_CH0>,
0092 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
0093 status = "disabled";
0094 };
0095
0096 framebuffer-fe0-lcd0-tve0 {
0097 compatible = "allwinner,simple-framebuffer",
0098 "simple-framebuffer";
0099 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
0100 clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
0101 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_AHB_DE_FE0>,
0102 <&ccu CLK_DE_BE0>, <&ccu CLK_DE_FE0>,
0103 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_TVE0>,
0104 <&ccu CLK_DRAM_DE_FE0>, <&ccu CLK_DRAM_DE_BE0>;
0105 status = "disabled";
0106 };
0107 };
0108
0109 cpus {
0110 #address-cells = <1>;
0111 #size-cells = <0>;
0112 cpu0: cpu@0 {
0113 device_type = "cpu";
0114 compatible = "arm,cortex-a8";
0115 reg = <0x0>;
0116 clocks = <&ccu CLK_CPU>;
0117 clock-latency = <244144>; /* 8 32k periods */
0118 operating-points =
0119 /* kHz uV */
0120 <1008000 1400000>,
0121 <912000 1350000>,
0122 <864000 1300000>,
0123 <624000 1250000>;
0124 #cooling-cells = <2>;
0125 };
0126 };
0127
0128 thermal-zones {
0129 cpu-thermal {
0130 /* milliseconds */
0131 polling-delay-passive = <250>;
0132 polling-delay = <1000>;
0133 thermal-sensors = <&rtp>;
0134
0135 cooling-maps {
0136 map0 {
0137 trip = <&cpu_alert0>;
0138 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0139 };
0140 };
0141
0142 trips {
0143 cpu_alert0: cpu-alert0 {
0144 /* milliCelsius */
0145 temperature = <85000>;
0146 hysteresis = <2000>;
0147 type = "passive";
0148 };
0149
0150 cpu_crit: cpu-crit {
0151 /* milliCelsius */
0152 temperature = <100000>;
0153 hysteresis = <2000>;
0154 type = "critical";
0155 };
0156 };
0157 };
0158 };
0159
0160 clocks {
0161 #address-cells = <1>;
0162 #size-cells = <1>;
0163 ranges;
0164
0165 osc24M: clk-24M {
0166 #clock-cells = <0>;
0167 compatible = "fixed-clock";
0168 clock-frequency = <24000000>;
0169 clock-output-names = "osc24M";
0170 };
0171
0172 osc32k: clk-32k {
0173 #clock-cells = <0>;
0174 compatible = "fixed-clock";
0175 clock-frequency = <32768>;
0176 clock-output-names = "osc32k";
0177 };
0178 };
0179
0180 de: display-engine {
0181 compatible = "allwinner,sun4i-a10-display-engine";
0182 allwinner,pipelines = <&fe0>, <&fe1>;
0183 status = "disabled";
0184 };
0185
0186 pmu {
0187 compatible = "arm,cortex-a8-pmu";
0188 interrupts = <3>;
0189 };
0190
0191 reserved-memory {
0192 #address-cells = <1>;
0193 #size-cells = <1>;
0194 ranges;
0195
0196 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
0197 default-pool {
0198 compatible = "shared-dma-pool";
0199 size = <0x6000000>;
0200 alloc-ranges = <0x40000000 0x10000000>;
0201 reusable;
0202 linux,cma-default;
0203 };
0204 };
0205
0206 soc {
0207 compatible = "simple-bus";
0208 #address-cells = <1>;
0209 #size-cells = <1>;
0210 ranges;
0211
0212 system-control@1c00000 {
0213 compatible = "allwinner,sun4i-a10-system-control";
0214 reg = <0x01c00000 0x30>;
0215 #address-cells = <1>;
0216 #size-cells = <1>;
0217 ranges;
0218
0219 sram_a: sram@0 {
0220 compatible = "mmio-sram";
0221 reg = <0x00000000 0xc000>;
0222 #address-cells = <1>;
0223 #size-cells = <1>;
0224 ranges = <0 0x00000000 0xc000>;
0225
0226 emac_sram: sram-section@8000 {
0227 compatible = "allwinner,sun4i-a10-sram-a3-a4";
0228 reg = <0x8000 0x4000>;
0229 status = "disabled";
0230 };
0231 };
0232
0233 sram_d: sram@10000 {
0234 compatible = "mmio-sram";
0235 reg = <0x00010000 0x1000>;
0236 #address-cells = <1>;
0237 #size-cells = <1>;
0238 ranges = <0 0x00010000 0x1000>;
0239
0240 otg_sram: sram-section@0 {
0241 compatible = "allwinner,sun4i-a10-sram-d";
0242 reg = <0x0000 0x1000>;
0243 status = "disabled";
0244 };
0245 };
0246
0247 sram_c: sram@1d00000 {
0248 compatible = "mmio-sram";
0249 reg = <0x01d00000 0xd0000>;
0250 #address-cells = <1>;
0251 #size-cells = <1>;
0252 ranges = <0 0x01d00000 0xd0000>;
0253
0254 ve_sram: sram-section@0 {
0255 compatible = "allwinner,sun4i-a10-sram-c1";
0256 reg = <0x000000 0x80000>;
0257 };
0258 };
0259 };
0260
0261 dma: dma-controller@1c02000 {
0262 compatible = "allwinner,sun4i-a10-dma";
0263 reg = <0x01c02000 0x1000>;
0264 interrupts = <27>;
0265 clocks = <&ccu CLK_AHB_DMA>;
0266 #dma-cells = <2>;
0267 };
0268
0269 nfc: nand-controller@1c03000 {
0270 compatible = "allwinner,sun4i-a10-nand";
0271 reg = <0x01c03000 0x1000>;
0272 interrupts = <37>;
0273 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
0274 clock-names = "ahb", "mod";
0275 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
0276 dma-names = "rxtx";
0277 status = "disabled";
0278 #address-cells = <1>;
0279 #size-cells = <0>;
0280 };
0281
0282 spi0: spi@1c05000 {
0283 compatible = "allwinner,sun4i-a10-spi";
0284 reg = <0x01c05000 0x1000>;
0285 interrupts = <10>;
0286 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
0287 clock-names = "ahb", "mod";
0288 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
0289 <&dma SUN4I_DMA_DEDICATED 26>;
0290 dma-names = "rx", "tx";
0291 status = "disabled";
0292 #address-cells = <1>;
0293 #size-cells = <0>;
0294 };
0295
0296 spi1: spi@1c06000 {
0297 compatible = "allwinner,sun4i-a10-spi";
0298 reg = <0x01c06000 0x1000>;
0299 interrupts = <11>;
0300 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
0301 clock-names = "ahb", "mod";
0302 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
0303 <&dma SUN4I_DMA_DEDICATED 8>;
0304 dma-names = "rx", "tx";
0305 pinctrl-names = "default";
0306 pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>;
0307 status = "disabled";
0308 #address-cells = <1>;
0309 #size-cells = <0>;
0310 };
0311
0312 emac: ethernet@1c0b000 {
0313 compatible = "allwinner,sun4i-a10-emac";
0314 reg = <0x01c0b000 0x1000>;
0315 interrupts = <55>;
0316 clocks = <&ccu CLK_AHB_EMAC>;
0317 allwinner,sram = <&emac_sram 1>;
0318 pinctrl-names = "default";
0319 pinctrl-0 = <&emac_pins>;
0320 status = "disabled";
0321 };
0322
0323 mdio: mdio@1c0b080 {
0324 compatible = "allwinner,sun4i-a10-mdio";
0325 reg = <0x01c0b080 0x14>;
0326 status = "disabled";
0327 #address-cells = <1>;
0328 #size-cells = <0>;
0329 };
0330
0331 tcon0: lcd-controller@1c0c000 {
0332 compatible = "allwinner,sun4i-a10-tcon";
0333 reg = <0x01c0c000 0x1000>;
0334 interrupts = <44>;
0335 resets = <&ccu RST_TCON0>;
0336 reset-names = "lcd";
0337 clocks = <&ccu CLK_AHB_LCD0>,
0338 <&ccu CLK_TCON0_CH0>,
0339 <&ccu CLK_TCON0_CH1>;
0340 clock-names = "ahb",
0341 "tcon-ch0",
0342 "tcon-ch1";
0343 clock-output-names = "tcon0-pixel-clock";
0344 #clock-cells = <0>;
0345 dmas = <&dma SUN4I_DMA_DEDICATED 14>;
0346
0347 ports {
0348 #address-cells = <1>;
0349 #size-cells = <0>;
0350
0351 tcon0_in: port@0 {
0352 #address-cells = <1>;
0353 #size-cells = <0>;
0354 reg = <0>;
0355
0356 tcon0_in_be0: endpoint@0 {
0357 reg = <0>;
0358 remote-endpoint = <&be0_out_tcon0>;
0359 };
0360
0361 tcon0_in_be1: endpoint@1 {
0362 reg = <1>;
0363 remote-endpoint = <&be1_out_tcon0>;
0364 };
0365 };
0366
0367 tcon0_out: port@1 {
0368 #address-cells = <1>;
0369 #size-cells = <0>;
0370 reg = <1>;
0371
0372 tcon0_out_hdmi: endpoint@1 {
0373 reg = <1>;
0374 remote-endpoint = <&hdmi_in_tcon0>;
0375 allwinner,tcon-channel = <1>;
0376 };
0377 };
0378 };
0379 };
0380
0381 tcon1: lcd-controller@1c0d000 {
0382 compatible = "allwinner,sun4i-a10-tcon";
0383 reg = <0x01c0d000 0x1000>;
0384 interrupts = <45>;
0385 resets = <&ccu RST_TCON1>;
0386 reset-names = "lcd";
0387 clocks = <&ccu CLK_AHB_LCD1>,
0388 <&ccu CLK_TCON1_CH0>,
0389 <&ccu CLK_TCON1_CH1>;
0390 clock-names = "ahb",
0391 "tcon-ch0",
0392 "tcon-ch1";
0393 clock-output-names = "tcon1-pixel-clock";
0394 #clock-cells = <0>;
0395 dmas = <&dma SUN4I_DMA_DEDICATED 15>;
0396
0397 ports {
0398 #address-cells = <1>;
0399 #size-cells = <0>;
0400
0401 tcon1_in: port@0 {
0402 #address-cells = <1>;
0403 #size-cells = <0>;
0404 reg = <0>;
0405
0406 tcon1_in_be0: endpoint@0 {
0407 reg = <0>;
0408 remote-endpoint = <&be0_out_tcon1>;
0409 };
0410
0411 tcon1_in_be1: endpoint@1 {
0412 reg = <1>;
0413 remote-endpoint = <&be1_out_tcon1>;
0414 };
0415 };
0416
0417 tcon1_out: port@1 {
0418 #address-cells = <1>;
0419 #size-cells = <0>;
0420 reg = <1>;
0421
0422 tcon1_out_hdmi: endpoint@1 {
0423 reg = <1>;
0424 remote-endpoint = <&hdmi_in_tcon1>;
0425 allwinner,tcon-channel = <1>;
0426 };
0427 };
0428 };
0429 };
0430
0431 video-codec@1c0e000 {
0432 compatible = "allwinner,sun4i-a10-video-engine";
0433 reg = <0x01c0e000 0x1000>;
0434 clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
0435 <&ccu CLK_DRAM_VE>;
0436 clock-names = "ahb", "mod", "ram";
0437 resets = <&ccu RST_VE>;
0438 interrupts = <53>;
0439 allwinner,sram = <&ve_sram 1>;
0440 };
0441
0442 mmc0: mmc@1c0f000 {
0443 compatible = "allwinner,sun4i-a10-mmc";
0444 reg = <0x01c0f000 0x1000>;
0445 clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
0446 clock-names = "ahb", "mmc";
0447 interrupts = <32>;
0448 pinctrl-names = "default";
0449 pinctrl-0 = <&mmc0_pins>;
0450 status = "disabled";
0451 #address-cells = <1>;
0452 #size-cells = <0>;
0453 };
0454
0455 mmc1: mmc@1c10000 {
0456 compatible = "allwinner,sun4i-a10-mmc";
0457 reg = <0x01c10000 0x1000>;
0458 clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
0459 clock-names = "ahb", "mmc";
0460 interrupts = <33>;
0461 status = "disabled";
0462 #address-cells = <1>;
0463 #size-cells = <0>;
0464 };
0465
0466 mmc2: mmc@1c11000 {
0467 compatible = "allwinner,sun4i-a10-mmc";
0468 reg = <0x01c11000 0x1000>;
0469 clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
0470 clock-names = "ahb", "mmc";
0471 interrupts = <34>;
0472 status = "disabled";
0473 #address-cells = <1>;
0474 #size-cells = <0>;
0475 };
0476
0477 mmc3: mmc@1c12000 {
0478 compatible = "allwinner,sun4i-a10-mmc";
0479 reg = <0x01c12000 0x1000>;
0480 clocks = <&ccu CLK_AHB_MMC3>, <&ccu CLK_MMC3>;
0481 clock-names = "ahb", "mmc";
0482 interrupts = <35>;
0483 status = "disabled";
0484 #address-cells = <1>;
0485 #size-cells = <0>;
0486 };
0487
0488 usb_otg: usb@1c13000 {
0489 compatible = "allwinner,sun4i-a10-musb";
0490 reg = <0x01c13000 0x0400>;
0491 clocks = <&ccu CLK_AHB_OTG>;
0492 interrupts = <38>;
0493 interrupt-names = "mc";
0494 phys = <&usbphy 0>;
0495 phy-names = "usb";
0496 extcon = <&usbphy 0>;
0497 allwinner,sram = <&otg_sram 1>;
0498 dr_mode = "otg";
0499 status = "disabled";
0500 };
0501
0502 usbphy: phy@1c13400 {
0503 #phy-cells = <1>;
0504 compatible = "allwinner,sun4i-a10-usb-phy";
0505 reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
0506 reg-names = "phy_ctrl", "pmu1", "pmu2";
0507 clocks = <&ccu CLK_USB_PHY>;
0508 clock-names = "usb_phy";
0509 resets = <&ccu RST_USB_PHY0>,
0510 <&ccu RST_USB_PHY1>,
0511 <&ccu RST_USB_PHY2>;
0512 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
0513 status = "disabled";
0514 };
0515
0516 ehci0: usb@1c14000 {
0517 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
0518 reg = <0x01c14000 0x100>;
0519 interrupts = <39>;
0520 clocks = <&ccu CLK_AHB_EHCI0>;
0521 phys = <&usbphy 1>;
0522 phy-names = "usb";
0523 status = "disabled";
0524 };
0525
0526 ohci0: usb@1c14400 {
0527 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
0528 reg = <0x01c14400 0x100>;
0529 interrupts = <64>;
0530 clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
0531 phys = <&usbphy 1>;
0532 phy-names = "usb";
0533 status = "disabled";
0534 };
0535
0536 crypto: crypto-engine@1c15000 {
0537 compatible = "allwinner,sun4i-a10-crypto";
0538 reg = <0x01c15000 0x1000>;
0539 interrupts = <86>;
0540 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
0541 clock-names = "ahb", "mod";
0542 };
0543
0544 hdmi: hdmi@1c16000 {
0545 compatible = "allwinner,sun4i-a10-hdmi";
0546 reg = <0x01c16000 0x1000>;
0547 interrupts = <58>;
0548 clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
0549 <&ccu CLK_PLL_VIDEO0_2X>,
0550 <&ccu CLK_PLL_VIDEO1_2X>;
0551 clock-names = "ahb", "mod", "pll-0", "pll-1";
0552 dmas = <&dma SUN4I_DMA_NORMAL 16>,
0553 <&dma SUN4I_DMA_NORMAL 16>,
0554 <&dma SUN4I_DMA_DEDICATED 24>;
0555 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
0556 status = "disabled";
0557
0558 ports {
0559 #address-cells = <1>;
0560 #size-cells = <0>;
0561
0562 hdmi_in: port@0 {
0563 #address-cells = <1>;
0564 #size-cells = <0>;
0565 reg = <0>;
0566
0567 hdmi_in_tcon0: endpoint@0 {
0568 reg = <0>;
0569 remote-endpoint = <&tcon0_out_hdmi>;
0570 };
0571
0572 hdmi_in_tcon1: endpoint@1 {
0573 reg = <1>;
0574 remote-endpoint = <&tcon1_out_hdmi>;
0575 };
0576 };
0577
0578 hdmi_out: port@1 {
0579 reg = <1>;
0580 };
0581 };
0582 };
0583
0584 spi2: spi@1c17000 {
0585 compatible = "allwinner,sun4i-a10-spi";
0586 reg = <0x01c17000 0x1000>;
0587 interrupts = <12>;
0588 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
0589 clock-names = "ahb", "mod";
0590 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
0591 <&dma SUN4I_DMA_DEDICATED 28>;
0592 dma-names = "rx", "tx";
0593 status = "disabled";
0594 #address-cells = <1>;
0595 #size-cells = <0>;
0596 };
0597
0598 ahci: sata@1c18000 {
0599 compatible = "allwinner,sun4i-a10-ahci";
0600 reg = <0x01c18000 0x1000>;
0601 interrupts = <56>;
0602 clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
0603 status = "disabled";
0604 };
0605
0606 ehci1: usb@1c1c000 {
0607 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
0608 reg = <0x01c1c000 0x100>;
0609 interrupts = <40>;
0610 clocks = <&ccu CLK_AHB_EHCI1>;
0611 phys = <&usbphy 2>;
0612 phy-names = "usb";
0613 status = "disabled";
0614 };
0615
0616 ohci1: usb@1c1c400 {
0617 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
0618 reg = <0x01c1c400 0x100>;
0619 interrupts = <65>;
0620 clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
0621 phys = <&usbphy 2>;
0622 phy-names = "usb";
0623 status = "disabled";
0624 };
0625
0626 csi1: csi@1c1d000 {
0627 compatible = "allwinner,sun4i-a10-csi1";
0628 reg = <0x01c1d000 0x1000>;
0629 interrupts = <43>;
0630 clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
0631 clock-names = "bus", "ram";
0632 resets = <&ccu RST_CSI1>;
0633 status = "disabled";
0634 };
0635
0636 spi3: spi@1c1f000 {
0637 compatible = "allwinner,sun4i-a10-spi";
0638 reg = <0x01c1f000 0x1000>;
0639 interrupts = <50>;
0640 clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
0641 clock-names = "ahb", "mod";
0642 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
0643 <&dma SUN4I_DMA_DEDICATED 30>;
0644 dma-names = "rx", "tx";
0645 status = "disabled";
0646 #address-cells = <1>;
0647 #size-cells = <0>;
0648 };
0649
0650 ccu: clock@1c20000 {
0651 compatible = "allwinner,sun4i-a10-ccu";
0652 reg = <0x01c20000 0x400>;
0653 clocks = <&osc24M>, <&osc32k>;
0654 clock-names = "hosc", "losc";
0655 #clock-cells = <1>;
0656 #reset-cells = <1>;
0657 };
0658
0659 intc: interrupt-controller@1c20400 {
0660 compatible = "allwinner,sun4i-a10-ic";
0661 reg = <0x01c20400 0x400>;
0662 interrupt-controller;
0663 #interrupt-cells = <1>;
0664 };
0665
0666 pio: pinctrl@1c20800 {
0667 compatible = "allwinner,sun4i-a10-pinctrl";
0668 reg = <0x01c20800 0x400>;
0669 interrupts = <28>;
0670 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
0671 clock-names = "apb", "hosc", "losc";
0672 gpio-controller;
0673 interrupt-controller;
0674 #interrupt-cells = <3>;
0675 #gpio-cells = <3>;
0676
0677 can0_ph_pins: can0-ph-pins {
0678 pins = "PH20", "PH21";
0679 function = "can";
0680 };
0681
0682 /omit-if-no-ref/
0683 csi1_8bits_pg_pins: csi1-8bits-pg-pins {
0684 pins = "PG0", "PG2", "PG3", "PG4", "PG5",
0685 "PG6", "PG7", "PG8", "PG9", "PG10",
0686 "PG11";
0687 function = "csi1";
0688 };
0689
0690 /omit-if-no-ref/
0691 csi1_24bits_ph_pins: csi1-24bits-ph-pins {
0692 pins = "PH0", "PH1", "PH2", "PH3", "PH4",
0693 "PH5", "PH6", "PH7", "PH8", "PH9",
0694 "PH10", "PH11", "PH12", "PH13", "PH14",
0695 "PH15", "PH16", "PH17", "PH18", "PH19",
0696 "PH20", "PH21", "PH22", "PH23", "PH24",
0697 "PH25", "PH26", "PH27";
0698 function = "csi1";
0699 };
0700
0701 /omit-if-no-ref/
0702 csi1_clk_pg_pin: csi1-clk-pg-pin {
0703 pins = "PG1";
0704 function = "csi1";
0705 };
0706
0707 emac_pins: emac0-pins {
0708 pins = "PA0", "PA1", "PA2",
0709 "PA3", "PA4", "PA5", "PA6",
0710 "PA7", "PA8", "PA9", "PA10",
0711 "PA11", "PA12", "PA13", "PA14",
0712 "PA15", "PA16";
0713 function = "emac";
0714 };
0715
0716 i2c0_pins: i2c0-pins {
0717 pins = "PB0", "PB1";
0718 function = "i2c0";
0719 };
0720
0721 i2c1_pins: i2c1-pins {
0722 pins = "PB18", "PB19";
0723 function = "i2c1";
0724 };
0725
0726 i2c2_pins: i2c2-pins {
0727 pins = "PB20", "PB21";
0728 function = "i2c2";
0729 };
0730
0731 ir0_rx_pins: ir0-rx-pin {
0732 pins = "PB4";
0733 function = "ir0";
0734 };
0735
0736 ir0_tx_pins: ir0-tx-pin {
0737 pins = "PB3";
0738 function = "ir0";
0739 };
0740
0741 ir1_rx_pins: ir1-rx-pin {
0742 pins = "PB23";
0743 function = "ir1";
0744 };
0745
0746 ir1_tx_pins: ir1-tx-pin {
0747 pins = "PB22";
0748 function = "ir1";
0749 };
0750
0751 mmc0_pins: mmc0-pins {
0752 pins = "PF0", "PF1", "PF2",
0753 "PF3", "PF4", "PF5";
0754 function = "mmc0";
0755 drive-strength = <30>;
0756 bias-pull-up;
0757 };
0758
0759 ps2_ch0_pins: ps2-ch0-pins {
0760 pins = "PI20", "PI21";
0761 function = "ps2";
0762 };
0763
0764 ps2_ch1_ph_pins: ps2-ch1-ph-pins {
0765 pins = "PH12", "PH13";
0766 function = "ps2";
0767 };
0768
0769 pwm0_pin: pwm0-pin {
0770 pins = "PB2";
0771 function = "pwm";
0772 };
0773
0774 pwm1_pin: pwm1-pin {
0775 pins = "PI3";
0776 function = "pwm";
0777 };
0778
0779 spdif_tx_pin: spdif-tx-pin {
0780 pins = "PB13";
0781 function = "spdif";
0782 bias-pull-up;
0783 };
0784
0785 spi0_pi_pins: spi0-pi-pins {
0786 pins = "PI11", "PI12", "PI13";
0787 function = "spi0";
0788 };
0789
0790 spi0_cs0_pi_pin: spi0-cs0-pi-pin {
0791 pins = "PI10";
0792 function = "spi0";
0793 };
0794
0795 spi1_pins: spi1-pins {
0796 pins = "PI17", "PI18", "PI19";
0797 function = "spi1";
0798 };
0799
0800 spi1_cs0_pin: spi1-cs0-pin {
0801 pins = "PI16";
0802 function = "spi1";
0803 };
0804
0805 spi2_pb_pins: spi2-pb-pins {
0806 pins = "PB15", "PB16", "PB17";
0807 function = "spi2";
0808 };
0809
0810 spi2_pc_pins: spi2-pc-pins {
0811 pins = "PC20", "PC21", "PC22";
0812 function = "spi2";
0813 };
0814
0815 spi2_cs0_pb_pin: spi2-cs0-pb-pin {
0816 pins = "PB14";
0817 function = "spi2";
0818 };
0819
0820 spi2_cs0_pc_pins: spi2-cs0-pc-pin {
0821 pins = "PC19";
0822 function = "spi2";
0823 };
0824
0825 uart0_pb_pins: uart0-pb-pins {
0826 pins = "PB22", "PB23";
0827 function = "uart0";
0828 };
0829
0830 uart0_pf_pins: uart0-pf-pins {
0831 pins = "PF2", "PF4";
0832 function = "uart0";
0833 };
0834
0835 uart1_pins: uart1-pins {
0836 pins = "PA10", "PA11";
0837 function = "uart1";
0838 };
0839 };
0840
0841 timer@1c20c00 {
0842 compatible = "allwinner,sun4i-a10-timer";
0843 reg = <0x01c20c00 0x90>;
0844 interrupts = <22>,
0845 <23>,
0846 <24>,
0847 <25>,
0848 <67>,
0849 <68>;
0850 clocks = <&osc24M>;
0851 };
0852
0853 wdt: watchdog@1c20c90 {
0854 compatible = "allwinner,sun4i-a10-wdt";
0855 reg = <0x01c20c90 0x10>;
0856 interrupts = <24>;
0857 clocks = <&osc24M>;
0858 };
0859
0860 rtc: rtc@1c20d00 {
0861 compatible = "allwinner,sun4i-a10-rtc";
0862 reg = <0x01c20d00 0x20>;
0863 interrupts = <24>;
0864 };
0865
0866 pwm: pwm@1c20e00 {
0867 compatible = "allwinner,sun4i-a10-pwm";
0868 reg = <0x01c20e00 0xc>;
0869 clocks = <&osc24M>;
0870 #pwm-cells = <3>;
0871 status = "disabled";
0872 };
0873
0874 spdif: spdif@1c21000 {
0875 #sound-dai-cells = <0>;
0876 compatible = "allwinner,sun4i-a10-spdif";
0877 reg = <0x01c21000 0x400>;
0878 interrupts = <13>;
0879 clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
0880 clock-names = "apb", "spdif";
0881 dmas = <&dma SUN4I_DMA_NORMAL 2>,
0882 <&dma SUN4I_DMA_NORMAL 2>;
0883 dma-names = "rx", "tx";
0884 status = "disabled";
0885 };
0886
0887 ir0: ir@1c21800 {
0888 compatible = "allwinner,sun4i-a10-ir";
0889 clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
0890 clock-names = "apb", "ir";
0891 interrupts = <5>;
0892 reg = <0x01c21800 0x40>;
0893 status = "disabled";
0894 };
0895
0896 ir1: ir@1c21c00 {
0897 compatible = "allwinner,sun4i-a10-ir";
0898 clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
0899 clock-names = "apb", "ir";
0900 interrupts = <6>;
0901 reg = <0x01c21c00 0x40>;
0902 status = "disabled";
0903 };
0904
0905 i2s0: i2s@1c22400 {
0906 #sound-dai-cells = <0>;
0907 compatible = "allwinner,sun4i-a10-i2s";
0908 reg = <0x01c22400 0x400>;
0909 interrupts = <16>;
0910 clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
0911 clock-names = "apb", "mod";
0912 dmas = <&dma SUN4I_DMA_NORMAL 3>,
0913 <&dma SUN4I_DMA_NORMAL 3>;
0914 dma-names = "rx", "tx";
0915 status = "disabled";
0916 };
0917
0918 lradc: lradc@1c22800 {
0919 compatible = "allwinner,sun4i-a10-lradc-keys";
0920 reg = <0x01c22800 0x100>;
0921 interrupts = <31>;
0922 status = "disabled";
0923 };
0924
0925 codec: codec@1c22c00 {
0926 #sound-dai-cells = <0>;
0927 compatible = "allwinner,sun4i-a10-codec";
0928 reg = <0x01c22c00 0x40>;
0929 interrupts = <30>;
0930 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
0931 clock-names = "apb", "codec";
0932 dmas = <&dma SUN4I_DMA_NORMAL 19>,
0933 <&dma SUN4I_DMA_NORMAL 19>;
0934 dma-names = "rx", "tx";
0935 status = "disabled";
0936 };
0937
0938 sid: eeprom@1c23800 {
0939 compatible = "allwinner,sun4i-a10-sid";
0940 reg = <0x01c23800 0x10>;
0941 };
0942
0943 rtp: rtp@1c25000 {
0944 compatible = "allwinner,sun4i-a10-ts";
0945 reg = <0x01c25000 0x100>;
0946 interrupts = <29>;
0947 #thermal-sensor-cells = <0>;
0948 };
0949
0950 uart0: serial@1c28000 {
0951 compatible = "snps,dw-apb-uart";
0952 reg = <0x01c28000 0x400>;
0953 interrupts = <1>;
0954 reg-shift = <2>;
0955 reg-io-width = <4>;
0956 clocks = <&ccu CLK_APB1_UART0>;
0957 status = "disabled";
0958 };
0959
0960 uart1: serial@1c28400 {
0961 compatible = "snps,dw-apb-uart";
0962 reg = <0x01c28400 0x400>;
0963 interrupts = <2>;
0964 reg-shift = <2>;
0965 reg-io-width = <4>;
0966 clocks = <&ccu CLK_APB1_UART1>;
0967 status = "disabled";
0968 };
0969
0970 uart2: serial@1c28800 {
0971 compatible = "snps,dw-apb-uart";
0972 reg = <0x01c28800 0x400>;
0973 interrupts = <3>;
0974 reg-shift = <2>;
0975 reg-io-width = <4>;
0976 clocks = <&ccu CLK_APB1_UART2>;
0977 status = "disabled";
0978 };
0979
0980 uart3: serial@1c28c00 {
0981 compatible = "snps,dw-apb-uart";
0982 reg = <0x01c28c00 0x400>;
0983 interrupts = <4>;
0984 reg-shift = <2>;
0985 reg-io-width = <4>;
0986 clocks = <&ccu CLK_APB1_UART3>;
0987 status = "disabled";
0988 };
0989
0990 uart4: serial@1c29000 {
0991 compatible = "snps,dw-apb-uart";
0992 reg = <0x01c29000 0x400>;
0993 interrupts = <17>;
0994 reg-shift = <2>;
0995 reg-io-width = <4>;
0996 clocks = <&ccu CLK_APB1_UART4>;
0997 status = "disabled";
0998 };
0999
1000 uart5: serial@1c29400 {
1001 compatible = "snps,dw-apb-uart";
1002 reg = <0x01c29400 0x400>;
1003 interrupts = <18>;
1004 reg-shift = <2>;
1005 reg-io-width = <4>;
1006 clocks = <&ccu CLK_APB1_UART5>;
1007 status = "disabled";
1008 };
1009
1010 uart6: serial@1c29800 {
1011 compatible = "snps,dw-apb-uart";
1012 reg = <0x01c29800 0x400>;
1013 interrupts = <19>;
1014 reg-shift = <2>;
1015 reg-io-width = <4>;
1016 clocks = <&ccu CLK_APB1_UART6>;
1017 status = "disabled";
1018 };
1019
1020 uart7: serial@1c29c00 {
1021 compatible = "snps,dw-apb-uart";
1022 reg = <0x01c29c00 0x400>;
1023 interrupts = <20>;
1024 reg-shift = <2>;
1025 reg-io-width = <4>;
1026 clocks = <&ccu CLK_APB1_UART7>;
1027 status = "disabled";
1028 };
1029
1030 ps20: ps2@1c2a000 {
1031 compatible = "allwinner,sun4i-a10-ps2";
1032 reg = <0x01c2a000 0x400>;
1033 interrupts = <62>;
1034 clocks = <&ccu CLK_APB1_PS20>;
1035 status = "disabled";
1036 };
1037
1038 ps21: ps2@1c2a400 {
1039 compatible = "allwinner,sun4i-a10-ps2";
1040 reg = <0x01c2a400 0x400>;
1041 interrupts = <63>;
1042 clocks = <&ccu CLK_APB1_PS21>;
1043 status = "disabled";
1044 };
1045
1046 i2c0: i2c@1c2ac00 {
1047 compatible = "allwinner,sun4i-a10-i2c";
1048 reg = <0x01c2ac00 0x400>;
1049 interrupts = <7>;
1050 clocks = <&ccu CLK_APB1_I2C0>;
1051 pinctrl-names = "default";
1052 pinctrl-0 = <&i2c0_pins>;
1053 status = "disabled";
1054 #address-cells = <1>;
1055 #size-cells = <0>;
1056 };
1057
1058 i2c1: i2c@1c2b000 {
1059 compatible = "allwinner,sun4i-a10-i2c";
1060 reg = <0x01c2b000 0x400>;
1061 interrupts = <8>;
1062 clocks = <&ccu CLK_APB1_I2C1>;
1063 pinctrl-names = "default";
1064 pinctrl-0 = <&i2c1_pins>;
1065 status = "disabled";
1066 #address-cells = <1>;
1067 #size-cells = <0>;
1068 };
1069
1070 i2c2: i2c@1c2b400 {
1071 compatible = "allwinner,sun4i-a10-i2c";
1072 reg = <0x01c2b400 0x400>;
1073 interrupts = <9>;
1074 clocks = <&ccu CLK_APB1_I2C2>;
1075 pinctrl-names = "default";
1076 pinctrl-0 = <&i2c2_pins>;
1077 status = "disabled";
1078 #address-cells = <1>;
1079 #size-cells = <0>;
1080 };
1081
1082 can0: can@1c2bc00 {
1083 compatible = "allwinner,sun4i-a10-can";
1084 reg = <0x01c2bc00 0x400>;
1085 interrupts = <26>;
1086 clocks = <&ccu CLK_APB1_CAN>;
1087 status = "disabled";
1088 };
1089
1090 mali: gpu@1c40000 {
1091 compatible = "allwinner,sun4i-a10-mali", "arm,mali-400";
1092 reg = <0x01c40000 0x10000>;
1093 interrupts = <69>,
1094 <70>,
1095 <71>,
1096 <72>,
1097 <73>;
1098 interrupt-names = "gp",
1099 "gpmmu",
1100 "pp0",
1101 "ppmmu0",
1102 "pmu";
1103 clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1104 clock-names = "bus", "core";
1105 resets = <&ccu RST_GPU>;
1106
1107 assigned-clocks = <&ccu CLK_GPU>;
1108 assigned-clock-rates = <384000000>;
1109 };
1110
1111 fe0: display-frontend@1e00000 {
1112 compatible = "allwinner,sun4i-a10-display-frontend";
1113 reg = <0x01e00000 0x20000>;
1114 interrupts = <47>;
1115 clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1116 <&ccu CLK_DRAM_DE_FE0>;
1117 clock-names = "ahb", "mod",
1118 "ram";
1119 resets = <&ccu RST_DE_FE0>;
1120
1121 ports {
1122 #address-cells = <1>;
1123 #size-cells = <0>;
1124
1125 fe0_out: port@1 {
1126 #address-cells = <1>;
1127 #size-cells = <0>;
1128 reg = <1>;
1129
1130 fe0_out_be0: endpoint@0 {
1131 reg = <0>;
1132 remote-endpoint = <&be0_in_fe0>;
1133 };
1134
1135 fe0_out_be1: endpoint@1 {
1136 reg = <1>;
1137 remote-endpoint = <&be1_in_fe0>;
1138 };
1139 };
1140 };
1141 };
1142
1143 fe1: display-frontend@1e20000 {
1144 compatible = "allwinner,sun4i-a10-display-frontend";
1145 reg = <0x01e20000 0x20000>;
1146 interrupts = <48>;
1147 clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1148 <&ccu CLK_DRAM_DE_FE1>;
1149 clock-names = "ahb", "mod",
1150 "ram";
1151 resets = <&ccu RST_DE_FE1>;
1152
1153 ports {
1154 #address-cells = <1>;
1155 #size-cells = <0>;
1156
1157 fe1_out: port@1 {
1158 #address-cells = <1>;
1159 #size-cells = <0>;
1160 reg = <1>;
1161
1162 fe1_out_be0: endpoint@0 {
1163 reg = <0>;
1164 remote-endpoint = <&be0_in_fe1>;
1165 };
1166
1167 fe1_out_be1: endpoint@1 {
1168 reg = <1>;
1169 remote-endpoint = <&be1_in_fe1>;
1170 };
1171 };
1172 };
1173 };
1174
1175 be1: display-backend@1e40000 {
1176 compatible = "allwinner,sun4i-a10-display-backend";
1177 reg = <0x01e40000 0x10000>;
1178 interrupts = <48>;
1179 clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1180 <&ccu CLK_DRAM_DE_BE1>;
1181 clock-names = "ahb", "mod",
1182 "ram";
1183 resets = <&ccu RST_DE_BE1>;
1184
1185 ports {
1186 #address-cells = <1>;
1187 #size-cells = <0>;
1188
1189 be1_in: port@0 {
1190 #address-cells = <1>;
1191 #size-cells = <0>;
1192 reg = <0>;
1193
1194 be1_in_fe0: endpoint@0 {
1195 reg = <0>;
1196 remote-endpoint = <&fe0_out_be1>;
1197 };
1198
1199 be1_in_fe1: endpoint@1 {
1200 reg = <1>;
1201 remote-endpoint = <&fe1_out_be1>;
1202 };
1203 };
1204
1205 be1_out: port@1 {
1206 #address-cells = <1>;
1207 #size-cells = <0>;
1208 reg = <1>;
1209
1210 be1_out_tcon0: endpoint@0 {
1211 reg = <0>;
1212 remote-endpoint = <&tcon0_in_be1>;
1213 };
1214
1215 be1_out_tcon1: endpoint@1 {
1216 reg = <1>;
1217 remote-endpoint = <&tcon1_in_be1>;
1218 };
1219 };
1220 };
1221 };
1222
1223 be0: display-backend@1e60000 {
1224 compatible = "allwinner,sun4i-a10-display-backend";
1225 reg = <0x01e60000 0x10000>;
1226 interrupts = <47>;
1227 clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1228 <&ccu CLK_DRAM_DE_BE0>;
1229 clock-names = "ahb", "mod",
1230 "ram";
1231 resets = <&ccu RST_DE_BE0>;
1232
1233 ports {
1234 #address-cells = <1>;
1235 #size-cells = <0>;
1236
1237 be0_in: port@0 {
1238 #address-cells = <1>;
1239 #size-cells = <0>;
1240 reg = <0>;
1241
1242 be0_in_fe0: endpoint@0 {
1243 reg = <0>;
1244 remote-endpoint = <&fe0_out_be0>;
1245 };
1246
1247 be0_in_fe1: endpoint@1 {
1248 reg = <1>;
1249 remote-endpoint = <&fe1_out_be0>;
1250 };
1251 };
1252
1253 be0_out: port@1 {
1254 #address-cells = <1>;
1255 #size-cells = <0>;
1256 reg = <1>;
1257
1258 be0_out_tcon0: endpoint@0 {
1259 reg = <0>;
1260 remote-endpoint = <&tcon0_in_be0>;
1261 };
1262
1263 be0_out_tcon1: endpoint@1 {
1264 reg = <1>;
1265 remote-endpoint = <&tcon1_in_be0>;
1266 };
1267 };
1268 };
1269 };
1270 };
1271 };
