0001 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
0002 /*
0003 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
0004 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
0005 */
0006
0007 #include "stm32mp151.dtsi"
0008
0009 / {
0010 cpus {
0011 cpu1: cpu@1 {
0012 compatible = "arm,cortex-a7";
0013 clock-frequency = <650000000>;
0014 device_type = "cpu";
0015 reg = <1>;
0016 };
0017 };
0018
0019 arm-pmu {
0020 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
0021 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
0022 interrupt-affinity = <&cpu0>, <&cpu1>;
0023 };
0024
0025 timer {
0026 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0027 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0028 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
0029 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
0030 };
0031
0032 soc {
0033 m_can1: can@4400e000 {
0034 compatible = "bosch,m_can";
0035 reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
0036 reg-names = "m_can", "message_ram";
0037 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0038 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
0039 interrupt-names = "int0", "int1";
0040 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
0041 clock-names = "hclk", "cclk";
0042 bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
0043 status = "disabled";
0044 };
0045
0046 m_can2: can@4400f000 {
0047 compatible = "bosch,m_can";
0048 reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
0049 reg-names = "m_can", "message_ram";
0050 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
0051 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0052 interrupt-names = "int0", "int1";
0053 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
0054 clock-names = "hclk", "cclk";
0055 bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
0056 status = "disabled";
0057 };
0058 };
0059 };
