0001 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
0002 /*
0003 * Copyright (C) Protonic Holland
0004 * Author: David Jander <david@protonic.nl>
0005 */
0006 /dts-v1/;
0007
0008 #include "stm32mp151a-prtt1l.dtsi"
0009
0010 / {
0011 model = "Protonic PRTT1C";
0012 compatible = "prt,prtt1c", "st,stm32mp151";
0013
0014 clock_ksz9031: clock-ksz9031 {
0015 compatible = "fixed-clock";
0016 #clock-cells = <0>;
0017 clock-frequency = <25000000>;
0018 };
0019
0020 clock_sja1105: clock-sja1105 {
0021 compatible = "fixed-clock";
0022 #clock-cells = <0>;
0023 clock-frequency = <25000000>;
0024 };
0025
0026 mdio0: mdio {
0027 compatible = "virtual,mdio-gpio";
0028 #address-cells = <1>;
0029 #size-cells = <0>;
0030 gpios = <&gpioc 1 GPIO_ACTIVE_HIGH
0031 &gpioa 2 GPIO_ACTIVE_HIGH>;
0032
0033 };
0034
0035 wifi_pwrseq: wifi-pwrseq {
0036 compatible = "mmc-pwrseq-simple";
0037 reset-gpios = <&gpiod 8 GPIO_ACTIVE_LOW>;
0038 };
0039 };
0040
0041 ðernet0 {
0042 fixed-link {
0043 speed = <100>;
0044 full-duplex;
0045 };
0046 };
0047
0048 &gpioa {
0049 gpio-line-names =
0050 "", "", "", "PHY0_nRESET", "PHY0_nINT", "", "", "",
0051 "", "", "", "", "", "", "", "SPI1_nSS";
0052 };
0053
0054 &gpiod {
0055 gpio-line-names =
0056 "", "", "", "", "", "", "", "",
0057 "WFM_RESET", "", "", "", "", "", "", "";
0058 };
0059
0060 &gpioe {
0061 gpio-line-names =
0062 "SDMMC2_nRESET", "", "", "", "", "", "SPI1_nRESET", "",
0063 "", "", "", "", "WFM_nIRQ", "", "", "";
0064 };
0065
0066 &gpiog {
0067 gpio-line-names =
0068 "", "", "", "", "", "", "", "PHY3_nINT",
0069 "PHY1_nINT", "PHY3_nRESET", "PHY2_nINT", "PHY2_nRESET",
0070 "PHY1_nRESET", "SPE1_PWR", "SPE0_PWR", "";
0071 };
0072
0073 &mdio0 {
0074 /* All this DP83TD510E PHYs can't be probed before switch@0 is
0075 * probed so we need to use compatible with PHYid
0076 */
0077 /* TI DP83TD510E */
0078 t1l0_phy: ethernet-phy@6 {
0079 compatible = "ethernet-phy-id2000.0181";
0080 reg = <6>;
0081 interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>;
0082 reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>;
0083 reset-assert-us = <10>;
0084 reset-deassert-us = <35>;
0085 };
0086
0087 /* TI DP83TD510E */
0088 t1l1_phy: ethernet-phy@7 {
0089 compatible = "ethernet-phy-id2000.0181";
0090 reg = <7>;
0091 interrupts-extended = <&gpiog 8 IRQ_TYPE_LEVEL_LOW>;
0092 reset-gpios = <&gpiog 12 GPIO_ACTIVE_LOW>;
0093 reset-assert-us = <10>;
0094 reset-deassert-us = <35>;
0095 };
0096
0097 /* TI DP83TD510E */
0098 t1l2_phy: ethernet-phy@10 {
0099 compatible = "ethernet-phy-id2000.0181";
0100 reg = <10>;
0101 interrupts-extended = <&gpiog 10 IRQ_TYPE_LEVEL_LOW>;
0102 reset-gpios = <&gpiog 11 GPIO_ACTIVE_LOW>;
0103 reset-assert-us = <10>;
0104 reset-deassert-us = <35>;
0105 };
0106
0107 /* Micrel KSZ9031 */
0108 rj45_phy: ethernet-phy@2 {
0109 reg = <2>;
0110 interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>;
0111 reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
0112 reset-assert-us = <10000>;
0113 reset-deassert-us = <1000>;
0114
0115 clocks = <&clock_ksz9031>;
0116 };
0117 };
0118
0119 &qspi {
0120 status = "disabled";
0121 };
0122
0123 &sdmmc2 {
0124 pinctrl-names = "default", "opendrain", "sleep";
0125 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
0126 pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
0127 pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
0128 non-removable;
0129 no-sd;
0130 no-sdio;
0131 no-1-8-v;
0132 st,neg-edge;
0133 bus-width = <8>;
0134 vmmc-supply = <®_3v3>;
0135 vqmmc-supply = <®_3v3>;
0136 status = "okay";
0137 };
0138
0139 &sdmmc2_b4_od_pins_a {
0140 pins1 {
0141 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
0142 <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
0143 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
0144 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
0145 };
0146 };
0147
0148 &sdmmc2_b4_pins_a {
0149 pins1 {
0150 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
0151 <STM32_PINMUX('B', 7, AF10)>, /* SDMMC2_D1 */
0152 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
0153 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
0154 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
0155 };
0156 };
0157
0158 &sdmmc2_b4_sleep_pins_a {
0159 pins {
0160 pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
0161 <STM32_PINMUX('B', 7, ANALOG)>, /* SDMMC2_D1 */
0162 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
0163 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
0164 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
0165 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
0166 };
0167 };
0168
0169 &sdmmc2_d47_pins_a {
0170 pins {
0171 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
0172 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
0173 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
0174 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
0175 };
0176 };
0177
0178 &sdmmc2_d47_sleep_pins_a {
0179 pins {
0180 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
0181 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
0182 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
0183 <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
0184 };
0185 };
0186
0187 &sdmmc3 {
0188 pinctrl-names = "default", "opendrain", "sleep";
0189 pinctrl-0 = <&sdmmc3_b4_pins_b>;
0190 pinctrl-1 = <&sdmmc3_b4_od_pins_b>;
0191 pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>;
0192 non-removable;
0193 no-1-8-v;
0194 st,neg-edge;
0195 bus-width = <4>;
0196 vmmc-supply = <®_3v3>;
0197 vqmmc-supply = <®_3v3>;
0198 mmc-pwrseq = <&wifi_pwrseq>;
0199 #address-cells = <1>;
0200 #size-cells = <0>;
0201 status = "okay";
0202
0203 mmc@1 {
0204 compatible = "prt,prtt1c-wfm200", "silabs,wf200";
0205 reg = <1>;
0206 };
0207 };
0208
0209 &sdmmc3_b4_od_pins_b {
0210 pins1 {
0211 pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */
0212 <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */
0213 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
0214 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
0215 };
0216 };
0217
0218 &sdmmc3_b4_pins_b {
0219 pins1 {
0220 pinmux = <STM32_PINMUX('D', 1, AF10)>, /* SDMMC3_D0 */
0221 <STM32_PINMUX('D', 4, AF10)>, /* SDMMC3_D1 */
0222 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
0223 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
0224 <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */
0225 };
0226 };
0227
0228 &sdmmc3_b4_sleep_pins_b {
0229 pins {
0230 pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* SDMMC3_D0 */
0231 <STM32_PINMUX('D', 4, ANALOG)>, /* SDMMC3_D1 */
0232 <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */
0233 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
0234 <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
0235 <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */
0236 };
0237 };
0238
0239 &spi1 {
0240 pinctrl-0 = <&spi1_pins_b>;
0241 pinctrl-names = "default";
0242 cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
0243 /delete-property/dmas;
0244 /delete-property/dma-names;
0245 status = "okay";
0246
0247 switch@0 {
0248 compatible = "nxp,sja1105q";
0249 reg = <0>;
0250 spi-max-frequency = <4000000>;
0251 spi-rx-delay-us = <1>;
0252 spi-tx-delay-us = <1>;
0253 spi-cpha;
0254
0255 reset-gpios = <&gpioe 6 GPIO_ACTIVE_LOW>;
0256
0257 clocks = <&clock_sja1105>;
0258
0259 ports {
0260 #address-cells = <1>;
0261 #size-cells = <0>;
0262
0263 port@0 {
0264 reg = <0>;
0265 label = "t1l0";
0266 phy-mode = "rmii";
0267 phy-handle = <&t1l0_phy>;
0268 };
0269
0270 port@1 {
0271 reg = <1>;
0272 label = "t1l1";
0273 phy-mode = "rmii";
0274 phy-handle = <&t1l1_phy>;
0275 };
0276
0277 port@2 {
0278 reg = <2>;
0279 label = "t1l2";
0280 phy-mode = "rmii";
0281 phy-handle = <&t1l2_phy>;
0282 };
0283
0284 port@3 {
0285 reg = <3>;
0286 label = "rj45";
0287 phy-handle = <&rj45_phy>;
0288 phy-mode = "rgmii-id";
0289 };
0290
0291 port@4 {
0292 reg = <4>;
0293 label = "cpu";
0294 ethernet = <ðernet0>;
0295 phy-mode = "rmii";
0296
0297 fixed-link {
0298 speed = <100>;
0299 full-duplex;
0300 };
0301 };
0302 };
0303 };
0304 };
