0001 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
0002 /*
0003 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
0004 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
0005 */
0006 #include <dt-bindings/interrupt-controller/arm-gic.h>
0007 #include <dt-bindings/clock/stm32mp1-clks.h>
0008 #include <dt-bindings/reset/stm32mp1-resets.h>
0009
0010 / {
0011 #address-cells = <1>;
0012 #size-cells = <1>;
0013
0014 cpus {
0015 #address-cells = <1>;
0016 #size-cells = <0>;
0017
0018 cpu0: cpu@0 {
0019 compatible = "arm,cortex-a7";
0020 clock-frequency = <650000000>;
0021 device_type = "cpu";
0022 reg = <0>;
0023 };
0024 };
0025
0026 arm-pmu {
0027 compatible = "arm,cortex-a7-pmu";
0028 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
0029 interrupt-affinity = <&cpu0>;
0030 interrupt-parent = <&intc>;
0031 };
0032
0033 psci {
0034 compatible = "arm,psci-1.0";
0035 method = "smc";
0036 };
0037
0038 intc: interrupt-controller@a0021000 {
0039 compatible = "arm,cortex-a7-gic";
0040 #interrupt-cells = <3>;
0041 interrupt-controller;
0042 reg = <0xa0021000 0x1000>,
0043 <0xa0022000 0x2000>;
0044 };
0045
0046 timer {
0047 compatible = "arm,armv7-timer";
0048 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0049 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0050 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0051 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
0052 interrupt-parent = <&intc>;
0053 };
0054
0055 clocks {
0056 clk_hse: clk-hse {
0057 #clock-cells = <0>;
0058 compatible = "fixed-clock";
0059 clock-frequency = <24000000>;
0060 };
0061
0062 clk_hsi: clk-hsi {
0063 #clock-cells = <0>;
0064 compatible = "fixed-clock";
0065 clock-frequency = <64000000>;
0066 };
0067
0068 clk_lse: clk-lse {
0069 #clock-cells = <0>;
0070 compatible = "fixed-clock";
0071 clock-frequency = <32768>;
0072 };
0073
0074 clk_lsi: clk-lsi {
0075 #clock-cells = <0>;
0076 compatible = "fixed-clock";
0077 clock-frequency = <32000>;
0078 };
0079
0080 clk_csi: clk-csi {
0081 #clock-cells = <0>;
0082 compatible = "fixed-clock";
0083 clock-frequency = <4000000>;
0084 };
0085 };
0086
0087 thermal-zones {
0088 cpu_thermal: cpu-thermal {
0089 polling-delay-passive = <0>;
0090 polling-delay = <0>;
0091 thermal-sensors = <&dts>;
0092
0093 trips {
0094 cpu_alert1: cpu-alert1 {
0095 temperature = <85000>;
0096 hysteresis = <0>;
0097 type = "passive";
0098 };
0099
0100 cpu-crit {
0101 temperature = <120000>;
0102 hysteresis = <0>;
0103 type = "critical";
0104 };
0105 };
0106
0107 cooling-maps {
0108 };
0109 };
0110 };
0111
0112 booster: regulator-booster {
0113 compatible = "st,stm32mp1-booster";
0114 st,syscfg = <&syscfg>;
0115 status = "disabled";
0116 };
0117
0118 soc {
0119 compatible = "simple-bus";
0120 #address-cells = <1>;
0121 #size-cells = <1>;
0122 interrupt-parent = <&intc>;
0123 ranges;
0124
0125 timers2: timer@40000000 {
0126 #address-cells = <1>;
0127 #size-cells = <0>;
0128 compatible = "st,stm32-timers";
0129 reg = <0x40000000 0x400>;
0130 clocks = <&rcc TIM2_K>;
0131 clock-names = "int";
0132 dmas = <&dmamux1 18 0x400 0x1>,
0133 <&dmamux1 19 0x400 0x1>,
0134 <&dmamux1 20 0x400 0x1>,
0135 <&dmamux1 21 0x400 0x1>,
0136 <&dmamux1 22 0x400 0x1>;
0137 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
0138 status = "disabled";
0139
0140 pwm {
0141 compatible = "st,stm32-pwm";
0142 #pwm-cells = <3>;
0143 status = "disabled";
0144 };
0145
0146 timer@1 {
0147 compatible = "st,stm32h7-timer-trigger";
0148 reg = <1>;
0149 status = "disabled";
0150 };
0151
0152 counter {
0153 compatible = "st,stm32-timer-counter";
0154 status = "disabled";
0155 };
0156 };
0157
0158 timers3: timer@40001000 {
0159 #address-cells = <1>;
0160 #size-cells = <0>;
0161 compatible = "st,stm32-timers";
0162 reg = <0x40001000 0x400>;
0163 clocks = <&rcc TIM3_K>;
0164 clock-names = "int";
0165 dmas = <&dmamux1 23 0x400 0x1>,
0166 <&dmamux1 24 0x400 0x1>,
0167 <&dmamux1 25 0x400 0x1>,
0168 <&dmamux1 26 0x400 0x1>,
0169 <&dmamux1 27 0x400 0x1>,
0170 <&dmamux1 28 0x400 0x1>;
0171 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
0172 status = "disabled";
0173
0174 pwm {
0175 compatible = "st,stm32-pwm";
0176 #pwm-cells = <3>;
0177 status = "disabled";
0178 };
0179
0180 timer@2 {
0181 compatible = "st,stm32h7-timer-trigger";
0182 reg = <2>;
0183 status = "disabled";
0184 };
0185
0186 counter {
0187 compatible = "st,stm32-timer-counter";
0188 status = "disabled";
0189 };
0190 };
0191
0192 timers4: timer@40002000 {
0193 #address-cells = <1>;
0194 #size-cells = <0>;
0195 compatible = "st,stm32-timers";
0196 reg = <0x40002000 0x400>;
0197 clocks = <&rcc TIM4_K>;
0198 clock-names = "int";
0199 dmas = <&dmamux1 29 0x400 0x1>,
0200 <&dmamux1 30 0x400 0x1>,
0201 <&dmamux1 31 0x400 0x1>,
0202 <&dmamux1 32 0x400 0x1>;
0203 dma-names = "ch1", "ch2", "ch3", "ch4";
0204 status = "disabled";
0205
0206 pwm {
0207 compatible = "st,stm32-pwm";
0208 #pwm-cells = <3>;
0209 status = "disabled";
0210 };
0211
0212 timer@3 {
0213 compatible = "st,stm32h7-timer-trigger";
0214 reg = <3>;
0215 status = "disabled";
0216 };
0217
0218 counter {
0219 compatible = "st,stm32-timer-counter";
0220 status = "disabled";
0221 };
0222 };
0223
0224 timers5: timer@40003000 {
0225 #address-cells = <1>;
0226 #size-cells = <0>;
0227 compatible = "st,stm32-timers";
0228 reg = <0x40003000 0x400>;
0229 clocks = <&rcc TIM5_K>;
0230 clock-names = "int";
0231 dmas = <&dmamux1 55 0x400 0x1>,
0232 <&dmamux1 56 0x400 0x1>,
0233 <&dmamux1 57 0x400 0x1>,
0234 <&dmamux1 58 0x400 0x1>,
0235 <&dmamux1 59 0x400 0x1>,
0236 <&dmamux1 60 0x400 0x1>;
0237 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
0238 status = "disabled";
0239
0240 pwm {
0241 compatible = "st,stm32-pwm";
0242 #pwm-cells = <3>;
0243 status = "disabled";
0244 };
0245
0246 timer@4 {
0247 compatible = "st,stm32h7-timer-trigger";
0248 reg = <4>;
0249 status = "disabled";
0250 };
0251
0252 counter {
0253 compatible = "st,stm32-timer-counter";
0254 status = "disabled";
0255 };
0256 };
0257
0258 timers6: timer@40004000 {
0259 #address-cells = <1>;
0260 #size-cells = <0>;
0261 compatible = "st,stm32-timers";
0262 reg = <0x40004000 0x400>;
0263 clocks = <&rcc TIM6_K>;
0264 clock-names = "int";
0265 dmas = <&dmamux1 69 0x400 0x1>;
0266 dma-names = "up";
0267 status = "disabled";
0268
0269 timer@5 {
0270 compatible = "st,stm32h7-timer-trigger";
0271 reg = <5>;
0272 status = "disabled";
0273 };
0274 };
0275
0276 timers7: timer@40005000 {
0277 #address-cells = <1>;
0278 #size-cells = <0>;
0279 compatible = "st,stm32-timers";
0280 reg = <0x40005000 0x400>;
0281 clocks = <&rcc TIM7_K>;
0282 clock-names = "int";
0283 dmas = <&dmamux1 70 0x400 0x1>;
0284 dma-names = "up";
0285 status = "disabled";
0286
0287 timer@6 {
0288 compatible = "st,stm32h7-timer-trigger";
0289 reg = <6>;
0290 status = "disabled";
0291 };
0292 };
0293
0294 timers12: timer@40006000 {
0295 #address-cells = <1>;
0296 #size-cells = <0>;
0297 compatible = "st,stm32-timers";
0298 reg = <0x40006000 0x400>;
0299 clocks = <&rcc TIM12_K>;
0300 clock-names = "int";
0301 status = "disabled";
0302
0303 pwm {
0304 compatible = "st,stm32-pwm";
0305 #pwm-cells = <3>;
0306 status = "disabled";
0307 };
0308
0309 timer@11 {
0310 compatible = "st,stm32h7-timer-trigger";
0311 reg = <11>;
0312 status = "disabled";
0313 };
0314 };
0315
0316 timers13: timer@40007000 {
0317 #address-cells = <1>;
0318 #size-cells = <0>;
0319 compatible = "st,stm32-timers";
0320 reg = <0x40007000 0x400>;
0321 clocks = <&rcc TIM13_K>;
0322 clock-names = "int";
0323 status = "disabled";
0324
0325 pwm {
0326 compatible = "st,stm32-pwm";
0327 #pwm-cells = <3>;
0328 status = "disabled";
0329 };
0330
0331 timer@12 {
0332 compatible = "st,stm32h7-timer-trigger";
0333 reg = <12>;
0334 status = "disabled";
0335 };
0336 };
0337
0338 timers14: timer@40008000 {
0339 #address-cells = <1>;
0340 #size-cells = <0>;
0341 compatible = "st,stm32-timers";
0342 reg = <0x40008000 0x400>;
0343 clocks = <&rcc TIM14_K>;
0344 clock-names = "int";
0345 status = "disabled";
0346
0347 pwm {
0348 compatible = "st,stm32-pwm";
0349 #pwm-cells = <3>;
0350 status = "disabled";
0351 };
0352
0353 timer@13 {
0354 compatible = "st,stm32h7-timer-trigger";
0355 reg = <13>;
0356 status = "disabled";
0357 };
0358 };
0359
0360 lptimer1: timer@40009000 {
0361 #address-cells = <1>;
0362 #size-cells = <0>;
0363 compatible = "st,stm32-lptimer";
0364 reg = <0x40009000 0x400>;
0365 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
0366 clocks = <&rcc LPTIM1_K>;
0367 clock-names = "mux";
0368 wakeup-source;
0369 status = "disabled";
0370
0371 pwm {
0372 compatible = "st,stm32-pwm-lp";
0373 #pwm-cells = <3>;
0374 status = "disabled";
0375 };
0376
0377 trigger@0 {
0378 compatible = "st,stm32-lptimer-trigger";
0379 reg = <0>;
0380 status = "disabled";
0381 };
0382
0383 counter {
0384 compatible = "st,stm32-lptimer-counter";
0385 status = "disabled";
0386 };
0387 };
0388
0389 spi2: spi@4000b000 {
0390 #address-cells = <1>;
0391 #size-cells = <0>;
0392 compatible = "st,stm32h7-spi";
0393 reg = <0x4000b000 0x400>;
0394 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0395 clocks = <&rcc SPI2_K>;
0396 resets = <&rcc SPI2_R>;
0397 dmas = <&dmamux1 39 0x400 0x05>,
0398 <&dmamux1 40 0x400 0x05>;
0399 dma-names = "rx", "tx";
0400 status = "disabled";
0401 };
0402
0403 i2s2: audio-controller@4000b000 {
0404 compatible = "st,stm32h7-i2s";
0405 #sound-dai-cells = <0>;
0406 reg = <0x4000b000 0x400>;
0407 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0408 dmas = <&dmamux1 39 0x400 0x01>,
0409 <&dmamux1 40 0x400 0x01>;
0410 dma-names = "rx", "tx";
0411 status = "disabled";
0412 };
0413
0414 spi3: spi@4000c000 {
0415 #address-cells = <1>;
0416 #size-cells = <0>;
0417 compatible = "st,stm32h7-spi";
0418 reg = <0x4000c000 0x400>;
0419 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
0420 clocks = <&rcc SPI3_K>;
0421 resets = <&rcc SPI3_R>;
0422 dmas = <&dmamux1 61 0x400 0x05>,
0423 <&dmamux1 62 0x400 0x05>;
0424 dma-names = "rx", "tx";
0425 status = "disabled";
0426 };
0427
0428 i2s3: audio-controller@4000c000 {
0429 compatible = "st,stm32h7-i2s";
0430 #sound-dai-cells = <0>;
0431 reg = <0x4000c000 0x400>;
0432 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
0433 dmas = <&dmamux1 61 0x400 0x01>,
0434 <&dmamux1 62 0x400 0x01>;
0435 dma-names = "rx", "tx";
0436 status = "disabled";
0437 };
0438
0439 spdifrx: audio-controller@4000d000 {
0440 compatible = "st,stm32h7-spdifrx";
0441 #sound-dai-cells = <0>;
0442 reg = <0x4000d000 0x400>;
0443 clocks = <&rcc SPDIF_K>;
0444 clock-names = "kclk";
0445 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0446 dmas = <&dmamux1 93 0x400 0x01>,
0447 <&dmamux1 94 0x400 0x01>;
0448 dma-names = "rx", "rx-ctrl";
0449 status = "disabled";
0450 };
0451
0452 usart2: serial@4000e000 {
0453 compatible = "st,stm32h7-uart";
0454 reg = <0x4000e000 0x400>;
0455 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
0456 clocks = <&rcc USART2_K>;
0457 wakeup-source;
0458 dmas = <&dmamux1 43 0x400 0x15>,
0459 <&dmamux1 44 0x400 0x11>;
0460 dma-names = "rx", "tx";
0461 status = "disabled";
0462 };
0463
0464 usart3: serial@4000f000 {
0465 compatible = "st,stm32h7-uart";
0466 reg = <0x4000f000 0x400>;
0467 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
0468 clocks = <&rcc USART3_K>;
0469 wakeup-source;
0470 dmas = <&dmamux1 45 0x400 0x15>,
0471 <&dmamux1 46 0x400 0x11>;
0472 dma-names = "rx", "tx";
0473 status = "disabled";
0474 };
0475
0476 uart4: serial@40010000 {
0477 compatible = "st,stm32h7-uart";
0478 reg = <0x40010000 0x400>;
0479 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
0480 clocks = <&rcc UART4_K>;
0481 wakeup-source;
0482 dmas = <&dmamux1 63 0x400 0x15>,
0483 <&dmamux1 64 0x400 0x11>;
0484 dma-names = "rx", "tx";
0485 status = "disabled";
0486 };
0487
0488 uart5: serial@40011000 {
0489 compatible = "st,stm32h7-uart";
0490 reg = <0x40011000 0x400>;
0491 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
0492 clocks = <&rcc UART5_K>;
0493 wakeup-source;
0494 dmas = <&dmamux1 65 0x400 0x15>,
0495 <&dmamux1 66 0x400 0x11>;
0496 dma-names = "rx", "tx";
0497 status = "disabled";
0498 };
0499
0500 i2c1: i2c@40012000 {
0501 compatible = "st,stm32mp15-i2c";
0502 reg = <0x40012000 0x400>;
0503 interrupt-names = "event", "error";
0504 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
0505 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0506 clocks = <&rcc I2C1_K>;
0507 resets = <&rcc I2C1_R>;
0508 #address-cells = <1>;
0509 #size-cells = <0>;
0510 st,syscfg-fmp = <&syscfg 0x4 0x1>;
0511 wakeup-source;
0512 i2c-analog-filter;
0513 status = "disabled";
0514 };
0515
0516 i2c2: i2c@40013000 {
0517 compatible = "st,stm32mp15-i2c";
0518 reg = <0x40013000 0x400>;
0519 interrupt-names = "event", "error";
0520 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
0521 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
0522 clocks = <&rcc I2C2_K>;
0523 resets = <&rcc I2C2_R>;
0524 #address-cells = <1>;
0525 #size-cells = <0>;
0526 st,syscfg-fmp = <&syscfg 0x4 0x2>;
0527 wakeup-source;
0528 i2c-analog-filter;
0529 status = "disabled";
0530 };
0531
0532 i2c3: i2c@40014000 {
0533 compatible = "st,stm32mp15-i2c";
0534 reg = <0x40014000 0x400>;
0535 interrupt-names = "event", "error";
0536 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
0537 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0538 clocks = <&rcc I2C3_K>;
0539 resets = <&rcc I2C3_R>;
0540 #address-cells = <1>;
0541 #size-cells = <0>;
0542 st,syscfg-fmp = <&syscfg 0x4 0x4>;
0543 wakeup-source;
0544 i2c-analog-filter;
0545 status = "disabled";
0546 };
0547
0548 i2c5: i2c@40015000 {
0549 compatible = "st,stm32mp15-i2c";
0550 reg = <0x40015000 0x400>;
0551 interrupt-names = "event", "error";
0552 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
0553 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
0554 clocks = <&rcc I2C5_K>;
0555 resets = <&rcc I2C5_R>;
0556 #address-cells = <1>;
0557 #size-cells = <0>;
0558 st,syscfg-fmp = <&syscfg 0x4 0x10>;
0559 wakeup-source;
0560 i2c-analog-filter;
0561 status = "disabled";
0562 };
0563
0564 cec: cec@40016000 {
0565 compatible = "st,stm32-cec";
0566 reg = <0x40016000 0x400>;
0567 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
0568 clocks = <&rcc CEC_K>, <&rcc CEC>;
0569 clock-names = "cec", "hdmi-cec";
0570 status = "disabled";
0571 };
0572
0573 dac: dac@40017000 {
0574 compatible = "st,stm32h7-dac-core";
0575 reg = <0x40017000 0x400>;
0576 clocks = <&rcc DAC12>;
0577 clock-names = "pclk";
0578 #address-cells = <1>;
0579 #size-cells = <0>;
0580 status = "disabled";
0581
0582 dac1: dac@1 {
0583 compatible = "st,stm32-dac";
0584 #io-channel-cells = <1>;
0585 reg = <1>;
0586 status = "disabled";
0587 };
0588
0589 dac2: dac@2 {
0590 compatible = "st,stm32-dac";
0591 #io-channel-cells = <1>;
0592 reg = <2>;
0593 status = "disabled";
0594 };
0595 };
0596
0597 uart7: serial@40018000 {
0598 compatible = "st,stm32h7-uart";
0599 reg = <0x40018000 0x400>;
0600 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
0601 clocks = <&rcc UART7_K>;
0602 wakeup-source;
0603 dmas = <&dmamux1 79 0x400 0x15>,
0604 <&dmamux1 80 0x400 0x11>;
0605 dma-names = "rx", "tx";
0606 status = "disabled";
0607 };
0608
0609 uart8: serial@40019000 {
0610 compatible = "st,stm32h7-uart";
0611 reg = <0x40019000 0x400>;
0612 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
0613 clocks = <&rcc UART8_K>;
0614 wakeup-source;
0615 dmas = <&dmamux1 81 0x400 0x15>,
0616 <&dmamux1 82 0x400 0x11>;
0617 dma-names = "rx", "tx";
0618 status = "disabled";
0619 };
0620
0621 timers1: timer@44000000 {
0622 #address-cells = <1>;
0623 #size-cells = <0>;
0624 compatible = "st,stm32-timers";
0625 reg = <0x44000000 0x400>;
0626 clocks = <&rcc TIM1_K>;
0627 clock-names = "int";
0628 dmas = <&dmamux1 11 0x400 0x1>,
0629 <&dmamux1 12 0x400 0x1>,
0630 <&dmamux1 13 0x400 0x1>,
0631 <&dmamux1 14 0x400 0x1>,
0632 <&dmamux1 15 0x400 0x1>,
0633 <&dmamux1 16 0x400 0x1>,
0634 <&dmamux1 17 0x400 0x1>;
0635 dma-names = "ch1", "ch2", "ch3", "ch4",
0636 "up", "trig", "com";
0637 status = "disabled";
0638
0639 pwm {
0640 compatible = "st,stm32-pwm";
0641 #pwm-cells = <3>;
0642 status = "disabled";
0643 };
0644
0645 timer@0 {
0646 compatible = "st,stm32h7-timer-trigger";
0647 reg = <0>;
0648 status = "disabled";
0649 };
0650
0651 counter {
0652 compatible = "st,stm32-timer-counter";
0653 status = "disabled";
0654 };
0655 };
0656
0657 timers8: timer@44001000 {
0658 #address-cells = <1>;
0659 #size-cells = <0>;
0660 compatible = "st,stm32-timers";
0661 reg = <0x44001000 0x400>;
0662 clocks = <&rcc TIM8_K>;
0663 clock-names = "int";
0664 dmas = <&dmamux1 47 0x400 0x1>,
0665 <&dmamux1 48 0x400 0x1>,
0666 <&dmamux1 49 0x400 0x1>,
0667 <&dmamux1 50 0x400 0x1>,
0668 <&dmamux1 51 0x400 0x1>,
0669 <&dmamux1 52 0x400 0x1>,
0670 <&dmamux1 53 0x400 0x1>;
0671 dma-names = "ch1", "ch2", "ch3", "ch4",
0672 "up", "trig", "com";
0673 status = "disabled";
0674
0675 pwm {
0676 compatible = "st,stm32-pwm";
0677 #pwm-cells = <3>;
0678 status = "disabled";
0679 };
0680
0681 timer@7 {
0682 compatible = "st,stm32h7-timer-trigger";
0683 reg = <7>;
0684 status = "disabled";
0685 };
0686
0687 counter {
0688 compatible = "st,stm32-timer-counter";
0689 status = "disabled";
0690 };
0691 };
0692
0693 usart6: serial@44003000 {
0694 compatible = "st,stm32h7-uart";
0695 reg = <0x44003000 0x400>;
0696 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
0697 clocks = <&rcc USART6_K>;
0698 wakeup-source;
0699 dmas = <&dmamux1 71 0x400 0x15>,
0700 <&dmamux1 72 0x400 0x11>;
0701 dma-names = "rx", "tx";
0702 status = "disabled";
0703 };
0704
0705 spi1: spi@44004000 {
0706 #address-cells = <1>;
0707 #size-cells = <0>;
0708 compatible = "st,stm32h7-spi";
0709 reg = <0x44004000 0x400>;
0710 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0711 clocks = <&rcc SPI1_K>;
0712 resets = <&rcc SPI1_R>;
0713 dmas = <&dmamux1 37 0x400 0x05>,
0714 <&dmamux1 38 0x400 0x05>;
0715 dma-names = "rx", "tx";
0716 status = "disabled";
0717 };
0718
0719 i2s1: audio-controller@44004000 {
0720 compatible = "st,stm32h7-i2s";
0721 #sound-dai-cells = <0>;
0722 reg = <0x44004000 0x400>;
0723 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
0724 dmas = <&dmamux1 37 0x400 0x01>,
0725 <&dmamux1 38 0x400 0x01>;
0726 dma-names = "rx", "tx";
0727 status = "disabled";
0728 };
0729
0730 spi4: spi@44005000 {
0731 #address-cells = <1>;
0732 #size-cells = <0>;
0733 compatible = "st,stm32h7-spi";
0734 reg = <0x44005000 0x400>;
0735 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0736 clocks = <&rcc SPI4_K>;
0737 resets = <&rcc SPI4_R>;
0738 dmas = <&dmamux1 83 0x400 0x05>,
0739 <&dmamux1 84 0x400 0x05>;
0740 dma-names = "rx", "tx";
0741 status = "disabled";
0742 };
0743
0744 timers15: timer@44006000 {
0745 #address-cells = <1>;
0746 #size-cells = <0>;
0747 compatible = "st,stm32-timers";
0748 reg = <0x44006000 0x400>;
0749 clocks = <&rcc TIM15_K>;
0750 clock-names = "int";
0751 dmas = <&dmamux1 105 0x400 0x1>,
0752 <&dmamux1 106 0x400 0x1>,
0753 <&dmamux1 107 0x400 0x1>,
0754 <&dmamux1 108 0x400 0x1>;
0755 dma-names = "ch1", "up", "trig", "com";
0756 status = "disabled";
0757
0758 pwm {
0759 compatible = "st,stm32-pwm";
0760 #pwm-cells = <3>;
0761 status = "disabled";
0762 };
0763
0764 timer@14 {
0765 compatible = "st,stm32h7-timer-trigger";
0766 reg = <14>;
0767 status = "disabled";
0768 };
0769 };
0770
0771 timers16: timer@44007000 {
0772 #address-cells = <1>;
0773 #size-cells = <0>;
0774 compatible = "st,stm32-timers";
0775 reg = <0x44007000 0x400>;
0776 clocks = <&rcc TIM16_K>;
0777 clock-names = "int";
0778 dmas = <&dmamux1 109 0x400 0x1>,
0779 <&dmamux1 110 0x400 0x1>;
0780 dma-names = "ch1", "up";
0781 status = "disabled";
0782
0783 pwm {
0784 compatible = "st,stm32-pwm";
0785 #pwm-cells = <3>;
0786 status = "disabled";
0787 };
0788 timer@15 {
0789 compatible = "st,stm32h7-timer-trigger";
0790 reg = <15>;
0791 status = "disabled";
0792 };
0793 };
0794
0795 timers17: timer@44008000 {
0796 #address-cells = <1>;
0797 #size-cells = <0>;
0798 compatible = "st,stm32-timers";
0799 reg = <0x44008000 0x400>;
0800 clocks = <&rcc TIM17_K>;
0801 clock-names = "int";
0802 dmas = <&dmamux1 111 0x400 0x1>,
0803 <&dmamux1 112 0x400 0x1>;
0804 dma-names = "ch1", "up";
0805 status = "disabled";
0806
0807 pwm {
0808 compatible = "st,stm32-pwm";
0809 #pwm-cells = <3>;
0810 status = "disabled";
0811 };
0812
0813 timer@16 {
0814 compatible = "st,stm32h7-timer-trigger";
0815 reg = <16>;
0816 status = "disabled";
0817 };
0818 };
0819
0820 spi5: spi@44009000 {
0821 #address-cells = <1>;
0822 #size-cells = <0>;
0823 compatible = "st,stm32h7-spi";
0824 reg = <0x44009000 0x400>;
0825 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
0826 clocks = <&rcc SPI5_K>;
0827 resets = <&rcc SPI5_R>;
0828 dmas = <&dmamux1 85 0x400 0x05>,
0829 <&dmamux1 86 0x400 0x05>;
0830 dma-names = "rx", "tx";
0831 status = "disabled";
0832 };
0833
0834 sai1: sai@4400a000 {
0835 compatible = "st,stm32h7-sai";
0836 #address-cells = <1>;
0837 #size-cells = <1>;
0838 ranges = <0 0x4400a000 0x400>;
0839 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
0840 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0841 resets = <&rcc SAI1_R>;
0842 status = "disabled";
0843
0844 sai1a: audio-controller@4400a004 {
0845 #sound-dai-cells = <0>;
0846
0847 compatible = "st,stm32-sai-sub-a";
0848 reg = <0x4 0x20>;
0849 clocks = <&rcc SAI1_K>;
0850 clock-names = "sai_ck";
0851 dmas = <&dmamux1 87 0x400 0x01>;
0852 status = "disabled";
0853 };
0854
0855 sai1b: audio-controller@4400a024 {
0856 #sound-dai-cells = <0>;
0857 compatible = "st,stm32-sai-sub-b";
0858 reg = <0x24 0x20>;
0859 clocks = <&rcc SAI1_K>;
0860 clock-names = "sai_ck";
0861 dmas = <&dmamux1 88 0x400 0x01>;
0862 status = "disabled";
0863 };
0864 };
0865
0866 sai2: sai@4400b000 {
0867 compatible = "st,stm32h7-sai";
0868 #address-cells = <1>;
0869 #size-cells = <1>;
0870 ranges = <0 0x4400b000 0x400>;
0871 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
0872 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
0873 resets = <&rcc SAI2_R>;
0874 status = "disabled";
0875
0876 sai2a: audio-controller@4400b004 {
0877 #sound-dai-cells = <0>;
0878 compatible = "st,stm32-sai-sub-a";
0879 reg = <0x4 0x20>;
0880 clocks = <&rcc SAI2_K>;
0881 clock-names = "sai_ck";
0882 dmas = <&dmamux1 89 0x400 0x01>;
0883 status = "disabled";
0884 };
0885
0886 sai2b: audio-controller@4400b024 {
0887 #sound-dai-cells = <0>;
0888 compatible = "st,stm32-sai-sub-b";
0889 reg = <0x24 0x20>;
0890 clocks = <&rcc SAI2_K>;
0891 clock-names = "sai_ck";
0892 dmas = <&dmamux1 90 0x400 0x01>;
0893 status = "disabled";
0894 };
0895 };
0896
0897 sai3: sai@4400c000 {
0898 compatible = "st,stm32h7-sai";
0899 #address-cells = <1>;
0900 #size-cells = <1>;
0901 ranges = <0 0x4400c000 0x400>;
0902 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
0903 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0904 resets = <&rcc SAI3_R>;
0905 status = "disabled";
0906
0907 sai3a: audio-controller@4400c004 {
0908 #sound-dai-cells = <0>;
0909 compatible = "st,stm32-sai-sub-a";
0910 reg = <0x04 0x20>;
0911 clocks = <&rcc SAI3_K>;
0912 clock-names = "sai_ck";
0913 dmas = <&dmamux1 113 0x400 0x01>;
0914 status = "disabled";
0915 };
0916
0917 sai3b: audio-controller@4400c024 {
0918 #sound-dai-cells = <0>;
0919 compatible = "st,stm32-sai-sub-b";
0920 reg = <0x24 0x20>;
0921 clocks = <&rcc SAI3_K>;
0922 clock-names = "sai_ck";
0923 dmas = <&dmamux1 114 0x400 0x01>;
0924 status = "disabled";
0925 };
0926 };
0927
0928 dfsdm: dfsdm@4400d000 {
0929 compatible = "st,stm32mp1-dfsdm";
0930 reg = <0x4400d000 0x800>;
0931 clocks = <&rcc DFSDM_K>;
0932 clock-names = "dfsdm";
0933 #address-cells = <1>;
0934 #size-cells = <0>;
0935 status = "disabled";
0936
0937 dfsdm0: filter@0 {
0938 compatible = "st,stm32-dfsdm-adc";
0939 #io-channel-cells = <1>;
0940 reg = <0>;
0941 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
0942 dmas = <&dmamux1 101 0x400 0x01>;
0943 dma-names = "rx";
0944 status = "disabled";
0945 };
0946
0947 dfsdm1: filter@1 {
0948 compatible = "st,stm32-dfsdm-adc";
0949 #io-channel-cells = <1>;
0950 reg = <1>;
0951 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
0952 dmas = <&dmamux1 102 0x400 0x01>;
0953 dma-names = "rx";
0954 status = "disabled";
0955 };
0956
0957 dfsdm2: filter@2 {
0958 compatible = "st,stm32-dfsdm-adc";
0959 #io-channel-cells = <1>;
0960 reg = <2>;
0961 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
0962 dmas = <&dmamux1 103 0x400 0x01>;
0963 dma-names = "rx";
0964 status = "disabled";
0965 };
0966
0967 dfsdm3: filter@3 {
0968 compatible = "st,stm32-dfsdm-adc";
0969 #io-channel-cells = <1>;
0970 reg = <3>;
0971 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
0972 dmas = <&dmamux1 104 0x400 0x01>;
0973 dma-names = "rx";
0974 status = "disabled";
0975 };
0976
0977 dfsdm4: filter@4 {
0978 compatible = "st,stm32-dfsdm-adc";
0979 #io-channel-cells = <1>;
0980 reg = <4>;
0981 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
0982 dmas = <&dmamux1 91 0x400 0x01>;
0983 dma-names = "rx";
0984 status = "disabled";
0985 };
0986
0987 dfsdm5: filter@5 {
0988 compatible = "st,stm32-dfsdm-adc";
0989 #io-channel-cells = <1>;
0990 reg = <5>;
0991 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
0992 dmas = <&dmamux1 92 0x400 0x01>;
0993 dma-names = "rx";
0994 status = "disabled";
0995 };
0996 };
0997
0998 dma1: dma-controller@48000000 {
0999 compatible = "st,stm32-dma";
1000 reg = <0x48000000 0x400>;
1001 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
1002 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1003 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1004 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1005 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1006 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1007 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
1008 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1009 clocks = <&rcc DMA1>;
1010 resets = <&rcc DMA1_R>;
1011 #dma-cells = <4>;
1012 st,mem2mem;
1013 dma-requests = <8>;
1014 };
1015
1016 dma2: dma-controller@48001000 {
1017 compatible = "st,stm32-dma";
1018 reg = <0x48001000 0x400>;
1019 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1020 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1021 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1022 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1023 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1024 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1025 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1026 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1027 clocks = <&rcc DMA2>;
1028 resets = <&rcc DMA2_R>;
1029 #dma-cells = <4>;
1030 st,mem2mem;
1031 dma-requests = <8>;
1032 };
1033
1034 dmamux1: dma-router@48002000 {
1035 compatible = "st,stm32h7-dmamux";
1036 reg = <0x48002000 0x40>;
1037 #dma-cells = <3>;
1038 dma-requests = <128>;
1039 dma-masters = <&dma1 &dma2>;
1040 dma-channels = <16>;
1041 clocks = <&rcc DMAMUX>;
1042 resets = <&rcc DMAMUX_R>;
1043 };
1044
1045 adc: adc@48003000 {
1046 compatible = "st,stm32mp1-adc-core";
1047 reg = <0x48003000 0x400>;
1048 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1049 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1050 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1051 clock-names = "bus", "adc";
1052 interrupt-controller;
1053 st,syscfg = <&syscfg>;
1054 #interrupt-cells = <1>;
1055 #address-cells = <1>;
1056 #size-cells = <0>;
1057 status = "disabled";
1058
1059 adc1: adc@0 {
1060 compatible = "st,stm32mp1-adc";
1061 #io-channel-cells = <1>;
1062 reg = <0x0>;
1063 interrupt-parent = <&adc>;
1064 interrupts = <0>;
1065 dmas = <&dmamux1 9 0x400 0x01>;
1066 dma-names = "rx";
1067 status = "disabled";
1068 };
1069
1070 adc2: adc@100 {
1071 compatible = "st,stm32mp1-adc";
1072 #io-channel-cells = <1>;
1073 reg = <0x100>;
1074 interrupt-parent = <&adc>;
1075 interrupts = <1>;
1076 dmas = <&dmamux1 10 0x400 0x01>;
1077 dma-names = "rx";
1078 status = "disabled";
1079 };
1080 };
1081
1082 sdmmc3: mmc@48004000 {
1083 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1084 arm,primecell-periphid = <0x00253180>;
1085 reg = <0x48004000 0x400>;
1086 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1087 interrupt-names = "cmd_irq";
1088 clocks = <&rcc SDMMC3_K>;
1089 clock-names = "apb_pclk";
1090 resets = <&rcc SDMMC3_R>;
1091 cap-sd-highspeed;
1092 cap-mmc-highspeed;
1093 max-frequency = <120000000>;
1094 status = "disabled";
1095 };
1096
1097 usbotg_hs: usb-otg@49000000 {
1098 compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1099 reg = <0x49000000 0x10000>;
1100 clocks = <&rcc USBO_K>;
1101 clock-names = "otg";
1102 resets = <&rcc USBO_R>;
1103 reset-names = "dwc2";
1104 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1105 g-rx-fifo-size = <512>;
1106 g-np-tx-fifo-size = <32>;
1107 g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
1108 dr_mode = "otg";
1109 otg-rev = <0x200>;
1110 usb33d-supply = <&usb33>;
1111 status = "disabled";
1112 };
1113
1114 ipcc: mailbox@4c001000 {
1115 compatible = "st,stm32mp1-ipcc";
1116 #mbox-cells = <1>;
1117 reg = <0x4c001000 0x400>;
1118 st,proc-id = <0>;
1119 interrupts-extended =
1120 <&exti 61 1>,
1121 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1122 interrupt-names = "rx", "tx";
1123 clocks = <&rcc IPCC>;
1124 wakeup-source;
1125 status = "disabled";
1126 };
1127
1128 dcmi: dcmi@4c006000 {
1129 compatible = "st,stm32-dcmi";
1130 reg = <0x4c006000 0x400>;
1131 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1132 resets = <&rcc CAMITF_R>;
1133 clocks = <&rcc DCMI>;
1134 clock-names = "mclk";
1135 dmas = <&dmamux1 75 0x400 0x01>;
1136 dma-names = "tx";
1137 status = "disabled";
1138 };
1139
1140 rcc: rcc@50000000 {
1141 compatible = "st,stm32mp1-rcc", "syscon";
1142 reg = <0x50000000 0x1000>;
1143 #clock-cells = <1>;
1144 #reset-cells = <1>;
1145 };
1146
1147 pwr_regulators: pwr@50001000 {
1148 compatible = "st,stm32mp1,pwr-reg";
1149 reg = <0x50001000 0x10>;
1150
1151 reg11: reg11 {
1152 regulator-name = "reg11";
1153 regulator-min-microvolt = <1100000>;
1154 regulator-max-microvolt = <1100000>;
1155 };
1156
1157 reg18: reg18 {
1158 regulator-name = "reg18";
1159 regulator-min-microvolt = <1800000>;
1160 regulator-max-microvolt = <1800000>;
1161 };
1162
1163 usb33: usb33 {
1164 regulator-name = "usb33";
1165 regulator-min-microvolt = <3300000>;
1166 regulator-max-microvolt = <3300000>;
1167 };
1168 };
1169
1170 pwr_mcu: pwr_mcu@50001014 {
1171 compatible = "st,stm32mp151-pwr-mcu", "syscon";
1172 reg = <0x50001014 0x4>;
1173 };
1174
1175 exti: interrupt-controller@5000d000 {
1176 compatible = "st,stm32mp1-exti", "syscon";
1177 interrupt-controller;
1178 #interrupt-cells = <2>;
1179 reg = <0x5000d000 0x400>;
1180 };
1181
1182 syscfg: syscon@50020000 {
1183 compatible = "st,stm32mp157-syscfg", "syscon";
1184 reg = <0x50020000 0x400>;
1185 clocks = <&rcc SYSCFG>;
1186 };
1187
1188 lptimer2: timer@50021000 {
1189 #address-cells = <1>;
1190 #size-cells = <0>;
1191 compatible = "st,stm32-lptimer";
1192 reg = <0x50021000 0x400>;
1193 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&rcc LPTIM2_K>;
1195 clock-names = "mux";
1196 wakeup-source;
1197 status = "disabled";
1198
1199 pwm {
1200 compatible = "st,stm32-pwm-lp";
1201 #pwm-cells = <3>;
1202 status = "disabled";
1203 };
1204
1205 trigger@1 {
1206 compatible = "st,stm32-lptimer-trigger";
1207 reg = <1>;
1208 status = "disabled";
1209 };
1210
1211 counter {
1212 compatible = "st,stm32-lptimer-counter";
1213 status = "disabled";
1214 };
1215 };
1216
1217 lptimer3: timer@50022000 {
1218 #address-cells = <1>;
1219 #size-cells = <0>;
1220 compatible = "st,stm32-lptimer";
1221 reg = <0x50022000 0x400>;
1222 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
1223 clocks = <&rcc LPTIM3_K>;
1224 clock-names = "mux";
1225 wakeup-source;
1226 status = "disabled";
1227
1228 pwm {
1229 compatible = "st,stm32-pwm-lp";
1230 #pwm-cells = <3>;
1231 status = "disabled";
1232 };
1233
1234 trigger@2 {
1235 compatible = "st,stm32-lptimer-trigger";
1236 reg = <2>;
1237 status = "disabled";
1238 };
1239 };
1240
1241 lptimer4: timer@50023000 {
1242 compatible = "st,stm32-lptimer";
1243 reg = <0x50023000 0x400>;
1244 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
1245 clocks = <&rcc LPTIM4_K>;
1246 clock-names = "mux";
1247 wakeup-source;
1248 status = "disabled";
1249
1250 pwm {
1251 compatible = "st,stm32-pwm-lp";
1252 #pwm-cells = <3>;
1253 status = "disabled";
1254 };
1255 };
1256
1257 lptimer5: timer@50024000 {
1258 compatible = "st,stm32-lptimer";
1259 reg = <0x50024000 0x400>;
1260 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
1261 clocks = <&rcc LPTIM5_K>;
1262 clock-names = "mux";
1263 wakeup-source;
1264 status = "disabled";
1265
1266 pwm {
1267 compatible = "st,stm32-pwm-lp";
1268 #pwm-cells = <3>;
1269 status = "disabled";
1270 };
1271 };
1272
1273 vrefbuf: vrefbuf@50025000 {
1274 compatible = "st,stm32-vrefbuf";
1275 reg = <0x50025000 0x8>;
1276 regulator-min-microvolt = <1500000>;
1277 regulator-max-microvolt = <2500000>;
1278 clocks = <&rcc VREF>;
1279 status = "disabled";
1280 };
1281
1282 sai4: sai@50027000 {
1283 compatible = "st,stm32h7-sai";
1284 #address-cells = <1>;
1285 #size-cells = <1>;
1286 ranges = <0 0x50027000 0x400>;
1287 reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1288 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1289 resets = <&rcc SAI4_R>;
1290 status = "disabled";
1291
1292 sai4a: audio-controller@50027004 {
1293 #sound-dai-cells = <0>;
1294 compatible = "st,stm32-sai-sub-a";
1295 reg = <0x04 0x20>;
1296 clocks = <&rcc SAI4_K>;
1297 clock-names = "sai_ck";
1298 dmas = <&dmamux1 99 0x400 0x01>;
1299 status = "disabled";
1300 };
1301
1302 sai4b: audio-controller@50027024 {
1303 #sound-dai-cells = <0>;
1304 compatible = "st,stm32-sai-sub-b";
1305 reg = <0x24 0x20>;
1306 clocks = <&rcc SAI4_K>;
1307 clock-names = "sai_ck";
1308 dmas = <&dmamux1 100 0x400 0x01>;
1309 status = "disabled";
1310 };
1311 };
1312
1313 dts: thermal@50028000 {
1314 compatible = "st,stm32-thermal";
1315 reg = <0x50028000 0x100>;
1316 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1317 clocks = <&rcc TMPSENS>;
1318 clock-names = "pclk";
1319 #thermal-sensor-cells = <0>;
1320 status = "disabled";
1321 };
1322
1323 hash1: hash@54002000 {
1324 compatible = "st,stm32f756-hash";
1325 reg = <0x54002000 0x400>;
1326 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1327 clocks = <&rcc HASH1>;
1328 resets = <&rcc HASH1_R>;
1329 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
1330 dma-names = "in";
1331 dma-maxburst = <2>;
1332 status = "disabled";
1333 };
1334
1335 rng1: rng@54003000 {
1336 compatible = "st,stm32-rng";
1337 reg = <0x54003000 0x400>;
1338 clocks = <&rcc RNG1_K>;
1339 resets = <&rcc RNG1_R>;
1340 status = "disabled";
1341 };
1342
1343 mdma1: dma-controller@58000000 {
1344 compatible = "st,stm32h7-mdma";
1345 reg = <0x58000000 0x1000>;
1346 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&rcc MDMA>;
1348 resets = <&rcc MDMA_R>;
1349 #dma-cells = <5>;
1350 dma-channels = <32>;
1351 dma-requests = <48>;
1352 };
1353
1354 fmc: memory-controller@58002000 {
1355 #address-cells = <2>;
1356 #size-cells = <1>;
1357 compatible = "st,stm32mp1-fmc2-ebi";
1358 reg = <0x58002000 0x1000>;
1359 clocks = <&rcc FMC_K>;
1360 resets = <&rcc FMC_R>;
1361 status = "disabled";
1362
1363 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1364 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1365 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1366 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1367 <4 0 0x80000000 0x10000000>; /* NAND */
1368
1369 nand-controller@4,0 {
1370 #address-cells = <1>;
1371 #size-cells = <0>;
1372 compatible = "st,stm32mp1-fmc2-nfc";
1373 reg = <4 0x00000000 0x1000>,
1374 <4 0x08010000 0x1000>,
1375 <4 0x08020000 0x1000>,
1376 <4 0x01000000 0x1000>,
1377 <4 0x09010000 0x1000>,
1378 <4 0x09020000 0x1000>;
1379 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1380 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
1381 <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
1382 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
1383 dma-names = "tx", "rx", "ecc";
1384 status = "disabled";
1385 };
1386 };
1387
1388 qspi: spi@58003000 {
1389 compatible = "st,stm32f469-qspi";
1390 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1391 reg-names = "qspi", "qspi_mm";
1392 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1393 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
1394 <&mdma1 22 0x2 0x10100008 0x0 0x0>;
1395 dma-names = "tx", "rx";
1396 clocks = <&rcc QSPI_K>;
1397 resets = <&rcc QSPI_R>;
1398 #address-cells = <1>;
1399 #size-cells = <0>;
1400 status = "disabled";
1401 };
1402
1403 sdmmc1: mmc@58005000 {
1404 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1405 arm,primecell-periphid = <0x00253180>;
1406 reg = <0x58005000 0x1000>;
1407 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1408 interrupt-names = "cmd_irq";
1409 clocks = <&rcc SDMMC1_K>;
1410 clock-names = "apb_pclk";
1411 resets = <&rcc SDMMC1_R>;
1412 cap-sd-highspeed;
1413 cap-mmc-highspeed;
1414 max-frequency = <120000000>;
1415 status = "disabled";
1416 };
1417
1418 sdmmc2: mmc@58007000 {
1419 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1420 arm,primecell-periphid = <0x00253180>;
1421 reg = <0x58007000 0x1000>;
1422 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1423 interrupt-names = "cmd_irq";
1424 clocks = <&rcc SDMMC2_K>;
1425 clock-names = "apb_pclk";
1426 resets = <&rcc SDMMC2_R>;
1427 cap-sd-highspeed;
1428 cap-mmc-highspeed;
1429 max-frequency = <120000000>;
1430 status = "disabled";
1431 };
1432
1433 crc1: crc@58009000 {
1434 compatible = "st,stm32f7-crc";
1435 reg = <0x58009000 0x400>;
1436 clocks = <&rcc CRC1>;
1437 status = "disabled";
1438 };
1439
1440 ethernet0: ethernet@5800a000 {
1441 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1442 reg = <0x5800a000 0x2000>;
1443 reg-names = "stmmaceth";
1444 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1445 interrupt-names = "macirq";
1446 clock-names = "stmmaceth",
1447 "mac-clk-tx",
1448 "mac-clk-rx",
1449 "eth-ck",
1450 "ptp_ref",
1451 "ethstp";
1452 clocks = <&rcc ETHMAC>,
1453 <&rcc ETHTX>,
1454 <&rcc ETHRX>,
1455 <&rcc ETHCK_K>,
1456 <&rcc ETHPTP_K>,
1457 <&rcc ETHSTP>;
1458 st,syscon = <&syscfg 0x4>;
1459 snps,mixed-burst;
1460 snps,pbl = <2>;
1461 snps,en-tx-lpi-clockgating;
1462 snps,axi-config = <&stmmac_axi_config_0>;
1463 snps,tso;
1464 status = "disabled";
1465
1466 stmmac_axi_config_0: stmmac-axi-config {
1467 snps,wr_osr_lmt = <0x7>;
1468 snps,rd_osr_lmt = <0x7>;
1469 snps,blen = <0 0 0 0 16 8 4>;
1470 };
1471 };
1472
1473 usbh_ohci: usb@5800c000 {
1474 compatible = "generic-ohci";
1475 reg = <0x5800c000 0x1000>;
1476 clocks = <&usbphyc>, <&rcc USBH>;
1477 resets = <&rcc USBH_R>;
1478 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1479 status = "disabled";
1480 };
1481
1482 usbh_ehci: usb@5800d000 {
1483 compatible = "generic-ehci";
1484 reg = <0x5800d000 0x1000>;
1485 clocks = <&usbphyc>, <&rcc USBH>;
1486 resets = <&rcc USBH_R>;
1487 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1488 companion = <&usbh_ohci>;
1489 status = "disabled";
1490 };
1491
1492 ltdc: display-controller@5a001000 {
1493 compatible = "st,stm32-ltdc";
1494 reg = <0x5a001000 0x400>;
1495 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1496 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1497 clocks = <&rcc LTDC_PX>;
1498 clock-names = "lcd";
1499 resets = <&rcc LTDC_R>;
1500 status = "disabled";
1501
1502 port {
1503 #address-cells = <1>;
1504 #size-cells = <0>;
1505 };
1506 };
1507
1508 iwdg2: watchdog@5a002000 {
1509 compatible = "st,stm32mp1-iwdg";
1510 reg = <0x5a002000 0x400>;
1511 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1512 clock-names = "pclk", "lsi";
1513 status = "disabled";
1514 };
1515
1516 usbphyc: usbphyc@5a006000 {
1517 #address-cells = <1>;
1518 #size-cells = <0>;
1519 #clock-cells = <0>;
1520 compatible = "st,stm32mp1-usbphyc";
1521 reg = <0x5a006000 0x1000>;
1522 clocks = <&rcc USBPHY_K>;
1523 resets = <&rcc USBPHY_R>;
1524 vdda1v1-supply = <®11>;
1525 vdda1v8-supply = <®18>;
1526 status = "disabled";
1527
1528 usbphyc_port0: usb-phy@0 {
1529 #phy-cells = <0>;
1530 reg = <0>;
1531 };
1532
1533 usbphyc_port1: usb-phy@1 {
1534 #phy-cells = <1>;
1535 reg = <1>;
1536 };
1537 };
1538
1539 usart1: serial@5c000000 {
1540 compatible = "st,stm32h7-uart";
1541 reg = <0x5c000000 0x400>;
1542 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
1543 clocks = <&rcc USART1_K>;
1544 wakeup-source;
1545 status = "disabled";
1546 };
1547
1548 spi6: spi@5c001000 {
1549 #address-cells = <1>;
1550 #size-cells = <0>;
1551 compatible = "st,stm32h7-spi";
1552 reg = <0x5c001000 0x400>;
1553 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1554 clocks = <&rcc SPI6_K>;
1555 resets = <&rcc SPI6_R>;
1556 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1557 <&mdma1 35 0x0 0x40002 0x0 0x0>;
1558 dma-names = "rx", "tx";
1559 status = "disabled";
1560 };
1561
1562 i2c4: i2c@5c002000 {
1563 compatible = "st,stm32mp15-i2c";
1564 reg = <0x5c002000 0x400>;
1565 interrupt-names = "event", "error";
1566 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1567 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1568 clocks = <&rcc I2C4_K>;
1569 resets = <&rcc I2C4_R>;
1570 #address-cells = <1>;
1571 #size-cells = <0>;
1572 st,syscfg-fmp = <&syscfg 0x4 0x8>;
1573 wakeup-source;
1574 i2c-analog-filter;
1575 status = "disabled";
1576 };
1577
1578 rtc: rtc@5c004000 {
1579 compatible = "st,stm32mp1-rtc";
1580 reg = <0x5c004000 0x400>;
1581 clocks = <&rcc RTCAPB>, <&rcc RTC>;
1582 clock-names = "pclk", "rtc_ck";
1583 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
1584 status = "disabled";
1585 };
1586
1587 bsec: efuse@5c005000 {
1588 compatible = "st,stm32mp15-bsec";
1589 reg = <0x5c005000 0x400>;
1590 #address-cells = <1>;
1591 #size-cells = <1>;
1592 ts_cal1: calib@5c {
1593 reg = <0x5c 0x2>;
1594 };
1595 ts_cal2: calib@5e {
1596 reg = <0x5e 0x2>;
1597 };
1598 };
1599
1600 i2c6: i2c@5c009000 {
1601 compatible = "st,stm32mp15-i2c";
1602 reg = <0x5c009000 0x400>;
1603 interrupt-names = "event", "error";
1604 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1605 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1606 clocks = <&rcc I2C6_K>;
1607 resets = <&rcc I2C6_R>;
1608 #address-cells = <1>;
1609 #size-cells = <0>;
1610 st,syscfg-fmp = <&syscfg 0x4 0x20>;
1611 wakeup-source;
1612 i2c-analog-filter;
1613 status = "disabled";
1614 };
1615
1616 tamp: tamp@5c00a000 {
1617 compatible = "st,stm32-tamp", "syscon", "simple-mfd";
1618 reg = <0x5c00a000 0x400>;
1619 };
1620
1621 /*
1622 * Break node order to solve dependency probe issue between
1623 * pinctrl and exti.
1624 */
1625 pinctrl: pinctrl@50002000 {
1626 #address-cells = <1>;
1627 #size-cells = <1>;
1628 compatible = "st,stm32mp157-pinctrl";
1629 ranges = <0 0x50002000 0xa400>;
1630 interrupt-parent = <&exti>;
1631 st,syscfg = <&exti 0x60 0xff>;
1632 pins-are-numbered;
1633
1634 gpioa: gpio@50002000 {
1635 gpio-controller;
1636 #gpio-cells = <2>;
1637 interrupt-controller;
1638 #interrupt-cells = <2>;
1639 reg = <0x0 0x400>;
1640 clocks = <&rcc GPIOA>;
1641 st,bank-name = "GPIOA";
1642 status = "disabled";
1643 };
1644
1645 gpiob: gpio@50003000 {
1646 gpio-controller;
1647 #gpio-cells = <2>;
1648 interrupt-controller;
1649 #interrupt-cells = <2>;
1650 reg = <0x1000 0x400>;
1651 clocks = <&rcc GPIOB>;
1652 st,bank-name = "GPIOB";
1653 status = "disabled";
1654 };
1655
1656 gpioc: gpio@50004000 {
1657 gpio-controller;
1658 #gpio-cells = <2>;
1659 interrupt-controller;
1660 #interrupt-cells = <2>;
1661 reg = <0x2000 0x400>;
1662 clocks = <&rcc GPIOC>;
1663 st,bank-name = "GPIOC";
1664 status = "disabled";
1665 };
1666
1667 gpiod: gpio@50005000 {
1668 gpio-controller;
1669 #gpio-cells = <2>;
1670 interrupt-controller;
1671 #interrupt-cells = <2>;
1672 reg = <0x3000 0x400>;
1673 clocks = <&rcc GPIOD>;
1674 st,bank-name = "GPIOD";
1675 status = "disabled";
1676 };
1677
1678 gpioe: gpio@50006000 {
1679 gpio-controller;
1680 #gpio-cells = <2>;
1681 interrupt-controller;
1682 #interrupt-cells = <2>;
1683 reg = <0x4000 0x400>;
1684 clocks = <&rcc GPIOE>;
1685 st,bank-name = "GPIOE";
1686 status = "disabled";
1687 };
1688
1689 gpiof: gpio@50007000 {
1690 gpio-controller;
1691 #gpio-cells = <2>;
1692 interrupt-controller;
1693 #interrupt-cells = <2>;
1694 reg = <0x5000 0x400>;
1695 clocks = <&rcc GPIOF>;
1696 st,bank-name = "GPIOF";
1697 status = "disabled";
1698 };
1699
1700 gpiog: gpio@50008000 {
1701 gpio-controller;
1702 #gpio-cells = <2>;
1703 interrupt-controller;
1704 #interrupt-cells = <2>;
1705 reg = <0x6000 0x400>;
1706 clocks = <&rcc GPIOG>;
1707 st,bank-name = "GPIOG";
1708 status = "disabled";
1709 };
1710
1711 gpioh: gpio@50009000 {
1712 gpio-controller;
1713 #gpio-cells = <2>;
1714 interrupt-controller;
1715 #interrupt-cells = <2>;
1716 reg = <0x7000 0x400>;
1717 clocks = <&rcc GPIOH>;
1718 st,bank-name = "GPIOH";
1719 status = "disabled";
1720 };
1721
1722 gpioi: gpio@5000a000 {
1723 gpio-controller;
1724 #gpio-cells = <2>;
1725 interrupt-controller;
1726 #interrupt-cells = <2>;
1727 reg = <0x8000 0x400>;
1728 clocks = <&rcc GPIOI>;
1729 st,bank-name = "GPIOI";
1730 status = "disabled";
1731 };
1732
1733 gpioj: gpio@5000b000 {
1734 gpio-controller;
1735 #gpio-cells = <2>;
1736 interrupt-controller;
1737 #interrupt-cells = <2>;
1738 reg = <0x9000 0x400>;
1739 clocks = <&rcc GPIOJ>;
1740 st,bank-name = "GPIOJ";
1741 status = "disabled";
1742 };
1743
1744 gpiok: gpio@5000c000 {
1745 gpio-controller;
1746 #gpio-cells = <2>;
1747 interrupt-controller;
1748 #interrupt-cells = <2>;
1749 reg = <0xa000 0x400>;
1750 clocks = <&rcc GPIOK>;
1751 st,bank-name = "GPIOK";
1752 status = "disabled";
1753 };
1754 };
1755
1756 pinctrl_z: pinctrl@54004000 {
1757 #address-cells = <1>;
1758 #size-cells = <1>;
1759 compatible = "st,stm32mp157-z-pinctrl";
1760 ranges = <0 0x54004000 0x400>;
1761 pins-are-numbered;
1762 interrupt-parent = <&exti>;
1763 st,syscfg = <&exti 0x60 0xff>;
1764
1765 gpioz: gpio@54004000 {
1766 gpio-controller;
1767 #gpio-cells = <2>;
1768 interrupt-controller;
1769 #interrupt-cells = <2>;
1770 reg = <0 0x400>;
1771 clocks = <&rcc GPIOZ>;
1772 st,bank-name = "GPIOZ";
1773 st,bank-ioport = <11>;
1774 status = "disabled";
1775 };
1776 };
1777 };
1778
1779 mlahb: ahb {
1780 compatible = "st,mlahb", "simple-bus";
1781 #address-cells = <1>;
1782 #size-cells = <1>;
1783 ranges;
1784 dma-ranges = <0x00000000 0x38000000 0x10000>,
1785 <0x10000000 0x10000000 0x60000>,
1786 <0x30000000 0x30000000 0x60000>;
1787
1788 m4_rproc: m4@10000000 {
1789 compatible = "st,stm32mp1-m4";
1790 reg = <0x10000000 0x40000>,
1791 <0x30000000 0x40000>,
1792 <0x38000000 0x10000>;
1793 resets = <&rcc MCU_R>;
1794 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1795 st,syscfg-tz = <&rcc 0x000 0x1>;
1796 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
1797 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
1798 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
1799 status = "disabled";
1800 };
1801 };
1802 };
