0001 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
0002 /*
0003 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
0004 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
0005 */
0006 #include <dt-bindings/interrupt-controller/arm-gic.h>
0007 #include <dt-bindings/clock/stm32mp13-clks.h>
0008 #include <dt-bindings/reset/stm32mp13-resets.h>
0009
0010 / {
0011 #address-cells = <1>;
0012 #size-cells = <1>;
0013
0014 cpus {
0015 #address-cells = <1>;
0016 #size-cells = <0>;
0017
0018 cpu0: cpu@0 {
0019 compatible = "arm,cortex-a7";
0020 device_type = "cpu";
0021 reg = <0>;
0022 };
0023 };
0024
0025 arm-pmu {
0026 compatible = "arm,cortex-a7-pmu";
0027 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
0028 interrupt-affinity = <&cpu0>;
0029 interrupt-parent = <&intc>;
0030 };
0031
0032 firmware {
0033 optee {
0034 method = "smc";
0035 compatible = "linaro,optee-tz";
0036 };
0037
0038 scmi: scmi {
0039 compatible = "linaro,scmi-optee";
0040 #address-cells = <1>;
0041 #size-cells = <0>;
0042 linaro,optee-channel-id = <0>;
0043 shmem = <&scmi_shm>;
0044
0045 scmi_clk: protocol@14 {
0046 reg = <0x14>;
0047 #clock-cells = <1>;
0048 };
0049
0050 scmi_reset: protocol@16 {
0051 reg = <0x16>;
0052 #reset-cells = <1>;
0053 };
0054 };
0055 };
0056
0057 intc: interrupt-controller@a0021000 {
0058 compatible = "arm,cortex-a7-gic";
0059 #interrupt-cells = <3>;
0060 interrupt-controller;
0061 reg = <0xa0021000 0x1000>,
0062 <0xa0022000 0x2000>;
0063 };
0064
0065 psci {
0066 compatible = "arm,psci-1.0";
0067 method = "smc";
0068 };
0069
0070 timer {
0071 compatible = "arm,armv7-timer";
0072 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0073 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0074 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
0075 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
0076 interrupt-parent = <&intc>;
0077 always-on;
0078 };
0079
0080 soc {
0081 compatible = "simple-bus";
0082 #address-cells = <1>;
0083 #size-cells = <1>;
0084 interrupt-parent = <&intc>;
0085 ranges;
0086
0087 scmi_sram: sram@2ffff000 {
0088 compatible = "mmio-sram";
0089 reg = <0x2ffff000 0x1000>;
0090 #address-cells = <1>;
0091 #size-cells = <1>;
0092 ranges = <0 0x2ffff000 0x1000>;
0093
0094 scmi_shm: scmi-sram@0 {
0095 compatible = "arm,scmi-shmem";
0096 reg = <0 0x80>;
0097 };
0098 };
0099
0100 uart4: serial@40010000 {
0101 compatible = "st,stm32h7-uart";
0102 reg = <0x40010000 0x400>;
0103 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
0104 clocks = <&rcc UART4_K>;
0105 resets = <&rcc UART4_R>;
0106 status = "disabled";
0107 };
0108
0109 dma1: dma-controller@48000000 {
0110 compatible = "st,stm32-dma";
0111 reg = <0x48000000 0x400>;
0112 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0113 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
0114 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0115 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
0116 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
0117 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
0118 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
0119 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
0120 clocks = <&rcc DMA1>;
0121 resets = <&rcc DMA1_R>;
0122 #dma-cells = <4>;
0123 st,mem2mem;
0124 dma-requests = <8>;
0125 };
0126
0127 dma2: dma-controller@48001000 {
0128 compatible = "st,stm32-dma";
0129 reg = <0x48001000 0x400>;
0130 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
0131 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
0132 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
0133 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
0134 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
0135 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
0136 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
0137 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0138 clocks = <&rcc DMA2>;
0139 resets = <&rcc DMA2_R>;
0140 #dma-cells = <4>;
0141 st,mem2mem;
0142 dma-requests = <8>;
0143 };
0144
0145 dmamux1: dma-router@48002000 {
0146 compatible = "st,stm32h7-dmamux";
0147 reg = <0x48002000 0x40>;
0148 clocks = <&rcc DMAMUX1>;
0149 resets = <&rcc DMAMUX1_R>;
0150 #dma-cells = <3>;
0151 dma-masters = <&dma1 &dma2>;
0152 dma-requests = <128>;
0153 dma-channels = <16>;
0154 };
0155
0156 rcc: rcc@50000000 {
0157 compatible = "st,stm32mp13-rcc", "syscon";
0158 reg = <0x50000000 0x1000>;
0159 #clock-cells = <1>;
0160 #reset-cells = <1>;
0161 clock-names = "hse", "hsi", "csi", "lse", "lsi";
0162 clocks = <&scmi_clk CK_SCMI_HSE>,
0163 <&scmi_clk CK_SCMI_HSI>,
0164 <&scmi_clk CK_SCMI_CSI>,
0165 <&scmi_clk CK_SCMI_LSE>,
0166 <&scmi_clk CK_SCMI_LSI>;
0167 };
0168
0169 exti: interrupt-controller@5000d000 {
0170 compatible = "st,stm32mp13-exti", "syscon";
0171 interrupt-controller;
0172 #interrupt-cells = <2>;
0173 reg = <0x5000d000 0x400>;
0174 };
0175
0176 syscfg: syscon@50020000 {
0177 compatible = "st,stm32mp157-syscfg", "syscon";
0178 reg = <0x50020000 0x400>;
0179 clocks = <&rcc SYSCFG>;
0180 };
0181
0182 mdma: dma-controller@58000000 {
0183 compatible = "st,stm32h7-mdma";
0184 reg = <0x58000000 0x1000>;
0185 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
0186 clocks = <&rcc MDMA>;
0187 #dma-cells = <5>;
0188 dma-channels = <32>;
0189 dma-requests = <48>;
0190 };
0191
0192 sdmmc1: mmc@58005000 {
0193 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
0194 arm,primecell-periphid = <0x20253180>;
0195 reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
0196 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0197 interrupt-names = "cmd_irq";
0198 clocks = <&rcc SDMMC1_K>;
0199 clock-names = "apb_pclk";
0200 resets = <&rcc SDMMC1_R>;
0201 cap-sd-highspeed;
0202 cap-mmc-highspeed;
0203 max-frequency = <130000000>;
0204 status = "disabled";
0205 };
0206
0207 sdmmc2: mmc@58007000 {
0208 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
0209 arm,primecell-periphid = <0x20253180>;
0210 reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
0211 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
0212 interrupt-names = "cmd_irq";
0213 clocks = <&rcc SDMMC2_K>;
0214 clock-names = "apb_pclk";
0215 resets = <&rcc SDMMC2_R>;
0216 cap-sd-highspeed;
0217 cap-mmc-highspeed;
0218 max-frequency = <130000000>;
0219 status = "disabled";
0220 };
0221
0222 iwdg2: watchdog@5a002000 {
0223 compatible = "st,stm32mp1-iwdg";
0224 reg = <0x5a002000 0x400>;
0225 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
0226 clock-names = "pclk", "lsi";
0227 status = "disabled";
0228 };
0229
0230 rtc: rtc@5c004000 {
0231 compatible = "st,stm32mp1-rtc";
0232 reg = <0x5c004000 0x400>;
0233 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
0234 clocks = <&scmi_clk CK_SCMI_RTCAPB>,
0235 <&scmi_clk CK_SCMI_RTC>;
0236 clock-names = "pclk", "rtc_ck";
0237 status = "disabled";
0238 };
0239
0240 bsec: efuse@5c005000 {
0241 compatible = "st,stm32mp15-bsec";
0242 reg = <0x5c005000 0x400>;
0243 #address-cells = <1>;
0244 #size-cells = <1>;
0245
0246 part_number_otp: part_number_otp@4 {
0247 reg = <0x4 0x2>;
0248 };
0249 ts_cal1: calib@5c {
0250 reg = <0x5c 0x2>;
0251 };
0252 ts_cal2: calib@5e {
0253 reg = <0x5e 0x2>;
0254 };
0255 };
0256
0257 /*
0258 * Break node order to solve dependency probe issue between
0259 * pinctrl and exti.
0260 */
0261 pinctrl: pinctrl@50002000 {
0262 #address-cells = <1>;
0263 #size-cells = <1>;
0264 compatible = "st,stm32mp135-pinctrl";
0265 ranges = <0 0x50002000 0x8400>;
0266 interrupt-parent = <&exti>;
0267 st,syscfg = <&exti 0x60 0xff>;
0268 pins-are-numbered;
0269
0270 gpioa: gpio@50002000 {
0271 gpio-controller;
0272 #gpio-cells = <2>;
0273 interrupt-controller;
0274 #interrupt-cells = <2>;
0275 reg = <0x0 0x400>;
0276 clocks = <&rcc GPIOA>;
0277 st,bank-name = "GPIOA";
0278 ngpios = <16>;
0279 gpio-ranges = <&pinctrl 0 0 16>;
0280 };
0281
0282 gpiob: gpio@50003000 {
0283 gpio-controller;
0284 #gpio-cells = <2>;
0285 interrupt-controller;
0286 #interrupt-cells = <2>;
0287 reg = <0x1000 0x400>;
0288 clocks = <&rcc GPIOB>;
0289 st,bank-name = "GPIOB";
0290 ngpios = <16>;
0291 gpio-ranges = <&pinctrl 0 16 16>;
0292 };
0293
0294 gpioc: gpio@50004000 {
0295 gpio-controller;
0296 #gpio-cells = <2>;
0297 interrupt-controller;
0298 #interrupt-cells = <2>;
0299 reg = <0x2000 0x400>;
0300 clocks = <&rcc GPIOC>;
0301 st,bank-name = "GPIOC";
0302 ngpios = <16>;
0303 gpio-ranges = <&pinctrl 0 32 16>;
0304 };
0305
0306 gpiod: gpio@50005000 {
0307 gpio-controller;
0308 #gpio-cells = <2>;
0309 interrupt-controller;
0310 #interrupt-cells = <2>;
0311 reg = <0x3000 0x400>;
0312 clocks = <&rcc GPIOD>;
0313 st,bank-name = "GPIOD";
0314 ngpios = <16>;
0315 gpio-ranges = <&pinctrl 0 48 16>;
0316 };
0317
0318 gpioe: gpio@50006000 {
0319 gpio-controller;
0320 #gpio-cells = <2>;
0321 interrupt-controller;
0322 #interrupt-cells = <2>;
0323 reg = <0x4000 0x400>;
0324 clocks = <&rcc GPIOE>;
0325 st,bank-name = "GPIOE";
0326 ngpios = <16>;
0327 gpio-ranges = <&pinctrl 0 64 16>;
0328 };
0329
0330 gpiof: gpio@50007000 {
0331 gpio-controller;
0332 #gpio-cells = <2>;
0333 interrupt-controller;
0334 #interrupt-cells = <2>;
0335 reg = <0x5000 0x400>;
0336 clocks = <&rcc GPIOF>;
0337 st,bank-name = "GPIOF";
0338 ngpios = <16>;
0339 gpio-ranges = <&pinctrl 0 80 16>;
0340 };
0341
0342 gpiog: gpio@50008000 {
0343 gpio-controller;
0344 #gpio-cells = <2>;
0345 interrupt-controller;
0346 #interrupt-cells = <2>;
0347 reg = <0x6000 0x400>;
0348 clocks = <&rcc GPIOG>;
0349 st,bank-name = "GPIOG";
0350 ngpios = <16>;
0351 gpio-ranges = <&pinctrl 0 96 16>;
0352 };
0353
0354 gpioh: gpio@50009000 {
0355 gpio-controller;
0356 #gpio-cells = <2>;
0357 interrupt-controller;
0358 #interrupt-cells = <2>;
0359 reg = <0x7000 0x400>;
0360 clocks = <&rcc GPIOH>;
0361 st,bank-name = "GPIOH";
0362 ngpios = <15>;
0363 gpio-ranges = <&pinctrl 0 112 15>;
0364 };
0365
0366 gpioi: gpio@5000a000 {
0367 gpio-controller;
0368 #gpio-cells = <2>;
0369 interrupt-controller;
0370 #interrupt-cells = <2>;
0371 reg = <0x8000 0x400>;
0372 clocks = <&rcc GPIOI>;
0373 st,bank-name = "GPIOI";
0374 ngpios = <8>;
0375 gpio-ranges = <&pinctrl 0 128 8>;
0376 };
0377 };
0378 };
0379 };
