0001 /*
0002 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
0003 *
0004 * This file is dual-licensed: you can use it either under the terms
0005 * of the GPL or the X11 license, at your option. Note that this dual
0006 * licensing only applies to this file, and not this project as a
0007 * whole.
0008 *
0009 * a) This file is free software; you can redistribute it and/or
0010 * modify it under the terms of the GNU General Public License as
0011 * published by the Free Software Foundation; either version 2 of the
0012 * License, or (at your option) any later version.
0013 *
0014 * This file is distributed in the hope that it will be useful,
0015 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0017 * GNU General Public License for more details.
0018 *
0019 * Or, alternatively,
0020 *
0021 * b) Permission is hereby granted, free of charge, to any person
0022 * obtaining a copy of this software and associated documentation
0023 * files (the "Software"), to deal in the Software without
0024 * restriction, including without limitation the rights to use,
0025 * copy, modify, merge, publish, distribute, sublicense, and/or
0026 * sell copies of the Software, and to permit persons to whom the
0027 * Software is furnished to do so, subject to the following
0028 * conditions:
0029 *
0030 * The above copyright notice and this permission notice shall be
0031 * included in all copies or substantial portions of the Software.
0032 *
0033 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0034 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0035 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0036 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0037 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0038 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0039 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0040 * OTHER DEALINGS IN THE SOFTWARE.
0041 */
0042
0043 #include "armv7-m.dtsi"
0044 #include <dt-bindings/clock/stm32h7-clks.h>
0045 #include <dt-bindings/mfd/stm32h7-rcc.h>
0046 #include <dt-bindings/interrupt-controller/irq.h>
0047
0048 / {
0049 #address-cells = <1>;
0050 #size-cells = <1>;
0051
0052 clocks {
0053 clk_hse: clk-hse {
0054 #clock-cells = <0>;
0055 compatible = "fixed-clock";
0056 clock-frequency = <0>;
0057 };
0058
0059 clk_lse: clk-lse {
0060 #clock-cells = <0>;
0061 compatible = "fixed-clock";
0062 clock-frequency = <32768>;
0063 };
0064
0065 clk_i2s: i2s_ckin {
0066 #clock-cells = <0>;
0067 compatible = "fixed-clock";
0068 clock-frequency = <0>;
0069 };
0070 };
0071
0072 soc {
0073 timer5: timer@40000c00 {
0074 compatible = "st,stm32-timer";
0075 reg = <0x40000c00 0x400>;
0076 interrupts = <50>;
0077 clocks = <&rcc TIM5_CK>;
0078 };
0079
0080 lptimer1: timer@40002400 {
0081 #address-cells = <1>;
0082 #size-cells = <0>;
0083 compatible = "st,stm32-lptimer";
0084 reg = <0x40002400 0x400>;
0085 clocks = <&rcc LPTIM1_CK>;
0086 clock-names = "mux";
0087 status = "disabled";
0088
0089 pwm {
0090 compatible = "st,stm32-pwm-lp";
0091 #pwm-cells = <3>;
0092 status = "disabled";
0093 };
0094
0095 trigger@0 {
0096 compatible = "st,stm32-lptimer-trigger";
0097 reg = <0>;
0098 status = "disabled";
0099 };
0100
0101 counter {
0102 compatible = "st,stm32-lptimer-counter";
0103 status = "disabled";
0104 };
0105 };
0106
0107 spi2: spi@40003800 {
0108 #address-cells = <1>;
0109 #size-cells = <0>;
0110 compatible = "st,stm32h7-spi";
0111 reg = <0x40003800 0x400>;
0112 interrupts = <36>;
0113 resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
0114 clocks = <&rcc SPI2_CK>;
0115 status = "disabled";
0116
0117 };
0118
0119 spi3: spi@40003c00 {
0120 #address-cells = <1>;
0121 #size-cells = <0>;
0122 compatible = "st,stm32h7-spi";
0123 reg = <0x40003c00 0x400>;
0124 interrupts = <51>;
0125 resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
0126 clocks = <&rcc SPI3_CK>;
0127 status = "disabled";
0128 };
0129
0130 usart2: serial@40004400 {
0131 compatible = "st,stm32h7-uart";
0132 reg = <0x40004400 0x400>;
0133 interrupts = <38>;
0134 status = "disabled";
0135 clocks = <&rcc USART2_CK>;
0136 };
0137
0138 usart3: serial@40004800 {
0139 compatible = "st,stm32h7-uart";
0140 reg = <0x40004800 0x400>;
0141 interrupts = <39>;
0142 status = "disabled";
0143 clocks = <&rcc USART3_CK>;
0144 };
0145
0146 uart4: serial@40004c00 {
0147 compatible = "st,stm32h7-uart";
0148 reg = <0x40004c00 0x400>;
0149 interrupts = <52>;
0150 status = "disabled";
0151 clocks = <&rcc UART4_CK>;
0152 };
0153
0154 i2c1: i2c@40005400 {
0155 compatible = "st,stm32f7-i2c";
0156 #address-cells = <1>;
0157 #size-cells = <0>;
0158 reg = <0x40005400 0x400>;
0159 interrupts = <31>,
0160 <32>;
0161 resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
0162 clocks = <&rcc I2C1_CK>;
0163 status = "disabled";
0164 };
0165
0166 i2c2: i2c@40005800 {
0167 compatible = "st,stm32f7-i2c";
0168 #address-cells = <1>;
0169 #size-cells = <0>;
0170 reg = <0x40005800 0x400>;
0171 interrupts = <33>,
0172 <34>;
0173 resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
0174 clocks = <&rcc I2C2_CK>;
0175 status = "disabled";
0176 };
0177
0178 i2c3: i2c@40005c00 {
0179 compatible = "st,stm32f7-i2c";
0180 #address-cells = <1>;
0181 #size-cells = <0>;
0182 reg = <0x40005C00 0x400>;
0183 interrupts = <72>,
0184 <73>;
0185 resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
0186 clocks = <&rcc I2C3_CK>;
0187 status = "disabled";
0188 };
0189
0190 dac: dac@40007400 {
0191 compatible = "st,stm32h7-dac-core";
0192 reg = <0x40007400 0x400>;
0193 clocks = <&rcc DAC12_CK>;
0194 clock-names = "pclk";
0195 #address-cells = <1>;
0196 #size-cells = <0>;
0197 status = "disabled";
0198
0199 dac1: dac@1 {
0200 compatible = "st,stm32-dac";
0201 #io-channel-cells = <1>;
0202 reg = <1>;
0203 status = "disabled";
0204 };
0205
0206 dac2: dac@2 {
0207 compatible = "st,stm32-dac";
0208 #io-channel-cells = <1>;
0209 reg = <2>;
0210 status = "disabled";
0211 };
0212 };
0213
0214 usart1: serial@40011000 {
0215 compatible = "st,stm32h7-uart";
0216 reg = <0x40011000 0x400>;
0217 interrupts = <37>;
0218 status = "disabled";
0219 clocks = <&rcc USART1_CK>;
0220 };
0221
0222 spi1: spi@40013000 {
0223 #address-cells = <1>;
0224 #size-cells = <0>;
0225 compatible = "st,stm32h7-spi";
0226 reg = <0x40013000 0x400>;
0227 interrupts = <35>;
0228 resets = <&rcc STM32H7_APB2_RESET(SPI1)>;
0229 clocks = <&rcc SPI1_CK>;
0230 status = "disabled";
0231 };
0232
0233 spi4: spi@40013400 {
0234 #address-cells = <1>;
0235 #size-cells = <0>;
0236 compatible = "st,stm32h7-spi";
0237 reg = <0x40013400 0x400>;
0238 interrupts = <84>;
0239 resets = <&rcc STM32H7_APB2_RESET(SPI4)>;
0240 clocks = <&rcc SPI4_CK>;
0241 status = "disabled";
0242 };
0243
0244 spi5: spi@40015000 {
0245 #address-cells = <1>;
0246 #size-cells = <0>;
0247 compatible = "st,stm32h7-spi";
0248 reg = <0x40015000 0x400>;
0249 interrupts = <85>;
0250 resets = <&rcc STM32H7_APB2_RESET(SPI5)>;
0251 clocks = <&rcc SPI5_CK>;
0252 status = "disabled";
0253 };
0254
0255 dma1: dma-controller@40020000 {
0256 compatible = "st,stm32-dma";
0257 reg = <0x40020000 0x400>;
0258 interrupts = <11>,
0259 <12>,
0260 <13>,
0261 <14>,
0262 <15>,
0263 <16>,
0264 <17>,
0265 <47>;
0266 clocks = <&rcc DMA1_CK>;
0267 #dma-cells = <4>;
0268 st,mem2mem;
0269 dma-requests = <8>;
0270 status = "disabled";
0271 };
0272
0273 dma2: dma-controller@40020400 {
0274 compatible = "st,stm32-dma";
0275 reg = <0x40020400 0x400>;
0276 interrupts = <56>,
0277 <57>,
0278 <58>,
0279 <59>,
0280 <60>,
0281 <68>,
0282 <69>,
0283 <70>;
0284 clocks = <&rcc DMA2_CK>;
0285 #dma-cells = <4>;
0286 st,mem2mem;
0287 dma-requests = <8>;
0288 status = "disabled";
0289 };
0290
0291 dmamux1: dma-router@40020800 {
0292 compatible = "st,stm32h7-dmamux";
0293 reg = <0x40020800 0x40>;
0294 #dma-cells = <3>;
0295 dma-channels = <16>;
0296 dma-requests = <128>;
0297 dma-masters = <&dma1 &dma2>;
0298 clocks = <&rcc DMA1_CK>;
0299 };
0300
0301 adc_12: adc@40022000 {
0302 compatible = "st,stm32h7-adc-core";
0303 reg = <0x40022000 0x400>;
0304 interrupts = <18>;
0305 clocks = <&rcc ADC12_CK>;
0306 clock-names = "bus";
0307 interrupt-controller;
0308 #interrupt-cells = <1>;
0309 #address-cells = <1>;
0310 #size-cells = <0>;
0311 status = "disabled";
0312
0313 adc1: adc@0 {
0314 compatible = "st,stm32h7-adc";
0315 #io-channel-cells = <1>;
0316 reg = <0x0>;
0317 interrupt-parent = <&adc_12>;
0318 interrupts = <0>;
0319 status = "disabled";
0320 };
0321
0322 adc2: adc@100 {
0323 compatible = "st,stm32h7-adc";
0324 #io-channel-cells = <1>;
0325 reg = <0x100>;
0326 interrupt-parent = <&adc_12>;
0327 interrupts = <1>;
0328 status = "disabled";
0329 };
0330 };
0331
0332 usbotg_hs: usb@40040000 {
0333 compatible = "st,stm32f7-hsotg";
0334 reg = <0x40040000 0x40000>;
0335 interrupts = <77>;
0336 clocks = <&rcc USB1OTG_CK>;
0337 clock-names = "otg";
0338 g-rx-fifo-size = <256>;
0339 g-np-tx-fifo-size = <32>;
0340 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
0341 status = "disabled";
0342 };
0343
0344 usbotg_fs: usb@40080000 {
0345 compatible = "st,stm32f4x9-fsotg";
0346 reg = <0x40080000 0x40000>;
0347 interrupts = <101>;
0348 clocks = <&rcc USB2OTG_CK>;
0349 clock-names = "otg";
0350 status = "disabled";
0351 };
0352
0353 ltdc: display-controller@50001000 {
0354 compatible = "st,stm32-ltdc";
0355 reg = <0x50001000 0x200>;
0356 interrupts = <88>, <89>;
0357 resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
0358 clocks = <&rcc LTDC_CK>;
0359 clock-names = "lcd";
0360 status = "disabled";
0361 };
0362
0363 mdma1: dma-controller@52000000 {
0364 compatible = "st,stm32h7-mdma";
0365 reg = <0x52000000 0x1000>;
0366 interrupts = <122>;
0367 clocks = <&rcc MDMA_CK>;
0368 #dma-cells = <5>;
0369 dma-channels = <16>;
0370 dma-requests = <32>;
0371 };
0372
0373 sdmmc1: mmc@52007000 {
0374 compatible = "arm,pl18x", "arm,primecell";
0375 arm,primecell-periphid = <0x10153180>;
0376 reg = <0x52007000 0x1000>;
0377 interrupts = <49>;
0378 interrupt-names = "cmd_irq";
0379 clocks = <&rcc SDMMC1_CK>;
0380 clock-names = "apb_pclk";
0381 resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
0382 cap-sd-highspeed;
0383 cap-mmc-highspeed;
0384 max-frequency = <120000000>;
0385 };
0386
0387 sdmmc2: mmc@48022400 {
0388 compatible = "arm,pl18x", "arm,primecell";
0389 arm,primecell-periphid = <0x10153180>;
0390 reg = <0x48022400 0x400>;
0391 interrupts = <124>;
0392 interrupt-names = "cmd_irq";
0393 clocks = <&rcc SDMMC2_CK>;
0394 clock-names = "apb_pclk";
0395 resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
0396 cap-sd-highspeed;
0397 cap-mmc-highspeed;
0398 max-frequency = <120000000>;
0399 status = "disabled";
0400 };
0401
0402 exti: interrupt-controller@58000000 {
0403 compatible = "st,stm32h7-exti";
0404 interrupt-controller;
0405 #interrupt-cells = <2>;
0406 reg = <0x58000000 0x400>;
0407 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
0408 };
0409
0410 syscfg: syscon@58000400 {
0411 compatible = "st,stm32-syscfg", "syscon";
0412 reg = <0x58000400 0x400>;
0413 };
0414
0415 spi6: spi@58001400 {
0416 #address-cells = <1>;
0417 #size-cells = <0>;
0418 compatible = "st,stm32h7-spi";
0419 reg = <0x58001400 0x400>;
0420 interrupts = <86>;
0421 resets = <&rcc STM32H7_APB4_RESET(SPI6)>;
0422 clocks = <&rcc SPI6_CK>;
0423 status = "disabled";
0424 };
0425
0426 i2c4: i2c@58001c00 {
0427 compatible = "st,stm32f7-i2c";
0428 #address-cells = <1>;
0429 #size-cells = <0>;
0430 reg = <0x58001C00 0x400>;
0431 interrupts = <95>,
0432 <96>;
0433 resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
0434 clocks = <&rcc I2C4_CK>;
0435 status = "disabled";
0436 };
0437
0438 lptimer2: timer@58002400 {
0439 #address-cells = <1>;
0440 #size-cells = <0>;
0441 compatible = "st,stm32-lptimer";
0442 reg = <0x58002400 0x400>;
0443 clocks = <&rcc LPTIM2_CK>;
0444 clock-names = "mux";
0445 status = "disabled";
0446
0447 pwm {
0448 compatible = "st,stm32-pwm-lp";
0449 #pwm-cells = <3>;
0450 status = "disabled";
0451 };
0452
0453 trigger@1 {
0454 compatible = "st,stm32-lptimer-trigger";
0455 reg = <1>;
0456 status = "disabled";
0457 };
0458
0459 counter {
0460 compatible = "st,stm32-lptimer-counter";
0461 status = "disabled";
0462 };
0463 };
0464
0465 lptimer3: timer@58002800 {
0466 #address-cells = <1>;
0467 #size-cells = <0>;
0468 compatible = "st,stm32-lptimer";
0469 reg = <0x58002800 0x400>;
0470 clocks = <&rcc LPTIM3_CK>;
0471 clock-names = "mux";
0472 status = "disabled";
0473
0474 pwm {
0475 compatible = "st,stm32-pwm-lp";
0476 #pwm-cells = <3>;
0477 status = "disabled";
0478 };
0479
0480 trigger@2 {
0481 compatible = "st,stm32-lptimer-trigger";
0482 reg = <2>;
0483 status = "disabled";
0484 };
0485 };
0486
0487 lptimer4: timer@58002c00 {
0488 compatible = "st,stm32-lptimer";
0489 reg = <0x58002c00 0x400>;
0490 clocks = <&rcc LPTIM4_CK>;
0491 clock-names = "mux";
0492 status = "disabled";
0493
0494 pwm {
0495 compatible = "st,stm32-pwm-lp";
0496 #pwm-cells = <3>;
0497 status = "disabled";
0498 };
0499 };
0500
0501 lptimer5: timer@58003000 {
0502 compatible = "st,stm32-lptimer";
0503 reg = <0x58003000 0x400>;
0504 clocks = <&rcc LPTIM5_CK>;
0505 clock-names = "mux";
0506 status = "disabled";
0507
0508 pwm {
0509 compatible = "st,stm32-pwm-lp";
0510 #pwm-cells = <3>;
0511 status = "disabled";
0512 };
0513 };
0514
0515 vrefbuf: regulator@58003c00 {
0516 compatible = "st,stm32-vrefbuf";
0517 reg = <0x58003C00 0x8>;
0518 clocks = <&rcc VREF_CK>;
0519 regulator-min-microvolt = <1500000>;
0520 regulator-max-microvolt = <2500000>;
0521 status = "disabled";
0522 };
0523
0524 rtc: rtc@58004000 {
0525 compatible = "st,stm32h7-rtc";
0526 reg = <0x58004000 0x400>;
0527 clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
0528 clock-names = "pclk", "rtc_ck";
0529 assigned-clocks = <&rcc RTC_CK>;
0530 assigned-clock-parents = <&rcc LSE_CK>;
0531 interrupt-parent = <&exti>;
0532 interrupts = <17 IRQ_TYPE_EDGE_RISING>;
0533 st,syscfg = <&pwrcfg 0x00 0x100>;
0534 status = "disabled";
0535 };
0536
0537 rcc: reset-clock-controller@58024400 {
0538 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
0539 reg = <0x58024400 0x400>;
0540 #clock-cells = <1>;
0541 #reset-cells = <1>;
0542 clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
0543 st,syscfg = <&pwrcfg>;
0544 };
0545
0546 pwrcfg: power-config@58024800 {
0547 compatible = "st,stm32-power-config", "syscon";
0548 reg = <0x58024800 0x400>;
0549 };
0550
0551 adc_3: adc@58026000 {
0552 compatible = "st,stm32h7-adc-core";
0553 reg = <0x58026000 0x400>;
0554 interrupts = <127>;
0555 clocks = <&rcc ADC3_CK>;
0556 clock-names = "bus";
0557 interrupt-controller;
0558 #interrupt-cells = <1>;
0559 #address-cells = <1>;
0560 #size-cells = <0>;
0561 status = "disabled";
0562
0563 adc3: adc@0 {
0564 compatible = "st,stm32h7-adc";
0565 #io-channel-cells = <1>;
0566 reg = <0x0>;
0567 interrupt-parent = <&adc_3>;
0568 interrupts = <0>;
0569 status = "disabled";
0570 };
0571 };
0572
0573 mac: ethernet@40028000 {
0574 compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
0575 reg = <0x40028000 0x8000>;
0576 reg-names = "stmmaceth";
0577 interrupts = <61>;
0578 interrupt-names = "macirq";
0579 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
0580 clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>;
0581 st,syscon = <&syscfg 0x4>;
0582 snps,pbl = <8>;
0583 status = "disabled";
0584 };
0585
0586 pinctrl: pinctrl@58020000 {
0587 #address-cells = <1>;
0588 #size-cells = <1>;
0589 compatible = "st,stm32h743-pinctrl";
0590 ranges = <0 0x58020000 0x3000>;
0591 interrupt-parent = <&exti>;
0592 st,syscfg = <&syscfg 0x8>;
0593 pins-are-numbered;
0594
0595 gpioa: gpio@58020000 {
0596 gpio-controller;
0597 #gpio-cells = <2>;
0598 reg = <0x0 0x400>;
0599 clocks = <&rcc GPIOA_CK>;
0600 st,bank-name = "GPIOA";
0601 interrupt-controller;
0602 #interrupt-cells = <2>;
0603 ngpios = <16>;
0604 gpio-ranges = <&pinctrl 0 0 16>;
0605 };
0606
0607 gpiob: gpio@58020400 {
0608 gpio-controller;
0609 #gpio-cells = <2>;
0610 reg = <0x400 0x400>;
0611 clocks = <&rcc GPIOB_CK>;
0612 st,bank-name = "GPIOB";
0613 interrupt-controller;
0614 #interrupt-cells = <2>;
0615 ngpios = <16>;
0616 gpio-ranges = <&pinctrl 0 16 16>;
0617 };
0618
0619 gpioc: gpio@58020800 {
0620 gpio-controller;
0621 #gpio-cells = <2>;
0622 reg = <0x800 0x400>;
0623 clocks = <&rcc GPIOC_CK>;
0624 st,bank-name = "GPIOC";
0625 interrupt-controller;
0626 #interrupt-cells = <2>;
0627 ngpios = <16>;
0628 gpio-ranges = <&pinctrl 0 32 16>;
0629 };
0630
0631 gpiod: gpio@58020c00 {
0632 gpio-controller;
0633 #gpio-cells = <2>;
0634 reg = <0xc00 0x400>;
0635 clocks = <&rcc GPIOD_CK>;
0636 st,bank-name = "GPIOD";
0637 interrupt-controller;
0638 #interrupt-cells = <2>;
0639 ngpios = <16>;
0640 gpio-ranges = <&pinctrl 0 48 16>;
0641 };
0642
0643 gpioe: gpio@58021000 {
0644 gpio-controller;
0645 #gpio-cells = <2>;
0646 reg = <0x1000 0x400>;
0647 clocks = <&rcc GPIOE_CK>;
0648 st,bank-name = "GPIOE";
0649 interrupt-controller;
0650 #interrupt-cells = <2>;
0651 ngpios = <16>;
0652 gpio-ranges = <&pinctrl 0 64 16>;
0653 };
0654
0655 gpiof: gpio@58021400 {
0656 gpio-controller;
0657 #gpio-cells = <2>;
0658 reg = <0x1400 0x400>;
0659 clocks = <&rcc GPIOF_CK>;
0660 st,bank-name = "GPIOF";
0661 interrupt-controller;
0662 #interrupt-cells = <2>;
0663 ngpios = <16>;
0664 gpio-ranges = <&pinctrl 0 80 16>;
0665 };
0666
0667 gpiog: gpio@58021800 {
0668 gpio-controller;
0669 #gpio-cells = <2>;
0670 reg = <0x1800 0x400>;
0671 clocks = <&rcc GPIOG_CK>;
0672 st,bank-name = "GPIOG";
0673 interrupt-controller;
0674 #interrupt-cells = <2>;
0675 ngpios = <16>;
0676 gpio-ranges = <&pinctrl 0 96 16>;
0677 };
0678
0679 gpioh: gpio@58021c00 {
0680 gpio-controller;
0681 #gpio-cells = <2>;
0682 reg = <0x1c00 0x400>;
0683 clocks = <&rcc GPIOH_CK>;
0684 st,bank-name = "GPIOH";
0685 interrupt-controller;
0686 #interrupt-cells = <2>;
0687 ngpios = <16>;
0688 gpio-ranges = <&pinctrl 0 112 16>;
0689 };
0690
0691 gpioi: gpio@58022000 {
0692 gpio-controller;
0693 #gpio-cells = <2>;
0694 reg = <0x2000 0x400>;
0695 clocks = <&rcc GPIOI_CK>;
0696 st,bank-name = "GPIOI";
0697 interrupt-controller;
0698 #interrupt-cells = <2>;
0699 ngpios = <16>;
0700 gpio-ranges = <&pinctrl 0 128 16>;
0701 };
0702
0703 gpioj: gpio@58022400 {
0704 gpio-controller;
0705 #gpio-cells = <2>;
0706 reg = <0x2400 0x400>;
0707 clocks = <&rcc GPIOJ_CK>;
0708 st,bank-name = "GPIOJ";
0709 interrupt-controller;
0710 #interrupt-cells = <2>;
0711 ngpios = <16>;
0712 gpio-ranges = <&pinctrl 0 144 16>;
0713 };
0714
0715 gpiok: gpio@58022800 {
0716 gpio-controller;
0717 #gpio-cells = <2>;
0718 reg = <0x2800 0x400>;
0719 clocks = <&rcc GPIOK_CK>;
0720 st,bank-name = "GPIOK";
0721 interrupt-controller;
0722 #interrupt-cells = <2>;
0723 ngpios = <8>;
0724 gpio-ranges = <&pinctrl 0 160 8>;
0725 };
0726 };
0727 };
0728 };
0729
0730 &systick {
0731 clock-frequency = <250000000>;
0732 status = "okay";
0733 };
