0001 /*
0002 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
0003 *
0004 * This file is dual-licensed: you can use it either under the terms
0005 * of the GPL or the X11 license, at your option. Note that this dual
0006 * licensing only applies to this file, and not this project as a
0007 * whole.
0008 *
0009 * a) This file is free software; you can redistribute it and/or
0010 * modify it under the terms of the GNU General Public License as
0011 * published by the Free Software Foundation; either version 2 of the
0012 * License, or (at your option) any later version.
0013 *
0014 * This file is distributed in the hope that it will be useful,
0015 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0017 * GNU General Public License for more details.
0018 *
0019 * Or, alternatively,
0020 *
0021 * b) Permission is hereby granted, free of charge, to any person
0022 * obtaining a copy of this software and associated documentation
0023 * files (the "Software"), to deal in the Software without
0024 * restriction, including without limitation the rights to use,
0025 * copy, modify, merge, publish, distribute, sublicense, and/or
0026 * sell copies of the Software, and to permit persons to whom the
0027 * Software is furnished to do so, subject to the following
0028 * conditions:
0029 *
0030 * The above copyright notice and this permission notice shall be
0031 * included in all copies or substantial portions of the Software.
0032 *
0033 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0034 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0035 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0036 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0037 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0038 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0039 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0040 * OTHER DEALINGS IN THE SOFTWARE.
0041 */
0042
0043 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
0044
0045 &pinctrl {
0046
0047 i2c1_pins_a: i2c1-0 {
0048 pins {
0049 pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
0050 <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
0051 bias-disable;
0052 drive-open-drain;
0053 slew-rate = <0>;
0054 };
0055 };
0056
0057 ethernet_rmii: rmii-0 {
0058 pins {
0059 pinmux = <STM32_PINMUX('G', 11, AF11)>,
0060 <STM32_PINMUX('G', 13, AF11)>,
0061 <STM32_PINMUX('G', 12, AF11)>,
0062 <STM32_PINMUX('C', 4, AF11)>,
0063 <STM32_PINMUX('C', 5, AF11)>,
0064 <STM32_PINMUX('A', 7, AF11)>,
0065 <STM32_PINMUX('C', 1, AF11)>,
0066 <STM32_PINMUX('A', 2, AF11)>,
0067 <STM32_PINMUX('A', 1, AF11)>;
0068 slew-rate = <2>;
0069 };
0070 };
0071
0072 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
0073 pins {
0074 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
0075 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
0076 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
0077 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
0078 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
0079 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
0080 slew-rate = <3>;
0081 drive-push-pull;
0082 bias-disable;
0083 };
0084 };
0085
0086 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
0087 pins1 {
0088 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
0089 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
0090 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
0091 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
0092 <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
0093 slew-rate = <3>;
0094 drive-push-pull;
0095 bias-disable;
0096 };
0097 pins2{
0098 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
0099 slew-rate = <3>;
0100 drive-open-drain;
0101 bias-disable;
0102 };
0103 };
0104
0105 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
0106 pins {
0107 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
0108 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
0109 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
0110 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
0111 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
0112 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
0113 };
0114 };
0115
0116 sdmmc1_dir_pins_a: sdmmc1-dir-0 {
0117 pins1 {
0118 pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
0119 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
0120 <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
0121 slew-rate = <3>;
0122 drive-push-pull;
0123 bias-pull-up;
0124 };
0125 pins2{
0126 pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
0127 bias-pull-up;
0128 };
0129 };
0130
0131 sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
0132 pins {
0133 pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
0134 <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
0135 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
0136 <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
0137 };
0138 };
0139
0140 sdmmc2_b4_pins_a: sdmmc2-b4-0 {
0141 pins {
0142 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC1_D0 */
0143 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
0144 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
0145 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
0146 <STM32_PINMUX('D', 6, AF11)>, /* SDMMC1_CK */
0147 <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
0148 slew-rate = <3>;
0149 drive-push-pull;
0150 bias-disable;
0151 };
0152 };
0153
0154 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
0155 pins1 {
0156 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
0157 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
0158 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
0159 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
0160 <STM32_PINMUX('D', 6, AF11)>; /* SDMMC1_CK */
0161 slew-rate = <3>;
0162 drive-push-pull;
0163 bias-disable;
0164 };
0165 pins2{
0166 pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
0167 slew-rate = <3>;
0168 drive-open-drain;
0169 bias-disable;
0170 };
0171 };
0172
0173 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
0174 pins {
0175 pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC1_D0 */
0176 <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC1_D1 */
0177 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC1_D2 */
0178 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC1_D3 */
0179 <STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC1_CK */
0180 <STM32_PINMUX('D', 7, ANALOG)>; /* SDMMC1_CMD */
0181 };
0182 };
0183
0184 spi1_pins: spi1-0 {
0185 pins1 {
0186 pinmux = <STM32_PINMUX('A', 5, AF5)>,
0187 /* SPI1_CLK */
0188 <STM32_PINMUX('B', 5, AF5)>;
0189 /* SPI1_MOSI */
0190 bias-disable;
0191 drive-push-pull;
0192 slew-rate = <2>;
0193 };
0194 pins2 {
0195 pinmux = <STM32_PINMUX('G', 9, AF5)>;
0196 /* SPI1_MISO */
0197 bias-disable;
0198 };
0199 };
0200
0201 uart4_pins: uart4-0 {
0202 pins1 {
0203 pinmux = <STM32_PINMUX('A', 0, AF8)>; /* UART4_TX */
0204 bias-disable;
0205 drive-push-pull;
0206 slew-rate = <0>;
0207 };
0208 pins2 {
0209 pinmux = <STM32_PINMUX('I', 9, AF8)>; /* UART4_RX */
0210 bias-disable;
0211 };
0212 };
0213
0214 usart1_pins: usart1-0 {
0215 pins1 {
0216 pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
0217 bias-disable;
0218 drive-push-pull;
0219 slew-rate = <0>;
0220 };
0221 pins2 {
0222 pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
0223 bias-disable;
0224 };
0225 };
0226
0227 usart2_pins: usart2-0 {
0228 pins1 {
0229 pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
0230 bias-disable;
0231 drive-push-pull;
0232 slew-rate = <0>;
0233 };
0234 pins2 {
0235 pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
0236 bias-disable;
0237 };
0238 };
0239
0240 usart3_pins: usart3-0 {
0241 pins1 {
0242 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
0243 <STM32_PINMUX('D', 12, AF7)>; /* USART3_RTS_DE */
0244 bias-disable;
0245 drive-push-pull;
0246 slew-rate = <0>;
0247 };
0248 pins2 {
0249 pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */
0250 <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
0251 bias-disable;
0252 };
0253 };
0254
0255 usbotg_hs_pins_a: usbotg-hs-0 {
0256 pins {
0257 pinmux = <STM32_PINMUX('H', 4, AF10)>, /* ULPI_NXT */
0258 <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
0259 <STM32_PINMUX('C', 0, AF10)>, /* ULPI_STP> */
0260 <STM32_PINMUX('A', 5, AF10)>, /* ULPI_CK> */
0261 <STM32_PINMUX('A', 3, AF10)>, /* ULPI_D0> */
0262 <STM32_PINMUX('B', 0, AF10)>, /* ULPI_D1> */
0263 <STM32_PINMUX('B', 1, AF10)>, /* ULPI_D2> */
0264 <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
0265 <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
0266 <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
0267 <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
0268 <STM32_PINMUX('B', 5, AF10)>; /* ULPI_D7> */
0269 bias-disable;
0270 drive-push-pull;
0271 slew-rate = <2>;
0272 };
0273 };
0274 };
0275
