0001 /*
0002 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
0003 *
0004 * This file is dual-licensed: you can use it either under the terms
0005 * of the GPL or the X11 license, at your option. Note that this dual
0006 * licensing only applies to this file, and not this project as a
0007 * whole.
0008 *
0009 * a) This file is free software; you can redistribute it and/or
0010 * modify it under the terms of the GNU General Public License as
0011 * published by the Free Software Foundation; either version 2 of the
0012 * License, or (at your option) any later version.
0013 *
0014 * This file is distributed in the hope that it will be useful,
0015 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0017 * GNU General Public License for more details.
0018 *
0019 * Or, alternatively,
0020 *
0021 * b) Permission is hereby granted, free of charge, to any person
0022 * obtaining a copy of this software and associated documentation
0023 * files (the "Software"), to deal in the Software without
0024 * restriction, including without limitation the rights to use,
0025 * copy, modify, merge, publish, distribute, sublicense, and/or
0026 * sell copies of the Software, and to permit persons to whom the
0027 * Software is furnished to do so, subject to the following
0028 * conditions:
0029 *
0030 * The above copyright notice and this permission notice shall be
0031 * included in all copies or substantial portions of the Software.
0032 *
0033 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0034 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0035 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0036 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0037 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0038 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0039 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0040 * OTHER DEALINGS IN THE SOFTWARE.
0041 */
0042
0043 #include "armv7-m.dtsi"
0044 #include <dt-bindings/clock/stm32fx-clock.h>
0045 #include <dt-bindings/mfd/stm32f7-rcc.h>
0046
0047 / {
0048 #address-cells = <1>;
0049 #size-cells = <1>;
0050
0051 clocks {
0052 clk_hse: clk-hse {
0053 #clock-cells = <0>;
0054 compatible = "fixed-clock";
0055 clock-frequency = <0>;
0056 };
0057
0058 clk-lse {
0059 #clock-cells = <0>;
0060 compatible = "fixed-clock";
0061 clock-frequency = <32768>;
0062 };
0063
0064 clk-lsi {
0065 #clock-cells = <0>;
0066 compatible = "fixed-clock";
0067 clock-frequency = <32000>;
0068 };
0069
0070 clk_i2s_ckin: clk-i2s-ckin {
0071 #clock-cells = <0>;
0072 compatible = "fixed-clock";
0073 clock-frequency = <48000000>;
0074 };
0075 };
0076
0077 soc {
0078 timers2: timers@40000000 {
0079 #address-cells = <1>;
0080 #size-cells = <0>;
0081 compatible = "st,stm32-timers";
0082 reg = <0x40000000 0x400>;
0083 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
0084 clock-names = "int";
0085 status = "disabled";
0086
0087 pwm {
0088 compatible = "st,stm32-pwm";
0089 #pwm-cells = <3>;
0090 status = "disabled";
0091 };
0092
0093 timer@1 {
0094 compatible = "st,stm32-timer-trigger";
0095 reg = <1>;
0096 status = "disabled";
0097 };
0098 };
0099
0100 timers3: timers@40000400 {
0101 #address-cells = <1>;
0102 #size-cells = <0>;
0103 compatible = "st,stm32-timers";
0104 reg = <0x40000400 0x400>;
0105 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
0106 clock-names = "int";
0107 status = "disabled";
0108
0109 pwm {
0110 compatible = "st,stm32-pwm";
0111 #pwm-cells = <3>;
0112 status = "disabled";
0113 };
0114
0115 timer@2 {
0116 compatible = "st,stm32-timer-trigger";
0117 reg = <2>;
0118 status = "disabled";
0119 };
0120 };
0121
0122 timers4: timers@40000800 {
0123 #address-cells = <1>;
0124 #size-cells = <0>;
0125 compatible = "st,stm32-timers";
0126 reg = <0x40000800 0x400>;
0127 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
0128 clock-names = "int";
0129 status = "disabled";
0130
0131 pwm {
0132 compatible = "st,stm32-pwm";
0133 #pwm-cells = <3>;
0134 status = "disabled";
0135 };
0136
0137 timer@3 {
0138 compatible = "st,stm32-timer-trigger";
0139 reg = <3>;
0140 status = "disabled";
0141 };
0142 };
0143
0144 timers5: timers@40000c00 {
0145 #address-cells = <1>;
0146 #size-cells = <0>;
0147 compatible = "st,stm32-timers";
0148 reg = <0x40000C00 0x400>;
0149 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
0150 clock-names = "int";
0151 status = "disabled";
0152
0153 pwm {
0154 compatible = "st,stm32-pwm";
0155 #pwm-cells = <3>;
0156 status = "disabled";
0157 };
0158
0159 timer@4 {
0160 compatible = "st,stm32-timer-trigger";
0161 reg = <4>;
0162 status = "disabled";
0163 };
0164 };
0165
0166 timers6: timers@40001000 {
0167 #address-cells = <1>;
0168 #size-cells = <0>;
0169 compatible = "st,stm32-timers";
0170 reg = <0x40001000 0x400>;
0171 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
0172 clock-names = "int";
0173 status = "disabled";
0174
0175 timer@5 {
0176 compatible = "st,stm32-timer-trigger";
0177 reg = <5>;
0178 status = "disabled";
0179 };
0180 };
0181
0182 timers7: timers@40001400 {
0183 #address-cells = <1>;
0184 #size-cells = <0>;
0185 compatible = "st,stm32-timers";
0186 reg = <0x40001400 0x400>;
0187 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
0188 clock-names = "int";
0189 status = "disabled";
0190
0191 timer@6 {
0192 compatible = "st,stm32-timer-trigger";
0193 reg = <6>;
0194 status = "disabled";
0195 };
0196 };
0197
0198 timers12: timers@40001800 {
0199 #address-cells = <1>;
0200 #size-cells = <0>;
0201 compatible = "st,stm32-timers";
0202 reg = <0x40001800 0x400>;
0203 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
0204 clock-names = "int";
0205 status = "disabled";
0206
0207 pwm {
0208 compatible = "st,stm32-pwm";
0209 #pwm-cells = <3>;
0210 status = "disabled";
0211 };
0212
0213 timer@11 {
0214 compatible = "st,stm32-timer-trigger";
0215 reg = <11>;
0216 status = "disabled";
0217 };
0218 };
0219
0220 timers13: timers@40001c00 {
0221 compatible = "st,stm32-timers";
0222 reg = <0x40001C00 0x400>;
0223 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
0224 clock-names = "int";
0225 status = "disabled";
0226
0227 pwm {
0228 compatible = "st,stm32-pwm";
0229 #pwm-cells = <3>;
0230 status = "disabled";
0231 };
0232 };
0233
0234 timers14: timers@40002000 {
0235 compatible = "st,stm32-timers";
0236 reg = <0x40002000 0x400>;
0237 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
0238 clock-names = "int";
0239 status = "disabled";
0240
0241 pwm {
0242 compatible = "st,stm32-pwm";
0243 #pwm-cells = <3>;
0244 status = "disabled";
0245 };
0246 };
0247
0248 rtc: rtc@40002800 {
0249 compatible = "st,stm32-rtc";
0250 reg = <0x40002800 0x400>;
0251 clocks = <&rcc 1 CLK_RTC>;
0252 assigned-clocks = <&rcc 1 CLK_RTC>;
0253 assigned-clock-parents = <&rcc 1 CLK_LSE>;
0254 interrupt-parent = <&exti>;
0255 interrupts = <17 1>;
0256 st,syscfg = <&pwrcfg 0x00 0x100>;
0257 status = "disabled";
0258 };
0259
0260 usart2: serial@40004400 {
0261 compatible = "st,stm32f7-uart";
0262 reg = <0x40004400 0x400>;
0263 interrupts = <38>;
0264 clocks = <&rcc 1 CLK_USART2>;
0265 status = "disabled";
0266 };
0267
0268 usart3: serial@40004800 {
0269 compatible = "st,stm32f7-uart";
0270 reg = <0x40004800 0x400>;
0271 interrupts = <39>;
0272 clocks = <&rcc 1 CLK_USART3>;
0273 status = "disabled";
0274 };
0275
0276 usart4: serial@40004c00 {
0277 compatible = "st,stm32f7-uart";
0278 reg = <0x40004c00 0x400>;
0279 interrupts = <52>;
0280 clocks = <&rcc 1 CLK_UART4>;
0281 status = "disabled";
0282 };
0283
0284 usart5: serial@40005000 {
0285 compatible = "st,stm32f7-uart";
0286 reg = <0x40005000 0x400>;
0287 interrupts = <53>;
0288 clocks = <&rcc 1 CLK_UART5>;
0289 status = "disabled";
0290 };
0291
0292 i2c1: i2c@40005400 {
0293 compatible = "st,stm32f7-i2c";
0294 reg = <0x40005400 0x400>;
0295 interrupts = <31>,
0296 <32>;
0297 resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
0298 clocks = <&rcc 1 CLK_I2C1>;
0299 #address-cells = <1>;
0300 #size-cells = <0>;
0301 status = "disabled";
0302 };
0303
0304 i2c2: i2c@40005800 {
0305 compatible = "st,stm32f7-i2c";
0306 reg = <0x40005800 0x400>;
0307 interrupts = <33>,
0308 <34>;
0309 resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
0310 clocks = <&rcc 1 CLK_I2C2>;
0311 #address-cells = <1>;
0312 #size-cells = <0>;
0313 status = "disabled";
0314 };
0315
0316 i2c3: i2c@40005c00 {
0317 compatible = "st,stm32f7-i2c";
0318 reg = <0x40005c00 0x400>;
0319 interrupts = <72>,
0320 <73>;
0321 resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
0322 clocks = <&rcc 1 CLK_I2C3>;
0323 #address-cells = <1>;
0324 #size-cells = <0>;
0325 status = "disabled";
0326 };
0327
0328 i2c4: i2c@40006000 {
0329 compatible = "st,stm32f7-i2c";
0330 reg = <0x40006000 0x400>;
0331 interrupts = <95>,
0332 <96>;
0333 resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
0334 clocks = <&rcc 1 CLK_I2C4>;
0335 #address-cells = <1>;
0336 #size-cells = <0>;
0337 status = "disabled";
0338 };
0339
0340 cec: cec@40006c00 {
0341 compatible = "st,stm32-cec";
0342 reg = <0x40006C00 0x400>;
0343 interrupts = <94>;
0344 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
0345 clock-names = "cec", "hdmi-cec";
0346 status = "disabled";
0347 };
0348
0349 usart7: serial@40007800 {
0350 compatible = "st,stm32f7-uart";
0351 reg = <0x40007800 0x400>;
0352 interrupts = <82>;
0353 clocks = <&rcc 1 CLK_UART7>;
0354 status = "disabled";
0355 };
0356
0357 usart8: serial@40007c00 {
0358 compatible = "st,stm32f7-uart";
0359 reg = <0x40007c00 0x400>;
0360 interrupts = <83>;
0361 clocks = <&rcc 1 CLK_UART8>;
0362 status = "disabled";
0363 };
0364
0365 timers1: timers@40010000 {
0366 #address-cells = <1>;
0367 #size-cells = <0>;
0368 compatible = "st,stm32-timers";
0369 reg = <0x40010000 0x400>;
0370 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
0371 clock-names = "int";
0372 status = "disabled";
0373
0374 pwm {
0375 compatible = "st,stm32-pwm";
0376 #pwm-cells = <3>;
0377 status = "disabled";
0378 };
0379
0380 timer@0 {
0381 compatible = "st,stm32-timer-trigger";
0382 reg = <0>;
0383 status = "disabled";
0384 };
0385 };
0386
0387 timers8: timers@40010400 {
0388 #address-cells = <1>;
0389 #size-cells = <0>;
0390 compatible = "st,stm32-timers";
0391 reg = <0x40010400 0x400>;
0392 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
0393 clock-names = "int";
0394 status = "disabled";
0395
0396 pwm {
0397 compatible = "st,stm32-pwm";
0398 #pwm-cells = <3>;
0399 status = "disabled";
0400 };
0401
0402 timer@7 {
0403 compatible = "st,stm32-timer-trigger";
0404 reg = <7>;
0405 status = "disabled";
0406 };
0407 };
0408
0409 usart1: serial@40011000 {
0410 compatible = "st,stm32f7-uart";
0411 reg = <0x40011000 0x400>;
0412 interrupts = <37>;
0413 clocks = <&rcc 1 CLK_USART1>;
0414 status = "disabled";
0415 };
0416
0417 usart6: serial@40011400 {
0418 compatible = "st,stm32f7-uart";
0419 reg = <0x40011400 0x400>;
0420 interrupts = <71>;
0421 clocks = <&rcc 1 CLK_USART6>;
0422 status = "disabled";
0423 };
0424
0425 sdio2: mmc@40011c00 {
0426 compatible = "arm,pl180", "arm,primecell";
0427 arm,primecell-periphid = <0x00880180>;
0428 reg = <0x40011c00 0x400>;
0429 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
0430 clock-names = "apb_pclk";
0431 interrupts = <103>;
0432 max-frequency = <48000000>;
0433 status = "disabled";
0434 };
0435
0436 sdio1: mmc@40012c00 {
0437 compatible = "arm,pl180", "arm,primecell";
0438 arm,primecell-periphid = <0x00880180>;
0439 reg = <0x40012c00 0x400>;
0440 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
0441 clock-names = "apb_pclk";
0442 interrupts = <49>;
0443 max-frequency = <48000000>;
0444 status = "disabled";
0445 };
0446
0447 syscfg: syscon@40013800 {
0448 compatible = "st,stm32-syscfg", "syscon";
0449 reg = <0x40013800 0x400>;
0450 };
0451
0452 exti: interrupt-controller@40013c00 {
0453 compatible = "st,stm32-exti";
0454 interrupt-controller;
0455 #interrupt-cells = <2>;
0456 reg = <0x40013C00 0x400>;
0457 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
0458 };
0459
0460 timers9: timers@40014000 {
0461 #address-cells = <1>;
0462 #size-cells = <0>;
0463 compatible = "st,stm32-timers";
0464 reg = <0x40014000 0x400>;
0465 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
0466 clock-names = "int";
0467 status = "disabled";
0468
0469 pwm {
0470 compatible = "st,stm32-pwm";
0471 #pwm-cells = <3>;
0472 status = "disabled";
0473 };
0474
0475 timer@8 {
0476 compatible = "st,stm32-timer-trigger";
0477 reg = <8>;
0478 status = "disabled";
0479 };
0480 };
0481
0482 timers10: timers@40014400 {
0483 compatible = "st,stm32-timers";
0484 reg = <0x40014400 0x400>;
0485 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
0486 clock-names = "int";
0487 status = "disabled";
0488
0489 pwm {
0490 compatible = "st,stm32-pwm";
0491 #pwm-cells = <3>;
0492 status = "disabled";
0493 };
0494 };
0495
0496 timers11: timers@40014800 {
0497 compatible = "st,stm32-timers";
0498 reg = <0x40014800 0x400>;
0499 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
0500 clock-names = "int";
0501 status = "disabled";
0502
0503 pwm {
0504 compatible = "st,stm32-pwm";
0505 #pwm-cells = <3>;
0506 status = "disabled";
0507 };
0508 };
0509
0510 pwrcfg: power-config@40007000 {
0511 compatible = "st,stm32-power-config", "syscon";
0512 reg = <0x40007000 0x400>;
0513 };
0514
0515 crc: crc@40023000 {
0516 compatible = "st,stm32f7-crc";
0517 reg = <0x40023000 0x400>;
0518 clocks = <&rcc 0 12>;
0519 status = "disabled";
0520 };
0521
0522 rcc: rcc@40023800 {
0523 #reset-cells = <1>;
0524 #clock-cells = <2>;
0525 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
0526 reg = <0x40023800 0x400>;
0527 clocks = <&clk_hse>, <&clk_i2s_ckin>;
0528 st,syscfg = <&pwrcfg>;
0529 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
0530 assigned-clock-rates = <1000000>;
0531 };
0532
0533 dma1: dma-controller@40026000 {
0534 compatible = "st,stm32-dma";
0535 reg = <0x40026000 0x400>;
0536 interrupts = <11>,
0537 <12>,
0538 <13>,
0539 <14>,
0540 <15>,
0541 <16>,
0542 <17>,
0543 <47>;
0544 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
0545 #dma-cells = <4>;
0546 status = "disabled";
0547 };
0548
0549 dma2: dma-controller@40026400 {
0550 compatible = "st,stm32-dma";
0551 reg = <0x40026400 0x400>;
0552 interrupts = <56>,
0553 <57>,
0554 <58>,
0555 <59>,
0556 <60>,
0557 <68>,
0558 <69>,
0559 <70>;
0560 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
0561 #dma-cells = <4>;
0562 st,mem2mem;
0563 status = "disabled";
0564 };
0565
0566 usbotg_hs: usb@40040000 {
0567 compatible = "st,stm32f7-hsotg";
0568 reg = <0x40040000 0x40000>;
0569 interrupts = <77>;
0570 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
0571 clock-names = "otg";
0572 g-rx-fifo-size = <256>;
0573 g-np-tx-fifo-size = <32>;
0574 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
0575 status = "disabled";
0576 };
0577
0578 usbotg_fs: usb@50000000 {
0579 compatible = "st,stm32f4x9-fsotg";
0580 reg = <0x50000000 0x40000>;
0581 interrupts = <67>;
0582 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
0583 clock-names = "otg";
0584 status = "disabled";
0585 };
0586 };
0587 };
0588
0589 &systick {
0590 clocks = <&rcc 1 0>;
0591 status = "okay";
0592 };
