OSCL-LXR |
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0001 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
0002 /*
0003 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
0004 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
0005 */
0006
0007 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
0008 #include <dt-bindings/mfd/stm32f7-rcc.h>
0009
0010 / {
0011 soc {
0012 pinctrl: pinctrl@40020000 {
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015 ranges = <0 0x40020000 0x3000>;
0016 interrupt-parent = <&exti>;
0017 st,syscfg = <&syscfg 0x8>;
0018 pins-are-numbered;
0019
0020 gpioa: gpio@40020000 {
0021 gpio-controller;
0022 #gpio-cells = <2>;
0023 interrupt-controller;
0024 #interrupt-cells = <2>;
0025 reg = <0x0 0x400>;
0026 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
0027 st,bank-name = "GPIOA";
0028 };
0029
0030 gpiob: gpio@40020400 {
0031 gpio-controller;
0032 #gpio-cells = <2>;
0033 interrupt-controller;
0034 #interrupt-cells = <2>;
0035 reg = <0x400 0x400>;
0036 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
0037 st,bank-name = "GPIOB";
0038 };
0039
0040 gpioc: gpio@40020800 {
0041 gpio-controller;
0042 #gpio-cells = <2>;
0043 interrupt-controller;
0044 #interrupt-cells = <2>;
0045 reg = <0x800 0x400>;
0046 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
0047 st,bank-name = "GPIOC";
0048 };
0049
0050 gpiod: gpio@40020c00 {
0051 gpio-controller;
0052 #gpio-cells = <2>;
0053 interrupt-controller;
0054 #interrupt-cells = <2>;
0055 reg = <0xc00 0x400>;
0056 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
0057 st,bank-name = "GPIOD";
0058 };
0059
0060 gpioe: gpio@40021000 {
0061 gpio-controller;
0062 #gpio-cells = <2>;
0063 interrupt-controller;
0064 #interrupt-cells = <2>;
0065 reg = <0x1000 0x400>;
0066 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
0067 st,bank-name = "GPIOE";
0068 };
0069
0070 gpiof: gpio@40021400 {
0071 gpio-controller;
0072 #gpio-cells = <2>;
0073 interrupt-controller;
0074 #interrupt-cells = <2>;
0075 reg = <0x1400 0x400>;
0076 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
0077 st,bank-name = "GPIOF";
0078 };
0079
0080 gpiog: gpio@40021800 {
0081 gpio-controller;
0082 #gpio-cells = <2>;
0083 interrupt-controller;
0084 #interrupt-cells = <2>;
0085 reg = <0x1800 0x400>;
0086 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
0087 st,bank-name = "GPIOG";
0088 };
0089
0090 gpioh: gpio@40021c00 {
0091 gpio-controller;
0092 #gpio-cells = <2>;
0093 interrupt-controller;
0094 #interrupt-cells = <2>;
0095 reg = <0x1c00 0x400>;
0096 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
0097 st,bank-name = "GPIOH";
0098 };
0099
0100 gpioi: gpio@40022000 {
0101 gpio-controller;
0102 #gpio-cells = <2>;
0103 interrupt-controller;
0104 #interrupt-cells = <2>;
0105 reg = <0x2000 0x400>;
0106 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
0107 st,bank-name = "GPIOI";
0108 };
0109
0110 gpioj: gpio@40022400 {
0111 gpio-controller;
0112 #gpio-cells = <2>;
0113 interrupt-controller;
0114 #interrupt-cells = <2>;
0115 reg = <0x2400 0x400>;
0116 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
0117 st,bank-name = "GPIOJ";
0118 };
0119
0120 gpiok: gpio@40022800 {
0121 gpio-controller;
0122 #gpio-cells = <2>;
0123 interrupt-controller;
0124 #interrupt-cells = <2>;
0125 reg = <0x2800 0x400>;
0126 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
0127 st,bank-name = "GPIOK";
0128 };
0129
0130 cec_pins_a: cec-0 {
0131 pins {
0132 pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
0133 slew-rate = <0>;
0134 drive-open-drain;
0135 bias-disable;
0136 };
0137 };
0138
0139 usart1_pins_a: usart1-0 {
0140 pins1 {
0141 pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
0142 bias-disable;
0143 drive-push-pull;
0144 slew-rate = <0>;
0145 };
0146 pins2 {
0147 pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
0148 bias-disable;
0149 };
0150 };
0151
0152 usart1_pins_b: usart1-1 {
0153 pins1 {
0154 pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
0155 bias-disable;
0156 drive-push-pull;
0157 slew-rate = <0>;
0158 };
0159 pins2 {
0160 pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
0161 bias-disable;
0162 };
0163 };
0164
0165 i2c1_pins_b: i2c1-0 {
0166 pins {
0167 pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
0168 <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
0169 bias-disable;
0170 drive-open-drain;
0171 slew-rate = <0>;
0172 };
0173 };
0174
0175 usbotg_hs_pins_a: usbotg-hs-0 {
0176 pins {
0177 pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
0178 <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
0179 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
0180 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
0181 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
0182 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
0183 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
0184 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
0185 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
0186 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
0187 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
0188 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
0189 bias-disable;
0190 drive-push-pull;
0191 slew-rate = <2>;
0192 };
0193 };
0194
0195 usbotg_hs_pins_b: usbotg-hs-1 {
0196 pins {
0197 pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
0198 <STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
0199 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
0200 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
0201 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
0202 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
0203 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
0204 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
0205 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
0206 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
0207 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
0208 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
0209 bias-disable;
0210 drive-push-pull;
0211 slew-rate = <2>;
0212 };
0213 };
0214
0215 usbotg_fs_pins_a: usbotg-fs-0 {
0216 pins {
0217 pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
0218 <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
0219 <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
0220 bias-disable;
0221 drive-push-pull;
0222 slew-rate = <2>;
0223 };
0224 };
0225
0226 sdio_pins_a: sdio-pins-a-0 {
0227 pins {
0228 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
0229 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
0230 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
0231 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
0232 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
0233 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
0234 drive-push-pull;
0235 slew-rate = <2>;
0236 };
0237 };
0238
0239 sdio_pins_od_a: sdio-pins-od-a-0 {
0240 pins1 {
0241 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
0242 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
0243 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
0244 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
0245 <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
0246 drive-push-pull;
0247 slew-rate = <2>;
0248 };
0249
0250 pins2 {
0251 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
0252 drive-open-drain;
0253 slew-rate = <2>;
0254 };
0255 };
0256
0257 sdio_pins_b: sdio-pins-b-0 {
0258 pins {
0259 pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
0260 <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
0261 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
0262 <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
0263 <STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
0264 <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
0265 drive-push-pull;
0266 slew-rate = <2>;
0267 };
0268 };
0269
0270 sdio_pins_od_b: sdio-pins-od-b-0 {
0271 pins1 {
0272 pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
0273 <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
0274 <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
0275 <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
0276 <STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
0277 drive-push-pull;
0278 slew-rate = <2>;
0279 };
0280
0281 pins2 {
0282 pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
0283 drive-open-drain;
0284 slew-rate = <2>;
0285 };
0286 };
0287 };
0288 };
0289 };
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