0001 /*
0002 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
0003 *
0004 * This file is dual-licensed: you can use it either under the terms
0005 * of the GPL or the X11 license, at your option. Note that this dual
0006 * licensing only applies to this file, and not this project as a
0007 * whole.
0008 *
0009 * a) This file is free software; you can redistribute it and/or
0010 * modify it under the terms of the GNU General Public License as
0011 * published by the Free Software Foundation; either version 2 of the
0012 * License, or (at your option) any later version.
0013 *
0014 * This file is distributed in the hope that it will be useful,
0015 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0017 * GNU General Public License for more details.
0018 *
0019 * You should have received a copy of the GNU General Public
0020 * License along with this file; if not, write to the Free
0021 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
0022 * MA 02110-1301 USA
0023 *
0024 * Or, alternatively,
0025 *
0026 * b) Permission is hereby granted, free of charge, to any person
0027 * obtaining a copy of this software and associated documentation
0028 * files (the "Software"), to deal in the Software without
0029 * restriction, including without limitation the rights to use,
0030 * copy, modify, merge, publish, distribute, sublicense, and/or
0031 * sell copies of the Software, and to permit persons to whom the
0032 * Software is furnished to do so, subject to the following
0033 * conditions:
0034 *
0035 * The above copyright notice and this permission notice shall be
0036 * included in all copies or substantial portions of the Software.
0037 *
0038 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0039 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0040 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0041 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0042 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0043 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0044 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0045 * OTHER DEALINGS IN THE SOFTWARE.
0046 */
0047
0048 #include "armv7-m.dtsi"
0049 #include <dt-bindings/clock/stm32fx-clock.h>
0050 #include <dt-bindings/mfd/stm32f4-rcc.h>
0051
0052 / {
0053 #address-cells = <1>;
0054 #size-cells = <1>;
0055
0056 clocks {
0057 clk_hse: clk-hse {
0058 #clock-cells = <0>;
0059 compatible = "fixed-clock";
0060 clock-frequency = <0>;
0061 };
0062
0063 clk_lse: clk-lse {
0064 #clock-cells = <0>;
0065 compatible = "fixed-clock";
0066 clock-frequency = <32768>;
0067 };
0068
0069 clk_lsi: clk-lsi {
0070 #clock-cells = <0>;
0071 compatible = "fixed-clock";
0072 clock-frequency = <32000>;
0073 };
0074
0075 clk_i2s_ckin: i2s-ckin {
0076 #clock-cells = <0>;
0077 compatible = "fixed-clock";
0078 clock-frequency = <0>;
0079 };
0080 };
0081
0082 soc {
0083 romem: efuse@1fff7800 {
0084 compatible = "st,stm32f4-otp";
0085 reg = <0x1fff7800 0x400>;
0086 #address-cells = <1>;
0087 #size-cells = <1>;
0088 ts_cal1: calib@22c {
0089 reg = <0x22c 0x2>;
0090 };
0091 ts_cal2: calib@22e {
0092 reg = <0x22e 0x2>;
0093 };
0094 };
0095
0096 timers2: timers@40000000 {
0097 #address-cells = <1>;
0098 #size-cells = <0>;
0099 compatible = "st,stm32-timers";
0100 reg = <0x40000000 0x400>;
0101 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
0102 clock-names = "int";
0103 status = "disabled";
0104
0105 pwm {
0106 compatible = "st,stm32-pwm";
0107 #pwm-cells = <3>;
0108 status = "disabled";
0109 };
0110
0111 timer@1 {
0112 compatible = "st,stm32-timer-trigger";
0113 reg = <1>;
0114 status = "disabled";
0115 };
0116 };
0117
0118 timers3: timers@40000400 {
0119 #address-cells = <1>;
0120 #size-cells = <0>;
0121 compatible = "st,stm32-timers";
0122 reg = <0x40000400 0x400>;
0123 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
0124 clock-names = "int";
0125 status = "disabled";
0126
0127 pwm {
0128 compatible = "st,stm32-pwm";
0129 #pwm-cells = <3>;
0130 status = "disabled";
0131 };
0132
0133 timer@2 {
0134 compatible = "st,stm32-timer-trigger";
0135 reg = <2>;
0136 status = "disabled";
0137 };
0138 };
0139
0140 timers4: timers@40000800 {
0141 #address-cells = <1>;
0142 #size-cells = <0>;
0143 compatible = "st,stm32-timers";
0144 reg = <0x40000800 0x400>;
0145 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
0146 clock-names = "int";
0147 status = "disabled";
0148
0149 pwm {
0150 compatible = "st,stm32-pwm";
0151 #pwm-cells = <3>;
0152 status = "disabled";
0153 };
0154
0155 timer@3 {
0156 compatible = "st,stm32-timer-trigger";
0157 reg = <3>;
0158 status = "disabled";
0159 };
0160 };
0161
0162 timers5: timers@40000c00 {
0163 #address-cells = <1>;
0164 #size-cells = <0>;
0165 compatible = "st,stm32-timers";
0166 reg = <0x40000C00 0x400>;
0167 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
0168 clock-names = "int";
0169 status = "disabled";
0170
0171 pwm {
0172 compatible = "st,stm32-pwm";
0173 #pwm-cells = <3>;
0174 status = "disabled";
0175 };
0176
0177 timer@4 {
0178 compatible = "st,stm32-timer-trigger";
0179 reg = <4>;
0180 status = "disabled";
0181 };
0182 };
0183
0184 timers6: timers@40001000 {
0185 #address-cells = <1>;
0186 #size-cells = <0>;
0187 compatible = "st,stm32-timers";
0188 reg = <0x40001000 0x400>;
0189 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
0190 clock-names = "int";
0191 status = "disabled";
0192
0193 timer@5 {
0194 compatible = "st,stm32-timer-trigger";
0195 reg = <5>;
0196 status = "disabled";
0197 };
0198 };
0199
0200 timers7: timers@40001400 {
0201 #address-cells = <1>;
0202 #size-cells = <0>;
0203 compatible = "st,stm32-timers";
0204 reg = <0x40001400 0x400>;
0205 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
0206 clock-names = "int";
0207 status = "disabled";
0208
0209 timer@6 {
0210 compatible = "st,stm32-timer-trigger";
0211 reg = <6>;
0212 status = "disabled";
0213 };
0214 };
0215
0216 timers12: timers@40001800 {
0217 #address-cells = <1>;
0218 #size-cells = <0>;
0219 compatible = "st,stm32-timers";
0220 reg = <0x40001800 0x400>;
0221 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
0222 clock-names = "int";
0223 status = "disabled";
0224
0225 pwm {
0226 compatible = "st,stm32-pwm";
0227 #pwm-cells = <3>;
0228 status = "disabled";
0229 };
0230
0231 timer@11 {
0232 compatible = "st,stm32-timer-trigger";
0233 reg = <11>;
0234 status = "disabled";
0235 };
0236 };
0237
0238 timers13: timers@40001c00 {
0239 compatible = "st,stm32-timers";
0240 reg = <0x40001C00 0x400>;
0241 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
0242 clock-names = "int";
0243 status = "disabled";
0244
0245 pwm {
0246 compatible = "st,stm32-pwm";
0247 #pwm-cells = <3>;
0248 status = "disabled";
0249 };
0250 };
0251
0252 timers14: timers@40002000 {
0253 compatible = "st,stm32-timers";
0254 reg = <0x40002000 0x400>;
0255 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
0256 clock-names = "int";
0257 status = "disabled";
0258
0259 pwm {
0260 compatible = "st,stm32-pwm";
0261 #pwm-cells = <3>;
0262 status = "disabled";
0263 };
0264 };
0265
0266 rtc: rtc@40002800 {
0267 compatible = "st,stm32-rtc";
0268 reg = <0x40002800 0x400>;
0269 clocks = <&rcc 1 CLK_RTC>;
0270 assigned-clocks = <&rcc 1 CLK_RTC>;
0271 assigned-clock-parents = <&rcc 1 CLK_LSE>;
0272 interrupt-parent = <&exti>;
0273 interrupts = <17 1>;
0274 st,syscfg = <&pwrcfg 0x00 0x100>;
0275 status = "disabled";
0276 };
0277
0278 iwdg: watchdog@40003000 {
0279 compatible = "st,stm32-iwdg";
0280 reg = <0x40003000 0x400>;
0281 clocks = <&clk_lsi>;
0282 clock-names = "lsi";
0283 status = "disabled";
0284 };
0285
0286 spi2: spi@40003800 {
0287 #address-cells = <1>;
0288 #size-cells = <0>;
0289 compatible = "st,stm32f4-spi";
0290 reg = <0x40003800 0x400>;
0291 interrupts = <36>;
0292 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
0293 status = "disabled";
0294 };
0295
0296 spi3: spi@40003c00 {
0297 #address-cells = <1>;
0298 #size-cells = <0>;
0299 compatible = "st,stm32f4-spi";
0300 reg = <0x40003c00 0x400>;
0301 interrupts = <51>;
0302 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
0303 status = "disabled";
0304 };
0305
0306 usart2: serial@40004400 {
0307 compatible = "st,stm32-uart";
0308 reg = <0x40004400 0x400>;
0309 interrupts = <38>;
0310 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
0311 status = "disabled";
0312 };
0313
0314 usart3: serial@40004800 {
0315 compatible = "st,stm32-uart";
0316 reg = <0x40004800 0x400>;
0317 interrupts = <39>;
0318 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
0319 status = "disabled";
0320 dmas = <&dma1 1 4 0x400 0x0>,
0321 <&dma1 3 4 0x400 0x0>;
0322 dma-names = "rx", "tx";
0323 };
0324
0325 usart4: serial@40004c00 {
0326 compatible = "st,stm32-uart";
0327 reg = <0x40004c00 0x400>;
0328 interrupts = <52>;
0329 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
0330 status = "disabled";
0331 };
0332
0333 usart5: serial@40005000 {
0334 compatible = "st,stm32-uart";
0335 reg = <0x40005000 0x400>;
0336 interrupts = <53>;
0337 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
0338 status = "disabled";
0339 };
0340
0341 i2c1: i2c@40005400 {
0342 compatible = "st,stm32f4-i2c";
0343 reg = <0x40005400 0x400>;
0344 interrupts = <31>,
0345 <32>;
0346 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
0347 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
0348 #address-cells = <1>;
0349 #size-cells = <0>;
0350 status = "disabled";
0351 };
0352
0353 i2c3: i2c@40005c00 {
0354 compatible = "st,stm32f4-i2c";
0355 reg = <0x40005c00 0x400>;
0356 interrupts = <72>,
0357 <73>;
0358 resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
0359 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
0360 #address-cells = <1>;
0361 #size-cells = <0>;
0362 status = "disabled";
0363 };
0364
0365 dac: dac@40007400 {
0366 compatible = "st,stm32f4-dac-core";
0367 reg = <0x40007400 0x400>;
0368 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
0369 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
0370 clock-names = "pclk";
0371 #address-cells = <1>;
0372 #size-cells = <0>;
0373 status = "disabled";
0374
0375 dac1: dac@1 {
0376 compatible = "st,stm32-dac";
0377 #io-channel-cells = <1>;
0378 reg = <1>;
0379 status = "disabled";
0380 };
0381
0382 dac2: dac@2 {
0383 compatible = "st,stm32-dac";
0384 #io-channel-cells = <1>;
0385 reg = <2>;
0386 status = "disabled";
0387 };
0388 };
0389
0390 usart7: serial@40007800 {
0391 compatible = "st,stm32-uart";
0392 reg = <0x40007800 0x400>;
0393 interrupts = <82>;
0394 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
0395 status = "disabled";
0396 };
0397
0398 usart8: serial@40007c00 {
0399 compatible = "st,stm32-uart";
0400 reg = <0x40007c00 0x400>;
0401 interrupts = <83>;
0402 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
0403 status = "disabled";
0404 };
0405
0406 timers1: timers@40010000 {
0407 #address-cells = <1>;
0408 #size-cells = <0>;
0409 compatible = "st,stm32-timers";
0410 reg = <0x40010000 0x400>;
0411 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
0412 clock-names = "int";
0413 status = "disabled";
0414
0415 pwm {
0416 compatible = "st,stm32-pwm";
0417 #pwm-cells = <3>;
0418 status = "disabled";
0419 };
0420
0421 timer@0 {
0422 compatible = "st,stm32-timer-trigger";
0423 reg = <0>;
0424 status = "disabled";
0425 };
0426 };
0427
0428 timers8: timers@40010400 {
0429 #address-cells = <1>;
0430 #size-cells = <0>;
0431 compatible = "st,stm32-timers";
0432 reg = <0x40010400 0x400>;
0433 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
0434 clock-names = "int";
0435 status = "disabled";
0436
0437 pwm {
0438 compatible = "st,stm32-pwm";
0439 #pwm-cells = <3>;
0440 status = "disabled";
0441 };
0442
0443 timer@7 {
0444 compatible = "st,stm32-timer-trigger";
0445 reg = <7>;
0446 status = "disabled";
0447 };
0448 };
0449
0450 usart1: serial@40011000 {
0451 compatible = "st,stm32-uart";
0452 reg = <0x40011000 0x400>;
0453 interrupts = <37>;
0454 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
0455 status = "disabled";
0456 dmas = <&dma2 2 4 0x400 0x0>,
0457 <&dma2 7 4 0x400 0x0>;
0458 dma-names = "rx", "tx";
0459 };
0460
0461 usart6: serial@40011400 {
0462 compatible = "st,stm32-uart";
0463 reg = <0x40011400 0x400>;
0464 interrupts = <71>;
0465 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
0466 status = "disabled";
0467 };
0468
0469 adc: adc@40012000 {
0470 compatible = "st,stm32f4-adc-core";
0471 reg = <0x40012000 0x400>;
0472 interrupts = <18>;
0473 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
0474 clock-names = "adc";
0475 interrupt-controller;
0476 #interrupt-cells = <1>;
0477 #address-cells = <1>;
0478 #size-cells = <0>;
0479 status = "disabled";
0480
0481 adc1: adc@0 {
0482 compatible = "st,stm32f4-adc";
0483 #io-channel-cells = <1>;
0484 reg = <0x0>;
0485 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
0486 interrupt-parent = <&adc>;
0487 interrupts = <0>;
0488 dmas = <&dma2 0 0 0x400 0x0>;
0489 dma-names = "rx";
0490 status = "disabled";
0491 };
0492
0493 adc2: adc@100 {
0494 compatible = "st,stm32f4-adc";
0495 #io-channel-cells = <1>;
0496 reg = <0x100>;
0497 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
0498 interrupt-parent = <&adc>;
0499 interrupts = <1>;
0500 dmas = <&dma2 3 1 0x400 0x0>;
0501 dma-names = "rx";
0502 status = "disabled";
0503 };
0504
0505 adc3: adc@200 {
0506 compatible = "st,stm32f4-adc";
0507 #io-channel-cells = <1>;
0508 reg = <0x200>;
0509 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
0510 interrupt-parent = <&adc>;
0511 interrupts = <2>;
0512 dmas = <&dma2 1 2 0x400 0x0>;
0513 dma-names = "rx";
0514 status = "disabled";
0515 };
0516 };
0517
0518 sdio: mmc@40012c00 {
0519 compatible = "arm,pl180", "arm,primecell";
0520 arm,primecell-periphid = <0x00880180>;
0521 reg = <0x40012c00 0x400>;
0522 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
0523 clock-names = "apb_pclk";
0524 interrupts = <49>;
0525 max-frequency = <48000000>;
0526 status = "disabled";
0527 };
0528
0529 spi1: spi@40013000 {
0530 #address-cells = <1>;
0531 #size-cells = <0>;
0532 compatible = "st,stm32f4-spi";
0533 reg = <0x40013000 0x400>;
0534 interrupts = <35>;
0535 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
0536 status = "disabled";
0537 };
0538
0539 spi4: spi@40013400 {
0540 #address-cells = <1>;
0541 #size-cells = <0>;
0542 compatible = "st,stm32f4-spi";
0543 reg = <0x40013400 0x400>;
0544 interrupts = <84>;
0545 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
0546 status = "disabled";
0547 };
0548
0549 syscfg: syscon@40013800 {
0550 compatible = "st,stm32-syscfg", "syscon";
0551 reg = <0x40013800 0x400>;
0552 };
0553
0554 exti: interrupt-controller@40013c00 {
0555 compatible = "st,stm32-exti";
0556 interrupt-controller;
0557 #interrupt-cells = <2>;
0558 reg = <0x40013C00 0x400>;
0559 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
0560 };
0561
0562 timers9: timers@40014000 {
0563 #address-cells = <1>;
0564 #size-cells = <0>;
0565 compatible = "st,stm32-timers";
0566 reg = <0x40014000 0x400>;
0567 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
0568 clock-names = "int";
0569 status = "disabled";
0570
0571 pwm {
0572 compatible = "st,stm32-pwm";
0573 #pwm-cells = <3>;
0574 status = "disabled";
0575 };
0576
0577 timer@8 {
0578 compatible = "st,stm32-timer-trigger";
0579 reg = <8>;
0580 status = "disabled";
0581 };
0582 };
0583
0584 timers10: timers@40014400 {
0585 compatible = "st,stm32-timers";
0586 reg = <0x40014400 0x400>;
0587 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
0588 clock-names = "int";
0589 status = "disabled";
0590
0591 pwm {
0592 compatible = "st,stm32-pwm";
0593 #pwm-cells = <3>;
0594 status = "disabled";
0595 };
0596 };
0597
0598 timers11: timers@40014800 {
0599 compatible = "st,stm32-timers";
0600 reg = <0x40014800 0x400>;
0601 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
0602 clock-names = "int";
0603 status = "disabled";
0604
0605 pwm {
0606 compatible = "st,stm32-pwm";
0607 #pwm-cells = <3>;
0608 status = "disabled";
0609 };
0610 };
0611
0612 spi5: spi@40015000 {
0613 #address-cells = <1>;
0614 #size-cells = <0>;
0615 compatible = "st,stm32f4-spi";
0616 reg = <0x40015000 0x400>;
0617 interrupts = <85>;
0618 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
0619 dmas = <&dma2 3 2 0x400 0x0>,
0620 <&dma2 4 2 0x400 0x0>;
0621 dma-names = "rx", "tx";
0622 status = "disabled";
0623 };
0624
0625 spi6: spi@40015400 {
0626 #address-cells = <1>;
0627 #size-cells = <0>;
0628 compatible = "st,stm32f4-spi";
0629 reg = <0x40015400 0x400>;
0630 interrupts = <86>;
0631 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
0632 status = "disabled";
0633 };
0634
0635 pwrcfg: power-config@40007000 {
0636 compatible = "st,stm32-power-config", "syscon";
0637 reg = <0x40007000 0x400>;
0638 };
0639
0640 ltdc: display-controller@40016800 {
0641 compatible = "st,stm32-ltdc";
0642 reg = <0x40016800 0x200>;
0643 interrupts = <88>, <89>;
0644 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
0645 clocks = <&rcc 1 CLK_LCD>;
0646 clock-names = "lcd";
0647 status = "disabled";
0648 };
0649
0650 crc: crc@40023000 {
0651 compatible = "st,stm32f4-crc";
0652 reg = <0x40023000 0x400>;
0653 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
0654 status = "disabled";
0655 };
0656
0657 rcc: rcc@40023800 {
0658 #reset-cells = <1>;
0659 #clock-cells = <2>;
0660 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
0661 reg = <0x40023800 0x400>;
0662 clocks = <&clk_hse>, <&clk_i2s_ckin>;
0663 st,syscfg = <&pwrcfg>;
0664 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
0665 assigned-clock-rates = <1000000>;
0666 };
0667
0668 dma1: dma-controller@40026000 {
0669 compatible = "st,stm32-dma";
0670 reg = <0x40026000 0x400>;
0671 interrupts = <11>,
0672 <12>,
0673 <13>,
0674 <14>,
0675 <15>,
0676 <16>,
0677 <17>,
0678 <47>;
0679 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
0680 #dma-cells = <4>;
0681 };
0682
0683 dma2: dma-controller@40026400 {
0684 compatible = "st,stm32-dma";
0685 reg = <0x40026400 0x400>;
0686 interrupts = <56>,
0687 <57>,
0688 <58>,
0689 <59>,
0690 <60>,
0691 <68>,
0692 <69>,
0693 <70>;
0694 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
0695 #dma-cells = <4>;
0696 st,mem2mem;
0697 };
0698
0699 mac: ethernet@40028000 {
0700 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
0701 reg = <0x40028000 0x8000>;
0702 reg-names = "stmmaceth";
0703 interrupts = <61>;
0704 interrupt-names = "macirq";
0705 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
0706 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
0707 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
0708 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
0709 st,syscon = <&syscfg 0x4>;
0710 snps,pbl = <8>;
0711 snps,mixed-burst;
0712 status = "disabled";
0713 };
0714
0715 dma2d: dma2d@4002b000 {
0716 compatible = "st,stm32-dma2d";
0717 reg = <0x4002b000 0xc00>;
0718 interrupts = <90>;
0719 resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>;
0720 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
0721 clock-names = "dma2d";
0722 status = "disabled";
0723 };
0724
0725 usbotg_hs: usb@40040000 {
0726 compatible = "snps,dwc2";
0727 reg = <0x40040000 0x40000>;
0728 interrupts = <77>;
0729 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
0730 clock-names = "otg";
0731 status = "disabled";
0732 };
0733
0734 usbotg_fs: usb@50000000 {
0735 compatible = "st,stm32f4x9-fsotg";
0736 reg = <0x50000000 0x40000>;
0737 interrupts = <67>;
0738 clocks = <&rcc 0 39>;
0739 clock-names = "otg";
0740 status = "disabled";
0741 };
0742
0743 dcmi: dcmi@50050000 {
0744 compatible = "st,stm32-dcmi";
0745 reg = <0x50050000 0x400>;
0746 interrupts = <78>;
0747 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
0748 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
0749 clock-names = "mclk";
0750 pinctrl-names = "default";
0751 pinctrl-0 = <&dcmi_pins>;
0752 dmas = <&dma2 1 1 0x414 0x3>;
0753 dma-names = "tx";
0754 status = "disabled";
0755 };
0756
0757 rng: rng@50060800 {
0758 compatible = "st,stm32-rng";
0759 reg = <0x50060800 0x400>;
0760 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
0761
0762 };
0763 };
0764 };
0765
0766 &systick {
0767 clocks = <&rcc 1 SYSTICK>;
0768 status = "okay";
0769 };
