OSCL-LXR |
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0001 /*
0002 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
0003 *
0004 * This file is dual-licensed: you can use it either under the terms
0005 * of the GPL or the X11 license, at your option. Note that this dual
0006 * licensing only applies to this file, and not this project as a
0007 * whole.
0008 *
0009 * a) This file is free software; you can redistribute it and/or
0010 * modify it under the terms of the GNU General Public License as
0011 * published by the Free Software Foundation; either version 2 of the
0012 * License, or (at your option) any later version.
0013 *
0014 * This file is distributed in the hope that it will be useful,
0015 * but WITHOUT ANY WARRANTY; without even the implied warranty of
0016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0017 * GNU General Public License for more details.
0018 *
0019 * Or, alternatively,
0020 *
0021 * b) Permission is hereby granted, free of charge, to any person
0022 * obtaining a copy of this software and associated documentation
0023 * files (the "Software"), to deal in the Software without
0024 * restriction, including without limitation the rights to use,
0025 * copy, modify, merge, publish, distribute, sublicense, and/or
0026 * sell copies of the Software, and to permit persons to whom the
0027 * Software is furnished to do so, subject to the following
0028 * conditions:
0029 *
0030 * The above copyright notice and this permission notice shall be
0031 * included in all copies or substantial portions of the Software.
0032 *
0033 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0034 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
0035 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0036 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
0037 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
0038 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0039 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0040 * OTHER DEALINGS IN THE SOFTWARE.
0041 */
0042
0043 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
0044 #include <dt-bindings/mfd/stm32f4-rcc.h>
0045
0046 / {
0047 soc {
0048 pinctrl: pinctrl@40020000 {
0049 #address-cells = <1>;
0050 #size-cells = <1>;
0051 ranges = <0 0x40020000 0x3000>;
0052 interrupt-parent = <&exti>;
0053 st,syscfg = <&syscfg 0x8>;
0054 pins-are-numbered;
0055
0056 gpioa: gpio@40020000 {
0057 gpio-controller;
0058 #gpio-cells = <2>;
0059 interrupt-controller;
0060 #interrupt-cells = <2>;
0061 reg = <0x0 0x400>;
0062 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
0063 st,bank-name = "GPIOA";
0064 };
0065
0066 gpiob: gpio@40020400 {
0067 gpio-controller;
0068 #gpio-cells = <2>;
0069 interrupt-controller;
0070 #interrupt-cells = <2>;
0071 reg = <0x400 0x400>;
0072 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
0073 st,bank-name = "GPIOB";
0074 };
0075
0076 gpioc: gpio@40020800 {
0077 gpio-controller;
0078 #gpio-cells = <2>;
0079 interrupt-controller;
0080 #interrupt-cells = <2>;
0081 reg = <0x800 0x400>;
0082 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
0083 st,bank-name = "GPIOC";
0084 };
0085
0086 gpiod: gpio@40020c00 {
0087 gpio-controller;
0088 #gpio-cells = <2>;
0089 interrupt-controller;
0090 #interrupt-cells = <2>;
0091 reg = <0xc00 0x400>;
0092 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
0093 st,bank-name = "GPIOD";
0094 };
0095
0096 gpioe: gpio@40021000 {
0097 gpio-controller;
0098 #gpio-cells = <2>;
0099 interrupt-controller;
0100 #interrupt-cells = <2>;
0101 reg = <0x1000 0x400>;
0102 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
0103 st,bank-name = "GPIOE";
0104 };
0105
0106 gpiof: gpio@40021400 {
0107 gpio-controller;
0108 #gpio-cells = <2>;
0109 interrupt-controller;
0110 #interrupt-cells = <2>;
0111 reg = <0x1400 0x400>;
0112 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
0113 st,bank-name = "GPIOF";
0114 };
0115
0116 gpiog: gpio@40021800 {
0117 gpio-controller;
0118 #gpio-cells = <2>;
0119 interrupt-controller;
0120 #interrupt-cells = <2>;
0121 reg = <0x1800 0x400>;
0122 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
0123 st,bank-name = "GPIOG";
0124 };
0125
0126 gpioh: gpio@40021c00 {
0127 gpio-controller;
0128 #gpio-cells = <2>;
0129 interrupt-controller;
0130 #interrupt-cells = <2>;
0131 reg = <0x1c00 0x400>;
0132 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
0133 st,bank-name = "GPIOH";
0134 };
0135
0136 gpioi: gpio@40022000 {
0137 gpio-controller;
0138 #gpio-cells = <2>;
0139 interrupt-controller;
0140 #interrupt-cells = <2>;
0141 reg = <0x2000 0x400>;
0142 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
0143 st,bank-name = "GPIOI";
0144 };
0145
0146 gpioj: gpio@40022400 {
0147 gpio-controller;
0148 #gpio-cells = <2>;
0149 interrupt-controller;
0150 #interrupt-cells = <2>;
0151 reg = <0x2400 0x400>;
0152 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
0153 st,bank-name = "GPIOJ";
0154 };
0155
0156 gpiok: gpio@40022800 {
0157 gpio-controller;
0158 #gpio-cells = <2>;
0159 interrupt-controller;
0160 #interrupt-cells = <2>;
0161 reg = <0x2800 0x400>;
0162 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
0163 st,bank-name = "GPIOK";
0164 };
0165
0166 usart1_pins_a: usart1-0 {
0167 pins1 {
0168 pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
0169 bias-disable;
0170 drive-push-pull;
0171 slew-rate = <0>;
0172 };
0173 pins2 {
0174 pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
0175 bias-disable;
0176 };
0177 };
0178
0179 usart3_pins_a: usart3-0 {
0180 pins1 {
0181 pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
0182 bias-disable;
0183 drive-push-pull;
0184 slew-rate = <0>;
0185 };
0186 pins2 {
0187 pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
0188 bias-disable;
0189 };
0190 };
0191
0192 usbotg_fs_pins_a: usbotg-fs-0 {
0193 pins {
0194 pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
0195 <STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
0196 <STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
0197 bias-disable;
0198 drive-push-pull;
0199 slew-rate = <2>;
0200 };
0201 };
0202
0203 usbotg_fs_pins_b: usbotg-fs-1 {
0204 pins {
0205 pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
0206 <STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
0207 <STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */
0208 bias-disable;
0209 drive-push-pull;
0210 slew-rate = <2>;
0211 };
0212 };
0213
0214 usbotg_hs_pins_a: usbotg-hs-0 {
0215 pins {
0216 pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/
0217 <STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
0218 <STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
0219 <STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
0220 <STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
0221 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
0222 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
0223 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
0224 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
0225 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
0226 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
0227 <STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
0228 bias-disable;
0229 drive-push-pull;
0230 slew-rate = <2>;
0231 };
0232 };
0233
0234 ethernet_mii: mii-0 {
0235 pins {
0236 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
0237 <STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
0238 <STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */
0239 <STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */
0240 <STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */
0241 <STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */
0242 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
0243 <STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
0244 <STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */
0245 <STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */
0246 <STM32_PINMUX('C', 4, AF11)>, /* ETH_MII_RXD0_ETH_RMII_RXD0 */
0247 <STM32_PINMUX('C', 5, AF11)>, /* ETH_MII_RXD1_ETH_RMII_RXD1 */
0248 <STM32_PINMUX('H', 6, AF11)>, /* ETH_MII_RXD2 */
0249 <STM32_PINMUX('H', 7, AF11)>; /* ETH_MII_RXD3 */
0250 slew-rate = <2>;
0251 };
0252 };
0253
0254 adc3_in8_pin: adc-200 {
0255 pins {
0256 pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
0257 };
0258 };
0259
0260 pwm1_pins: pwm1-0 {
0261 pins {
0262 pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
0263 <STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
0264 <STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */
0265 };
0266 };
0267
0268 pwm3_pins: pwm3-0 {
0269 pins {
0270 pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
0271 <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
0272 };
0273 };
0274
0275 i2c1_pins: i2c1-0 {
0276 pins {
0277 pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
0278 <STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
0279 bias-disable;
0280 drive-open-drain;
0281 slew-rate = <3>;
0282 };
0283 };
0284
0285 ltdc_pins_a: ltdc-0 {
0286 pins {
0287 pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
0288 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
0289 <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
0290 <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
0291 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
0292 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
0293 <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
0294 <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
0295 <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
0296 <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6*/
0297 <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
0298 <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
0299 <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
0300 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
0301 <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
0302 <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
0303 <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
0304 <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
0305 <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
0306 <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3*/
0307 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
0308 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
0309 <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
0310 <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
0311 <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
0312 <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
0313 <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
0314 <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
0315 slew-rate = <2>;
0316 };
0317 };
0318
0319 ltdc_pins_b: ltdc-1 {
0320 pins {
0321 pinmux = <STM32_PINMUX('C', 6, AF14)>,
0322 /* LCD_HSYNC */
0323 <STM32_PINMUX('A', 4, AF14)>,
0324 /* LCD_VSYNC */
0325 <STM32_PINMUX('G', 7, AF14)>,
0326 /* LCD_CLK */
0327 <STM32_PINMUX('C', 10, AF14)>,
0328 /* LCD_R2 */
0329 <STM32_PINMUX('B', 0, AF9)>,
0330 /* LCD_R3 */
0331 <STM32_PINMUX('A', 11, AF14)>,
0332 /* LCD_R4 */
0333 <STM32_PINMUX('A', 12, AF14)>,
0334 /* LCD_R5 */
0335 <STM32_PINMUX('B', 1, AF9)>,
0336 /* LCD_R6*/
0337 <STM32_PINMUX('G', 6, AF14)>,
0338 /* LCD_R7 */
0339 <STM32_PINMUX('A', 6, AF14)>,
0340 /* LCD_G2 */
0341 <STM32_PINMUX('G', 10, AF9)>,
0342 /* LCD_G3 */
0343 <STM32_PINMUX('B', 10, AF14)>,
0344 /* LCD_G4 */
0345 <STM32_PINMUX('D', 6, AF14)>,
0346 /* LCD_B2 */
0347 <STM32_PINMUX('G', 11, AF14)>,
0348 /* LCD_B3*/
0349 <STM32_PINMUX('B', 11, AF14)>,
0350 /* LCD_G5 */
0351 <STM32_PINMUX('C', 7, AF14)>,
0352 /* LCD_G6 */
0353 <STM32_PINMUX('D', 3, AF14)>,
0354 /* LCD_G7 */
0355 <STM32_PINMUX('G', 12, AF9)>,
0356 /* LCD_B4 */
0357 <STM32_PINMUX('A', 3, AF14)>,
0358 /* LCD_B5 */
0359 <STM32_PINMUX('B', 8, AF14)>,
0360 /* LCD_B6 */
0361 <STM32_PINMUX('B', 9, AF14)>,
0362 /* LCD_B7 */
0363 <STM32_PINMUX('F', 10, AF14)>;
0364 /* LCD_DE */
0365 slew-rate = <2>;
0366 };
0367 };
0368
0369 spi5_pins: spi5-0 {
0370 pins1 {
0371 pinmux = <STM32_PINMUX('F', 7, AF5)>,
0372 /* SPI5_CLK */
0373 <STM32_PINMUX('F', 9, AF5)>;
0374 /* SPI5_MOSI */
0375 bias-disable;
0376 drive-push-pull;
0377 slew-rate = <0>;
0378 };
0379 pins2 {
0380 pinmux = <STM32_PINMUX('F', 8, AF5)>;
0381 /* SPI5_MISO */
0382 bias-disable;
0383 };
0384 };
0385
0386 i2c3_pins: i2c3-0 {
0387 pins {
0388 pinmux = <STM32_PINMUX('C', 9, AF4)>,
0389 /* I2C3_SDA */
0390 <STM32_PINMUX('A', 8, AF4)>;
0391 /* I2C3_SCL */
0392 bias-disable;
0393 drive-open-drain;
0394 slew-rate = <3>;
0395 };
0396 };
0397
0398 dcmi_pins: dcmi-0 {
0399 pins {
0400 pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
0401 <STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
0402 <STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */
0403 <STM32_PINMUX('C', 6, AF13)>, /* DCMI_D0 */
0404 <STM32_PINMUX('C', 7, AF13)>, /* DCMI_D1 */
0405 <STM32_PINMUX('C', 8, AF13)>, /* DCMI_D2 */
0406 <STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */
0407 <STM32_PINMUX('C', 11, AF13)>, /*DCMI_D4 */
0408 <STM32_PINMUX('D', 3, AF13)>, /* DCMI_D5 */
0409 <STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */
0410 <STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */
0411 <STM32_PINMUX('C', 10, AF13)>, /* DCMI_D8 */
0412 <STM32_PINMUX('C', 12, AF13)>, /* DCMI_D9 */
0413 <STM32_PINMUX('D', 6, AF13)>, /* DCMI_D10 */
0414 <STM32_PINMUX('D', 2, AF13)>; /* DCMI_D11 */
0415 bias-disable;
0416 drive-push-pull;
0417 slew-rate = <3>;
0418 };
0419 };
0420
0421 sdio_pins: sdio-pins-0 {
0422 pins {
0423 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
0424 <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
0425 <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
0426 <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
0427 <STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */
0428 <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
0429 drive-push-pull;
0430 slew-rate = <2>;
0431 };
0432 };
0433
0434 sdio_pins_od: sdio-pins-od-0 {
0435 pins1 {
0436 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
0437 <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
0438 <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
0439 <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
0440 <STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */
0441 drive-push-pull;
0442 slew-rate = <2>;
0443 };
0444
0445 pins2 {
0446 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
0447 drive-open-drain;
0448 slew-rate = <2>;
0449 };
0450 };
0451 };
0452 };
0453 };
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