0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2014 STMicroelectronics Limited.
0004 * Author: Peter Griffin <peter.griffin@linaro.org>
0005 */
0006 #include "stih418-clock.dtsi"
0007 #include "stih407-family.dtsi"
0008 #include "stih410-pinctrl.dtsi"
0009 / {
0010 cpus {
0011 #address-cells = <1>;
0012 #size-cells = <0>;
0013 cpu@2 {
0014 device_type = "cpu";
0015 compatible = "arm,cortex-a9";
0016 reg = <2>;
0017 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
0018 cpu-release-addr = <0x94100A4>;
0019 };
0020 cpu@3 {
0021 device_type = "cpu";
0022 compatible = "arm,cortex-a9";
0023 reg = <3>;
0024 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
0025 cpu-release-addr = <0x94100A4>;
0026 };
0027 };
0028
0029 usb2_picophy1: phy2 {
0030 compatible = "st,stih407-usb2-phy";
0031 #phy-cells = <0>;
0032 st,syscfg = <&syscfg_core 0xf8 0xf4>;
0033 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
0034 <&picophyreset STIH407_PICOPHY0_RESET>;
0035 reset-names = "global", "port";
0036 };
0037
0038 usb2_picophy2: phy3 {
0039 compatible = "st,stih407-usb2-phy";
0040 #phy-cells = <0>;
0041 st,syscfg = <&syscfg_core 0xfc 0xf4>;
0042 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
0043 <&picophyreset STIH407_PICOPHY1_RESET>;
0044 reset-names = "global", "port";
0045 };
0046
0047 soc {
0048 rng11: rng@8a8a000 {
0049 status = "disabled";
0050 };
0051
0052 ohci0: usb@9a03c00 {
0053 compatible = "st,st-ohci-300x";
0054 reg = <0x9a03c00 0x100>;
0055 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
0056 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
0057 resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
0058 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
0059 reset-names = "power", "softreset";
0060 phys = <&usb2_picophy1>;
0061 phy-names = "usb";
0062 };
0063
0064 ehci0: usb@9a03e00 {
0065 compatible = "st,st-ehci-300x";
0066 reg = <0x9a03e00 0x100>;
0067 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
0068 pinctrl-names = "default";
0069 pinctrl-0 = <&pinctrl_usb0>;
0070 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
0071 resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
0072 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
0073 reset-names = "power", "softreset";
0074 phys = <&usb2_picophy1>;
0075 phy-names = "usb";
0076 };
0077
0078 ohci1: usb@9a83c00 {
0079 compatible = "st,st-ohci-300x";
0080 reg = <0x9a83c00 0x100>;
0081 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
0082 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
0083 resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
0084 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
0085 reset-names = "power", "softreset";
0086 phys = <&usb2_picophy2>;
0087 phy-names = "usb";
0088 };
0089
0090 ehci1: usb@9a83e00 {
0091 compatible = "st,st-ehci-300x";
0092 reg = <0x9a83e00 0x100>;
0093 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
0094 pinctrl-names = "default";
0095 pinctrl-0 = <&pinctrl_usb1>;
0096 clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
0097 resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
0098 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
0099 reset-names = "power", "softreset";
0100 phys = <&usb2_picophy2>;
0101 phy-names = "usb";
0102 };
0103
0104 mmc0: sdhci@9060000 {
0105 assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
0106 assigned-clock-parents = <&clk_s_c0_pll1 0>;
0107 assigned-clock-rates = <200000000>;
0108 };
0109
0110 thermal@91a0000 {
0111 compatible = "st,stih407-thermal";
0112 reg = <0x91a0000 0x28>;
0113 clock-names = "thermal";
0114 clocks = <&clk_sysin>;
0115 interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
0116 };
0117 };
0118 };
