boot/dts/stih418-b2264.dts

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2021 STMicroelectronics
0004  * Author: Alain Volmat <avolmat@me.com>
0005  */
0006 /dts-v1/;
0007 #include "stih418.dtsi"
0008 #include <dt-bindings/gpio/gpio.h>
0009 / {
0010         model = "STiH418 B2264";
0011         compatible = "st,stih418-b2264", "st,stih418";
0012
0013         chosen {
0014                 stdout-path = &sbc_serial0;
0015         };
0016
0017         memory@40000000 {
0018                 device_type = "memory";
0019                 reg = <0x40000000 0xc0000000>;
0020         };
0021
0022         cpus {
0023                 cpu@0 {
0024                         operating-points-v2 = <&cpu_opp_table>;
0025                         /* u-boot puts hpen in SBC dmem at 0xb8 offset */
0026                         cpu-release-addr = <0x94100b8>;
0027                 };
0028                 cpu@1 {
0029                         operating-points-v2 = <&cpu_opp_table>;
0030                         /* u-boot puts hpen in SBC dmem at 0xb8 offset */
0031                         cpu-release-addr = <0x94100b8>;
0032                 };
0033                 cpu@2 {
0034                         operating-points-v2 = <&cpu_opp_table>;
0035                         /* u-boot puts hpen in SBC dmem at 0xb8 offset */
0036                         cpu-release-addr = <0x94100b8>;
0037                 };
0038                 cpu@3 {
0039                         operating-points-v2 = <&cpu_opp_table>;
0040                         /* u-boot puts hpen in SBC dmem at 0xb8 offset */
0041                         cpu-release-addr = <0x94100b8>;
0042                 };
0043         };
0044
0045         cpu_opp_table: opp_table {
0046                 compatible = "operating-points-v2";
0047                 opp-shared;
0048
0049                 opp00 {
0050                         opp-hz = /bits/ 64 <300000000>;
0051                         opp-microvolt = <784000>;
0052                 };
0053                 opp01 {
0054                         opp-hz = /bits/ 64 <500000000>;
0055                         opp-microvolt = <784000>;
0056                 };
0057                 opp02 {
0058                         opp-hz = /bits/ 64 <800000000>;
0059                         opp-microvolt = <784000>;
0060                 };
0061                 opp03 {
0062                         opp-hz = /bits/ 64 <1200000000>;
0063                         opp-microvolt = <784000>;
0064                 };
0065                 opp04 {
0066                         opp-hz = /bits/ 64 <1500000000>;
0067                         opp-microvolt = <784000>;
0068                 };
0069         };
0070
0071         aliases {
0072                 ttyAS0 = &sbc_serial0;
0073                 ethernet0 = &ethernet0;
0074         };
0075
0076         soc {
0077                 leds {
0078                         compatible = "gpio-leds";
0079                         green {
0080                                 gpios = <&pio1 3 GPIO_ACTIVE_HIGH>;
0081                                 default-state = "off";
0082                         };
0083                 };
0084
0085                 pin-controller-sbc@961f080 {
0086                         gmac1 {
0087                                 rgmii1-0 {
0088                                         st,pins {
0089                                                 rxd0 = <&pio1 4 ALT1 IN DE_IO 300 CLK_A>;
0090                                                 rxd1 = <&pio1 5 ALT1 IN DE_IO 300 CLK_A>;
0091                                                 rxd2 = <&pio1 6 ALT1 IN DE_IO 300 CLK_A>;
0092                                                 rxd3 = <&pio1 7 ALT1 IN DE_IO 300 CLK_A>;
0093                                                 rxdv = <&pio2 0 ALT1 IN DE_IO 300 CLK_A>;
0094                                         };
0095                                 };
0096                         };
0097                 };
0098
0099         };
0100 };
0101
0102 &ehci0 {
0103         status = "okay";
0104 };
0105
0106 &ethernet0 {
0107         phy-mode = "rgmii";
0108         pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>;
0109         st,tx-retime-src = "clkgen";
0110
0111         snps,reset-gpio = <&pio0 7 0>;
0112         snps,reset-active-low;
0113         snps,reset-delays-us = <0 10000 1000000>;
0114
0115         status = "okay";
0116 };
0117
0118 &miphy28lp_phy {
0119         phy_port0: port@9b22000 {
0120                 st,sata-gen = <2>; /* SATA GEN3 */
0121                 st,osc-rdy;
0122         };
0123 };
0124
0125 &mmc0 {
0126         status = "okay";
0127 };
0128
0129 &ohci1 {
0130         status = "okay";
0131 };
0132
0133 &pwm1 {
0134         status = "okay";
0135 };
0136
0137 &sata0 {
0138         status = "okay";
0139 };
0140
0141 &sbc_serial0 {
0142         status = "okay";
0143 };
0144
0145 &spifsm {
0146         status = "okay";
0147 };
0148
0149 &st_dwc3 {
0150         status = "okay";
0151 };