OSCL-LXR |
|
|
|
|||
0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2014 STMicroelectronics R&D Limited
0004 */
0005 #include <dt-bindings/clock/stih410-clks.h>
0006 / {
0007 /*
0008 * Fixed 30MHz oscillator inputs to SoC
0009 */
0010 clk_sysin: clk-sysin {
0011 #clock-cells = <0>;
0012 compatible = "fixed-clock";
0013 clock-frequency = <30000000>;
0014 clock-output-names = "CLK_SYSIN";
0015 };
0016
0017 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
0018 #clock-cells = <0>;
0019 compatible = "fixed-clock";
0020 clock-frequency = <0>;
0021 };
0022
0023 clocks {
0024 #address-cells = <1>;
0025 #size-cells = <1>;
0026 ranges;
0027
0028 compatible = "st,stih410-clk", "simple-bus";
0029
0030 /*
0031 * A9 PLL.
0032 */
0033 clockgen-a9@92b0000 {
0034 compatible = "st,clkgen-c32";
0035 reg = <0x92b0000 0x10000>;
0036
0037 clockgen_a9_pll: clockgen-a9-pll {
0038 #clock-cells = <1>;
0039 compatible = "st,stih407-clkgen-plla9";
0040
0041 clocks = <&clk_sysin>;
0042 };
0043
0044 /*
0045 * ARM CPU related clocks.
0046 */
0047 clk_m_a9: clk-m-a9 {
0048 #clock-cells = <0>;
0049 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
0050
0051 clocks = <&clockgen_a9_pll 0>,
0052 <&clockgen_a9_pll 0>,
0053 <&clk_s_c0_flexgen 13>,
0054 <&clk_m_a9_ext2f_div2>;
0055
0056 /*
0057 * ARM Peripheral clock for timers
0058 */
0059 arm_periph_clk: clk-m-a9-periphs {
0060 #clock-cells = <0>;
0061 compatible = "fixed-factor-clock";
0062 clocks = <&clk_m_a9>;
0063 clock-div = <2>;
0064 clock-mult = <1>;
0065 };
0066 };
0067 };
0068
0069 clockgen-a@90ff000 {
0070 compatible = "st,clkgen-c32";
0071 reg = <0x90ff000 0x1000>;
0072
0073 clk_s_a0_pll: clk-s-a0-pll {
0074 #clock-cells = <1>;
0075 compatible = "st,clkgen-pll0-a0";
0076
0077 clocks = <&clk_sysin>;
0078 };
0079
0080 clk_s_a0_flexgen: clk-s-a0-flexgen {
0081 compatible = "st,flexgen", "st,flexgen-stih410-a0";
0082
0083 #clock-cells = <1>;
0084
0085 clocks = <&clk_s_a0_pll 0>,
0086 <&clk_sysin>;
0087 };
0088 };
0089
0090 clk_s_c0: clockgen-c@9103000 {
0091 compatible = "st,clkgen-c32";
0092 reg = <0x9103000 0x1000>;
0093
0094 clk_s_c0_pll0: clk-s-c0-pll0 {
0095 #clock-cells = <1>;
0096 compatible = "st,clkgen-pll0-c0";
0097
0098 clocks = <&clk_sysin>;
0099 };
0100
0101 clk_s_c0_pll1: clk-s-c0-pll1 {
0102 #clock-cells = <1>;
0103 compatible = "st,clkgen-pll1-c0";
0104
0105 clocks = <&clk_sysin>;
0106 };
0107
0108 clk_s_c0_quadfs: clk-s-c0-quadfs {
0109 #clock-cells = <1>;
0110 compatible = "st,quadfs-pll";
0111
0112 clocks = <&clk_sysin>;
0113 };
0114
0115 clk_s_c0_flexgen: clk-s-c0-flexgen {
0116 #clock-cells = <1>;
0117 compatible = "st,flexgen", "st,flexgen-stih410-c0";
0118
0119 clocks = <&clk_s_c0_pll0 0>,
0120 <&clk_s_c0_pll1 0>,
0121 <&clk_s_c0_quadfs 0>,
0122 <&clk_s_c0_quadfs 1>,
0123 <&clk_s_c0_quadfs 2>,
0124 <&clk_s_c0_quadfs 3>,
0125 <&clk_sysin>;
0126
0127 /*
0128 * ARM Peripheral clock for timers
0129 */
0130 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
0131 #clock-cells = <0>;
0132 compatible = "fixed-factor-clock";
0133
0134 clocks = <&clk_s_c0_flexgen 13>;
0135
0136 clock-output-names = "clk-m-a9-ext2f-div2";
0137
0138 clock-div = <2>;
0139 clock-mult = <1>;
0140 };
0141 };
0142 };
0143
0144 clockgen-d0@9104000 {
0145 compatible = "st,clkgen-c32";
0146 reg = <0x9104000 0x1000>;
0147
0148 clk_s_d0_quadfs: clk-s-d0-quadfs {
0149 #clock-cells = <1>;
0150 compatible = "st,quadfs-d0";
0151
0152 clocks = <&clk_sysin>;
0153 };
0154
0155 clk_s_d0_flexgen: clk-s-d0-flexgen {
0156 #clock-cells = <1>;
0157 compatible = "st,flexgen", "st,flexgen-stih410-d0";
0158
0159 clocks = <&clk_s_d0_quadfs 0>,
0160 <&clk_s_d0_quadfs 1>,
0161 <&clk_s_d0_quadfs 2>,
0162 <&clk_s_d0_quadfs 3>,
0163 <&clk_sysin>;
0164 };
0165 };
0166
0167 clockgen-d2@9106000 {
0168 compatible = "st,clkgen-c32";
0169 reg = <0x9106000 0x1000>;
0170
0171 clk_s_d2_quadfs: clk-s-d2-quadfs {
0172 #clock-cells = <1>;
0173 compatible = "st,quadfs-d2";
0174
0175 clocks = <&clk_sysin>;
0176 };
0177
0178 clk_s_d2_flexgen: clk-s-d2-flexgen {
0179 #clock-cells = <1>;
0180 compatible = "st,flexgen", "st,flexgen-stih407-d2";
0181
0182 clocks = <&clk_s_d2_quadfs 0>,
0183 <&clk_s_d2_quadfs 1>,
0184 <&clk_s_d2_quadfs 2>,
0185 <&clk_s_d2_quadfs 3>,
0186 <&clk_sysin>,
0187 <&clk_sysin>,
0188 <&clk_tmdsout_hdmi>;
0189 };
0190 };
0191
0192 clockgen-d3@9107000 {
0193 compatible = "st,clkgen-c32";
0194 reg = <0x9107000 0x1000>;
0195
0196 clk_s_d3_quadfs: clk-s-d3-quadfs {
0197 #clock-cells = <1>;
0198 compatible = "st,quadfs-d3";
0199
0200 clocks = <&clk_sysin>;
0201 };
0202
0203 clk_s_d3_flexgen: clk-s-d3-flexgen {
0204 #clock-cells = <1>;
0205 compatible = "st,flexgen", "st,flexgen-stih407-d3";
0206
0207 clocks = <&clk_s_d3_quadfs 0>,
0208 <&clk_s_d3_quadfs 1>,
0209 <&clk_s_d3_quadfs 2>,
0210 <&clk_s_d3_quadfs 3>,
0211 <&clk_sysin>;
0212 };
0213 };
0214 };
0215 };
| [ Source navigation ] | [ Diff markup ] | [ Identifier search ] | [ general search ] |
|
This page was automatically generated by the 2.1.0 LXR engine. The LXR team |
|