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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2015 STMicroelectronics Limited.
0004 * Author: Gabriel Fernandez <gabriel.fernandez@linaro.org>
0005 */
0006 #include "stih407-clock.dtsi"
0007 #include "stih407-family.dtsi"
0008 #include <dt-bindings/gpio/gpio.h>
0009 / {
0010 soc {
0011 sti-display-subsystem@0 {
0012 compatible = "st,sti-display-subsystem";
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015 reg = <0 0>;
0016 assigned-clocks = <&clk_s_d2_quadfs 0>,
0017 <&clk_s_d2_quadfs 1>,
0018 <&clk_s_c0_pll1 0>,
0019 <&clk_s_c0_flexgen CLK_COMPO_DVP>,
0020 <&clk_s_c0_flexgen CLK_MAIN_DISP>,
0021 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
0022 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
0023 <&clk_s_d2_flexgen CLK_PIX_GDP1>,
0024 <&clk_s_d2_flexgen CLK_PIX_GDP2>,
0025 <&clk_s_d2_flexgen CLK_PIX_GDP3>,
0026 <&clk_s_d2_flexgen CLK_PIX_GDP4>;
0027
0028 assigned-clock-parents = <0>,
0029 <0>,
0030 <0>,
0031 <&clk_s_c0_pll1 0>,
0032 <&clk_s_c0_pll1 0>,
0033 <&clk_s_d2_quadfs 0>,
0034 <&clk_s_d2_quadfs 1>,
0035 <&clk_s_d2_quadfs 0>,
0036 <&clk_s_d2_quadfs 0>,
0037 <&clk_s_d2_quadfs 0>,
0038 <&clk_s_d2_quadfs 0>;
0039
0040 assigned-clock-rates = <297000000>,
0041 <108000000>,
0042 <0>,
0043 <400000000>,
0044 <400000000>;
0045
0046 ranges;
0047
0048 sti-compositor@9d11000 {
0049 compatible = "st,stih407-compositor";
0050 reg = <0x9d11000 0x1000>;
0051
0052 clock-names = "compo_main",
0053 "compo_aux",
0054 "pix_main",
0055 "pix_aux",
0056 "pix_gdp1",
0057 "pix_gdp2",
0058 "pix_gdp3",
0059 "pix_gdp4",
0060 "main_parent",
0061 "aux_parent";
0062
0063 clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
0064 <&clk_s_c0_flexgen CLK_COMPO_DVP>,
0065 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
0066 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
0067 <&clk_s_d2_flexgen CLK_PIX_GDP1>,
0068 <&clk_s_d2_flexgen CLK_PIX_GDP2>,
0069 <&clk_s_d2_flexgen CLK_PIX_GDP3>,
0070 <&clk_s_d2_flexgen CLK_PIX_GDP4>,
0071 <&clk_s_d2_quadfs 0>,
0072 <&clk_s_d2_quadfs 1>;
0073
0074 reset-names = "compo-main", "compo-aux";
0075 resets = <&softreset STIH407_COMPO_SOFTRESET>,
0076 <&softreset STIH407_COMPO_SOFTRESET>;
0077 st,vtg = <&vtg_main>, <&vtg_aux>;
0078 };
0079
0080 sti-tvout@8d08000 {
0081 compatible = "st,stih407-tvout";
0082 reg = <0x8d08000 0x1000>;
0083 reg-names = "tvout-reg";
0084 reset-names = "tvout";
0085 resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
0086 #address-cells = <1>;
0087 #size-cells = <1>;
0088 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
0089 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
0090 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
0091 <&clk_s_d0_flexgen CLK_PCM_0>,
0092 <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
0093 <&clk_s_d2_flexgen CLK_HDDAC>;
0094
0095 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
0096 <&clk_tmdsout_hdmi>,
0097 <&clk_s_d2_quadfs 0>,
0098 <&clk_s_d0_quadfs 0>,
0099 <&clk_s_d2_quadfs 0>,
0100 <&clk_s_d2_quadfs 0>;
0101 };
0102
0103 sti_hdmi: sti-hdmi@8d04000 {
0104 compatible = "st,stih407-hdmi";
0105 reg = <0x8d04000 0x1000>;
0106 reg-names = "hdmi-reg";
0107 #sound-dai-cells = <0>;
0108 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
0109 interrupt-names = "irq";
0110 clock-names = "pix",
0111 "tmds",
0112 "phy",
0113 "audio",
0114 "main_parent",
0115 "aux_parent";
0116
0117 clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
0118 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
0119 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
0120 <&clk_s_d0_flexgen CLK_PCM_0>,
0121 <&clk_s_d2_quadfs 0>,
0122 <&clk_s_d2_quadfs 1>;
0123
0124 hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
0125 reset-names = "hdmi";
0126 resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
0127 ddc = <&hdmiddc>;
0128 };
0129
0130 sti-hda@8d02000 {
0131 compatible = "st,stih407-hda";
0132 reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
0133 reg-names = "hda-reg", "video-dacs-ctrl";
0134 clock-names = "pix",
0135 "hddac",
0136 "main_parent",
0137 "aux_parent";
0138 clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
0139 <&clk_s_d2_flexgen CLK_HDDAC>,
0140 <&clk_s_d2_quadfs 0>,
0141 <&clk_s_d2_quadfs 1>;
0142 };
0143 };
0144 };
0145 };
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