OSCL-LXR |
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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2014 STMicroelectronics Limited.
0004 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
0005 */
0006 #include "st-pincfg.h"
0007 #include <dt-bindings/interrupt-controller/arm-gic.h>
0008 / {
0009
0010 aliases {
0011 /* 0-5: PIO_SBC */
0012 gpio0 = &pio0;
0013 gpio1 = &pio1;
0014 gpio2 = &pio2;
0015 gpio3 = &pio3;
0016 gpio4 = &pio4;
0017 gpio5 = &pio5;
0018 /* 10-19: PIO_FRONT0 */
0019 gpio6 = &pio10;
0020 gpio7 = &pio11;
0021 gpio8 = &pio12;
0022 gpio9 = &pio13;
0023 gpio10 = &pio14;
0024 gpio11 = &pio15;
0025 gpio12 = &pio16;
0026 gpio13 = &pio17;
0027 gpio14 = &pio18;
0028 gpio15 = &pio19;
0029 /* 20: PIO_FRONT1 */
0030 gpio16 = &pio20;
0031 /* 30-35: PIO_REAR */
0032 gpio17 = &pio30;
0033 gpio18 = &pio31;
0034 gpio19 = &pio32;
0035 gpio20 = &pio33;
0036 gpio21 = &pio34;
0037 gpio22 = &pio35;
0038 /* 40-42: PIO_FLASH */
0039 gpio23 = &pio40;
0040 gpio24 = &pio41;
0041 gpio25 = &pio42;
0042 };
0043
0044 soc {
0045 pin-controller-sbc@961f080 {
0046 #address-cells = <1>;
0047 #size-cells = <1>;
0048 compatible = "st,stih407-sbc-pinctrl";
0049 st,syscfg = <&syscfg_sbc>;
0050 reg = <0x0961f080 0x4>;
0051 reg-names = "irqmux";
0052 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
0053 interrupt-names = "irqmux";
0054 ranges = <0 0x09610000 0x6000>;
0055
0056 pio0: gpio@9610000 {
0057 gpio-controller;
0058 #gpio-cells = <2>;
0059 interrupt-controller;
0060 #interrupt-cells = <2>;
0061 reg = <0x0 0x100>;
0062 st,bank-name = "PIO0";
0063 };
0064 pio1: gpio@9611000 {
0065 gpio-controller;
0066 #gpio-cells = <2>;
0067 interrupt-controller;
0068 #interrupt-cells = <2>;
0069 reg = <0x1000 0x100>;
0070 st,bank-name = "PIO1";
0071 };
0072 pio2: gpio@9612000 {
0073 gpio-controller;
0074 #gpio-cells = <2>;
0075 interrupt-controller;
0076 #interrupt-cells = <2>;
0077 reg = <0x2000 0x100>;
0078 st,bank-name = "PIO2";
0079 };
0080 pio3: gpio@9613000 {
0081 gpio-controller;
0082 #gpio-cells = <2>;
0083 interrupt-controller;
0084 #interrupt-cells = <2>;
0085 reg = <0x3000 0x100>;
0086 st,bank-name = "PIO3";
0087 };
0088 pio4: gpio@9614000 {
0089 gpio-controller;
0090 #gpio-cells = <2>;
0091 interrupt-controller;
0092 #interrupt-cells = <2>;
0093 reg = <0x4000 0x100>;
0094 st,bank-name = "PIO4";
0095 };
0096
0097 pio5: gpio@9615000 {
0098 gpio-controller;
0099 #gpio-cells = <2>;
0100 interrupt-controller;
0101 #interrupt-cells = <2>;
0102 reg = <0x5000 0x100>;
0103 st,bank-name = "PIO5";
0104 st,retime-pin-mask = <0x3f>;
0105 };
0106
0107 cec0 {
0108 pinctrl_cec0_default: cec0-default {
0109 st,pins {
0110 hdmi_cec = <&pio2 4 ALT1 BIDIR>;
0111 };
0112 };
0113 };
0114
0115 rc {
0116 pinctrl_ir: ir0 {
0117 st,pins {
0118 ir = <&pio4 0 ALT2 IN>;
0119 };
0120 };
0121
0122 pinctrl_uhf: uhf0 {
0123 st,pins {
0124 ir = <&pio4 1 ALT2 IN>;
0125 };
0126 };
0127
0128 pinctrl_tx: tx0 {
0129 st,pins {
0130 tx = <&pio4 2 ALT2 OUT>;
0131 };
0132 };
0133
0134 pinctrl_tx_od: tx_od0 {
0135 st,pins {
0136 tx_od = <&pio4 3 ALT2 OUT>;
0137 };
0138 };
0139 };
0140
0141 /* SBC_ASC0 - UART10 */
0142 sbc_serial0 {
0143 pinctrl_sbc_serial0: sbc_serial0-0 {
0144 st,pins {
0145 tx = <&pio3 4 ALT1 OUT>;
0146 rx = <&pio3 5 ALT1 IN>;
0147 };
0148 };
0149 };
0150 /* SBC_ASC1 - UART11 */
0151 sbc_serial1 {
0152 pinctrl_sbc_serial1: sbc_serial1-0 {
0153 st,pins {
0154 tx = <&pio2 6 ALT3 OUT>;
0155 rx = <&pio2 7 ALT3 IN>;
0156 };
0157 };
0158 };
0159
0160 i2c10 {
0161 pinctrl_i2c10_default: i2c10-default {
0162 st,pins {
0163 sda = <&pio4 6 ALT1 BIDIR>;
0164 scl = <&pio4 5 ALT1 BIDIR>;
0165 };
0166 };
0167 };
0168
0169 i2c11 {
0170 pinctrl_i2c11_default: i2c11-default {
0171 st,pins {
0172 sda = <&pio5 1 ALT1 BIDIR>;
0173 scl = <&pio5 0 ALT1 BIDIR>;
0174 };
0175 };
0176 };
0177
0178 keyscan {
0179 pinctrl_keyscan: keyscan {
0180 st,pins {
0181 keyin0 = <&pio4 0 ALT6 IN>;
0182 keyin1 = <&pio4 5 ALT4 IN>;
0183 keyin2 = <&pio0 4 ALT2 IN>;
0184 keyin3 = <&pio2 6 ALT2 IN>;
0185
0186 keyout0 = <&pio4 6 ALT4 OUT>;
0187 keyout1 = <&pio1 7 ALT2 OUT>;
0188 keyout2 = <&pio0 6 ALT2 OUT>;
0189 keyout3 = <&pio2 7 ALT2 OUT>;
0190 };
0191 };
0192 };
0193
0194 gmac1 {
0195 /*
0196 * Almost all the boards based on STiH407 SoC have an embedded
0197 * switch where the mdio/mdc have been used for managing the SMI
0198 * iface via I2C. For this reason these lines can be allocated
0199 * by using dedicated configuration (in case of there will be a
0200 * standard PHY transceiver on-board).
0201 */
0202 pinctrl_rgmii1: rgmii1-0 {
0203 st,pins {
0204
0205 txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>;
0206 txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>;
0207 txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>;
0208 txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>;
0209 txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
0210 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
0211 rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>;
0212 rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
0213 rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
0214 rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
0215 rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>;
0216 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
0217 clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
0218 phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>;
0219 };
0220 };
0221
0222 pinctrl_rgmii1_mdio: rgmii1-mdio {
0223 st,pins {
0224 mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
0225 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
0226 mdint = <&pio1 3 ALT1 IN BYPASS 0>;
0227 };
0228 };
0229
0230 pinctrl_rgmii1_mdio_1: rgmii1-mdio-1 {
0231 st,pins {
0232 mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
0233 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
0234 };
0235 };
0236
0237 pinctrl_mii1: mii1 {
0238 st,pins {
0239 txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
0240 txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
0241 txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
0242 txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
0243 txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
0244 txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
0245 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
0246 col = <&pio0 7 ALT1 IN BYPASS 1000>;
0247
0248 mdio = <&pio1 0 ALT1 OUT BYPASS 1500>;
0249 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
0250 crs = <&pio1 2 ALT1 IN BYPASS 1000>;
0251 mdint = <&pio1 3 ALT1 IN BYPASS 0>;
0252 rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0253 rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0254 rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0255 rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0256
0257 rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0258 rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0259 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
0260 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
0261 };
0262 };
0263
0264 pinctrl_rmii1: rmii1-0 {
0265 st,pins {
0266 txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
0267 txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
0268 txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
0269 mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
0270 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
0271 mdint = <&pio1 3 ALT1 IN BYPASS 0>;
0272 rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_B>;
0273 rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_B>;
0274 rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_B>;
0275 rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0276 };
0277 };
0278
0279 pinctrl_rmii1_phyclk: rmii1_phyclk {
0280 st,pins {
0281 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
0282 };
0283 };
0284
0285 pinctrl_rmii1_phyclk_ext: rmii1_phyclk_ext {
0286 st,pins {
0287 phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>;
0288 };
0289 };
0290 };
0291
0292 pwm1 {
0293 pinctrl_pwm1_chan0_default: pwm1-0-default {
0294 st,pins {
0295 pwm-out = <&pio3 0 ALT1 OUT>;
0296 pwm-capturein = <&pio3 2 ALT1 IN>;
0297 };
0298 };
0299 pinctrl_pwm1_chan1_default: pwm1-1-default {
0300 st,pins {
0301 pwm-capturein = <&pio4 3 ALT1 IN>;
0302 pwm-out = <&pio4 4 ALT1 OUT>;
0303 };
0304 };
0305 pinctrl_pwm1_chan2_default: pwm1-2-default {
0306 st,pins {
0307 pwm-out = <&pio4 6 ALT3 OUT>;
0308 };
0309 };
0310 pinctrl_pwm1_chan3_default: pwm1-3-default {
0311 st,pins {
0312 pwm-out = <&pio4 7 ALT3 OUT>;
0313 };
0314 };
0315 };
0316
0317 spi10 {
0318 pinctrl_spi10_default: spi10-4w-alt1-0 {
0319 st,pins {
0320 mtsr = <&pio4 6 ALT1 OUT>;
0321 mrst = <&pio4 7 ALT1 IN>;
0322 scl = <&pio4 5 ALT1 OUT>;
0323 };
0324 };
0325
0326 pinctrl_spi10_3w_alt1_0: spi10-3w-alt1-0 {
0327 st,pins {
0328 mtsr = <&pio4 6 ALT1 BIDIR_PU>;
0329 scl = <&pio4 5 ALT1 OUT>;
0330 };
0331 };
0332 };
0333
0334 spi11 {
0335 pinctrl_spi11_default: spi11-4w-alt2-0 {
0336 st,pins {
0337 mtsr = <&pio3 1 ALT2 OUT>;
0338 mrst = <&pio3 0 ALT2 IN>;
0339 scl = <&pio3 2 ALT2 OUT>;
0340 };
0341 };
0342
0343 pinctrl_spi11_3w_alt2_0: spi11-3w-alt2-0 {
0344 st,pins {
0345 mtsr = <&pio3 1 ALT2 BIDIR_PU>;
0346 scl = <&pio3 2 ALT2 OUT>;
0347 };
0348 };
0349 };
0350
0351 spi12 {
0352 pinctrl_spi12_default: spi12-4w-alt2-0 {
0353 st,pins {
0354 mtsr = <&pio3 6 ALT2 OUT>;
0355 mrst = <&pio3 4 ALT2 IN>;
0356 scl = <&pio3 7 ALT2 OUT>;
0357 };
0358 };
0359
0360 pinctrl_spi12_3w_alt2_0: spi12-3w-alt2-0 {
0361 st,pins {
0362 mtsr = <&pio3 6 ALT2 BIDIR_PU>;
0363 scl = <&pio3 7 ALT2 OUT>;
0364 };
0365 };
0366 };
0367 };
0368
0369 pin-controller-front0@920f080 {
0370 #address-cells = <1>;
0371 #size-cells = <1>;
0372 compatible = "st,stih407-front-pinctrl";
0373 st,syscfg = <&syscfg_front>;
0374 reg = <0x0920f080 0x4>;
0375 reg-names = "irqmux";
0376 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
0377 interrupt-names = "irqmux";
0378 ranges = <0 0x09200000 0x10000>;
0379
0380 pio10: pio@9200000 {
0381 gpio-controller;
0382 #gpio-cells = <2>;
0383 interrupt-controller;
0384 #interrupt-cells = <2>;
0385 reg = <0x0 0x100>;
0386 st,bank-name = "PIO10";
0387 };
0388 pio11: pio@9201000 {
0389 gpio-controller;
0390 #gpio-cells = <2>;
0391 interrupt-controller;
0392 #interrupt-cells = <2>;
0393 reg = <0x1000 0x100>;
0394 st,bank-name = "PIO11";
0395 };
0396 pio12: pio@9202000 {
0397 gpio-controller;
0398 #gpio-cells = <2>;
0399 interrupt-controller;
0400 #interrupt-cells = <2>;
0401 reg = <0x2000 0x100>;
0402 st,bank-name = "PIO12";
0403 };
0404 pio13: pio@9203000 {
0405 gpio-controller;
0406 #gpio-cells = <2>;
0407 interrupt-controller;
0408 #interrupt-cells = <2>;
0409 reg = <0x3000 0x100>;
0410 st,bank-name = "PIO13";
0411 };
0412 pio14: pio@9204000 {
0413 gpio-controller;
0414 #gpio-cells = <2>;
0415 interrupt-controller;
0416 #interrupt-cells = <2>;
0417 reg = <0x4000 0x100>;
0418 st,bank-name = "PIO14";
0419 };
0420 pio15: pio@9205000 {
0421 gpio-controller;
0422 #gpio-cells = <2>;
0423 interrupt-controller;
0424 #interrupt-cells = <2>;
0425 reg = <0x5000 0x100>;
0426 st,bank-name = "PIO15";
0427 };
0428 pio16: pio@9206000 {
0429 gpio-controller;
0430 #gpio-cells = <2>;
0431 interrupt-controller;
0432 #interrupt-cells = <2>;
0433 reg = <0x6000 0x100>;
0434 st,bank-name = "PIO16";
0435 };
0436 pio17: pio@9207000 {
0437 gpio-controller;
0438 #gpio-cells = <2>;
0439 interrupt-controller;
0440 #interrupt-cells = <2>;
0441 reg = <0x7000 0x100>;
0442 st,bank-name = "PIO17";
0443 };
0444 pio18: pio@9208000 {
0445 gpio-controller;
0446 #gpio-cells = <2>;
0447 interrupt-controller;
0448 #interrupt-cells = <2>;
0449 reg = <0x8000 0x100>;
0450 st,bank-name = "PIO18";
0451 };
0452 pio19: pio@9209000 {
0453 gpio-controller;
0454 #gpio-cells = <2>;
0455 interrupt-controller;
0456 #interrupt-cells = <2>;
0457 reg = <0x9000 0x100>;
0458 st,bank-name = "PIO19";
0459 };
0460
0461 /* Comms */
0462 serial0 {
0463 pinctrl_serial0: serial0-0 {
0464 st,pins {
0465 tx = <&pio17 0 ALT1 OUT>;
0466 rx = <&pio17 1 ALT1 IN>;
0467 };
0468 };
0469 pinctrl_serial0_hw_flowctrl: serial0-0_hw_flowctrl {
0470 st,pins {
0471 tx = <&pio17 0 ALT1 OUT>;
0472 rx = <&pio17 1 ALT1 IN>;
0473 cts = <&pio17 2 ALT1 IN>;
0474 rts = <&pio17 3 ALT1 OUT>;
0475 };
0476 };
0477 };
0478
0479 serial1 {
0480 pinctrl_serial1: serial1-0 {
0481 st,pins {
0482 tx = <&pio16 0 ALT1 OUT>;
0483 rx = <&pio16 1 ALT1 IN>;
0484 };
0485 };
0486 };
0487
0488 serial2 {
0489 pinctrl_serial2: serial2-0 {
0490 st,pins {
0491 tx = <&pio15 0 ALT1 OUT>;
0492 rx = <&pio15 1 ALT1 IN>;
0493 };
0494 };
0495 };
0496
0497 mmc1 {
0498 pinctrl_sd1: sd1-0 {
0499 st,pins {
0500 sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>;
0501 sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>;
0502 sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>;
0503 sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>;
0504 sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>;
0505 sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>;
0506 sd_led = <&pio16 6 ALT6 OUT>;
0507 sd_pwren = <&pio16 7 ALT6 OUT>;
0508 sd_cd = <&pio19 0 ALT6 IN>;
0509 sd_wp = <&pio19 1 ALT6 IN>;
0510 };
0511 };
0512 };
0513
0514
0515 i2c0 {
0516 pinctrl_i2c0_default: i2c0-default {
0517 st,pins {
0518 sda = <&pio10 6 ALT2 BIDIR>;
0519 scl = <&pio10 5 ALT2 BIDIR>;
0520 };
0521 };
0522 };
0523
0524 i2c1 {
0525 pinctrl_i2c1_default: i2c1-default {
0526 st,pins {
0527 sda = <&pio11 1 ALT2 BIDIR>;
0528 scl = <&pio11 0 ALT2 BIDIR>;
0529 };
0530 };
0531 };
0532
0533 i2c2 {
0534 pinctrl_i2c2_default: i2c2-default {
0535 st,pins {
0536 sda = <&pio15 6 ALT2 BIDIR>;
0537 scl = <&pio15 5 ALT2 BIDIR>;
0538 };
0539 };
0540
0541 pinctrl_i2c2_alt2_1: i2c2-alt2-1 {
0542 st,pins {
0543 sda = <&pio12 6 ALT2 BIDIR>;
0544 scl = <&pio12 5 ALT2 BIDIR>;
0545 };
0546 };
0547 };
0548
0549 i2c3 {
0550 pinctrl_i2c3_default: i2c3-alt1-0 {
0551 st,pins {
0552 sda = <&pio18 6 ALT1 BIDIR>;
0553 scl = <&pio18 5 ALT1 BIDIR>;
0554 };
0555 };
0556 pinctrl_i2c3_alt1_1: i2c3-alt1-1 {
0557 st,pins {
0558 sda = <&pio17 7 ALT1 BIDIR>;
0559 scl = <&pio17 6 ALT1 BIDIR>;
0560 };
0561 };
0562 pinctrl_i2c3_alt3_0: i2c3-alt3-0 {
0563 st,pins {
0564 sda = <&pio13 6 ALT3 BIDIR>;
0565 scl = <&pio13 5 ALT3 BIDIR>;
0566 };
0567 };
0568 };
0569
0570 spi0 {
0571 pinctrl_spi0_default: spi0-4w-alt2-0 {
0572 st,pins {
0573 mtsr = <&pio10 6 ALT2 OUT>;
0574 mrst = <&pio10 7 ALT2 IN>;
0575 scl = <&pio10 5 ALT2 OUT>;
0576 };
0577 };
0578
0579 pinctrl_spi0_3w_alt2_0: spi0-3w-alt2-0 {
0580 st,pins {
0581 mtsr = <&pio10 6 ALT2 BIDIR_PU>;
0582 scl = <&pio10 5 ALT2 OUT>;
0583 };
0584 };
0585
0586 pinctrl_spi0_4w_alt1_0: spi0-4w-alt1-0 {
0587 st,pins {
0588 mtsr = <&pio19 7 ALT1 OUT>;
0589 mrst = <&pio19 5 ALT1 IN>;
0590 scl = <&pio19 6 ALT1 OUT>;
0591 };
0592 };
0593
0594 pinctrl_spi0_3w_alt1_0: spi0-3w-alt1-0 {
0595 st,pins {
0596 mtsr = <&pio19 7 ALT1 BIDIR_PU>;
0597 scl = <&pio19 6 ALT1 OUT>;
0598 };
0599 };
0600 };
0601
0602 spi1 {
0603 pinctrl_spi1_default: spi1-4w-alt2-0 {
0604 st,pins {
0605 mtsr = <&pio11 1 ALT2 OUT>;
0606 mrst = <&pio11 2 ALT2 IN>;
0607 scl = <&pio11 0 ALT2 OUT>;
0608 };
0609 };
0610
0611 pinctrl_spi1_3w_alt2_0: spi1-3w-alt2-0 {
0612 st,pins {
0613 mtsr = <&pio11 1 ALT2 BIDIR_PU>;
0614 scl = <&pio11 0 ALT2 OUT>;
0615 };
0616 };
0617
0618 pinctrl_spi1_4w_alt1_0: spi1-4w-alt1-0 {
0619 st,pins {
0620 mtsr = <&pio14 3 ALT1 OUT>;
0621 mrst = <&pio14 4 ALT1 IN>;
0622 scl = <&pio14 2 ALT1 OUT>;
0623 };
0624 };
0625
0626 pinctrl_spi1_3w_alt1_0: spi1-3w-alt1-0 {
0627 st,pins {
0628 mtsr = <&pio14 3 ALT1 BIDIR_PU>;
0629 scl = <&pio14 2 ALT1 OUT>;
0630 };
0631 };
0632 };
0633
0634 spi2 {
0635 pinctrl_spi2_default: spi2-4w-alt2-0 {
0636 st,pins {
0637 mtsr = <&pio12 6 ALT2 OUT>;
0638 mrst = <&pio12 7 ALT2 IN>;
0639 scl = <&pio12 5 ALT2 OUT>;
0640 };
0641 };
0642
0643 pinctrl_spi2_3w_alt2_0: spi2-3w-alt2-0 {
0644 st,pins {
0645 mtsr = <&pio12 6 ALT2 BIDIR_PU>;
0646 scl = <&pio12 5 ALT2 OUT>;
0647 };
0648 };
0649
0650 pinctrl_spi2_4w_alt1_0: spi2-4w-alt1-0 {
0651 st,pins {
0652 mtsr = <&pio14 6 ALT1 OUT>;
0653 mrst = <&pio14 7 ALT1 IN>;
0654 scl = <&pio14 5 ALT1 OUT>;
0655 };
0656 };
0657
0658 pinctrl_spi2_3w_alt1_0: spi2-3w-alt1-0 {
0659 st,pins {
0660 mtsr = <&pio14 6 ALT1 BIDIR_PU>;
0661 scl = <&pio14 5 ALT1 OUT>;
0662 };
0663 };
0664
0665 pinctrl_spi2_4w_alt2_1: spi2-4w-alt2-1 {
0666 st,pins {
0667 mtsr = <&pio15 6 ALT2 OUT>;
0668 mrst = <&pio15 7 ALT2 IN>;
0669 scl = <&pio15 5 ALT2 OUT>;
0670 };
0671 };
0672
0673 pinctrl_spi2_3w_alt2_1: spi2-3w-alt2-1 {
0674 st,pins {
0675 mtsr = <&pio15 6 ALT2 BIDIR_PU>;
0676 scl = <&pio15 5 ALT2 OUT>;
0677 };
0678 };
0679 };
0680
0681 spi3 {
0682 pinctrl_spi3_default: spi3-4w-alt3-0 {
0683 st,pins {
0684 mtsr = <&pio13 6 ALT3 OUT>;
0685 mrst = <&pio13 7 ALT3 IN>;
0686 scl = <&pio13 5 ALT3 OUT>;
0687 };
0688 };
0689
0690 pinctrl_spi3_3w_alt3_0: spi3-3w-alt3-0 {
0691 st,pins {
0692 mtsr = <&pio13 6 ALT3 BIDIR_PU>;
0693 scl = <&pio13 5 ALT3 OUT>;
0694 };
0695 };
0696
0697 pinctrl_spi3_4w_alt1_0: spi3-4w-alt1-0 {
0698 st,pins {
0699 mtsr = <&pio17 7 ALT1 OUT>;
0700 mrst = <&pio17 5 ALT1 IN>;
0701 scl = <&pio17 6 ALT1 OUT>;
0702 };
0703 };
0704
0705 pinctrl_spi3_3w_alt1_0: spi3-3w-alt1-0 {
0706 st,pins {
0707 mtsr = <&pio17 7 ALT1 BIDIR_PU>;
0708 scl = <&pio17 6 ALT1 OUT>;
0709 };
0710 };
0711
0712 pinctrl_spi3_4w_alt1_1: spi3-4w-alt1-1 {
0713 st,pins {
0714 mtsr = <&pio18 6 ALT1 OUT>;
0715 mrst = <&pio18 7 ALT1 IN>;
0716 scl = <&pio18 5 ALT1 OUT>;
0717 };
0718 };
0719
0720 pinctrl_spi3_3w_alt1_1: spi3-3w-alt1-1 {
0721 st,pins {
0722 mtsr = <&pio18 6 ALT1 BIDIR_PU>;
0723 scl = <&pio18 5 ALT1 OUT>;
0724 };
0725 };
0726 };
0727
0728 tsin0 {
0729 pinctrl_tsin0_parallel: tsin0_parallel {
0730 st,pins {
0731 DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0732 DATA6 = <&pio10 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0733 DATA5 = <&pio10 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0734 DATA4 = <&pio10 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0735 DATA3 = <&pio11 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0736 DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0737 DATA1 = <&pio11 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0738 DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0739 CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
0740 VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0741 ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0742 PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0743 };
0744 };
0745 pinctrl_tsin0_serial: tsin0_serial {
0746 st,pins {
0747 DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0748 CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
0749 VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0750 ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0751 PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0752 };
0753 };
0754 };
0755
0756 tsin1 {
0757 pinctrl_tsin1_parallel: tsin1_parallel {
0758 st,pins {
0759 DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0760 DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0761 DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0762 DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0763 DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0764 DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0765 DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0766 DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0767 CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
0768 VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0769 ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0770 PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0771 };
0772 };
0773 pinctrl_tsin1_serial: tsin1_serial {
0774 st,pins {
0775 DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0776 CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
0777 VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0778 ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0779 PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0780 };
0781 };
0782 };
0783
0784 tsin2 {
0785 pinctrl_tsin2_parallel: tsin2_parallel {
0786 st,pins {
0787 DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0788 DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>;
0789 DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>;
0790 DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>;
0791 DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
0792 DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>;
0793 DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
0794 DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
0795 CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
0796 VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0797 ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0798 PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0799 };
0800 };
0801 pinctrl_tsin2_serial: tsin2_serial {
0802 st,pins {
0803 DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0804 CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
0805 VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0806 ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0807 PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0808 };
0809 };
0810 };
0811
0812 tsin3 {
0813 pinctrl_tsin3_serial: tsin3_serial {
0814 st,pins {
0815 DATA7 = <&pio14 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0816 CLKIN = <&pio14 0 ALT1 IN CLKNOTDATA 0 CLK_A>;
0817 VALID = <&pio13 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0818 ERROR = <&pio13 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0819 PKCLK = <&pio13 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0820 };
0821 };
0822 };
0823
0824 tsin4 {
0825 pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 {
0826 st,pins {
0827 DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;
0828 CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>;
0829 VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>;
0830 ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>;
0831 PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;
0832 };
0833 };
0834 };
0835
0836 tsin5 {
0837 pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 {
0838 st,pins {
0839 DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0840 CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
0841 VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0842 ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0843 PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0844 };
0845 };
0846 pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 {
0847 st,pins {
0848 DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>;
0849 CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>;
0850 VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
0851 ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
0852 PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
0853 };
0854 };
0855 };
0856
0857 tsout0 {
0858 pinctrl_tsout0_parallel: tsout0_parallel {
0859 st,pins {
0860 DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
0861 DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
0862 DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
0863 DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
0864 DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
0865 DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
0866 DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
0867 DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
0868 CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
0869 VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
0870 ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
0871 PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
0872 };
0873 };
0874 pinctrl_tsout0_serial: tsout0_serial {
0875 st,pins {
0876 DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
0877 CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
0878 VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
0879 ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
0880 PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
0881 };
0882 };
0883 };
0884
0885 tsout1 {
0886 pinctrl_tsout1_serial: tsout1_serial {
0887 st,pins {
0888 DATA7 = <&pio19 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
0889 CLKIN = <&pio19 3 ALT1 OUT NICLK 0 CLK_A>;
0890 VALID = <&pio19 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
0891 ERROR = <&pio19 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
0892 PKCLK = <&pio19 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
0893 };
0894 };
0895 };
0896
0897 mtsin0 {
0898 pinctrl_mtsin0_parallel: mtsin0_parallel {
0899 st,pins {
0900 DATA7 = <&pio10 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;
0901 DATA6 = <&pio10 5 ALT3 IN SE_NICLK_IO 0 CLK_A>;
0902 DATA5 = <&pio10 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;
0903 DATA4 = <&pio10 7 ALT3 IN SE_NICLK_IO 0 CLK_A>;
0904 DATA3 = <&pio11 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;
0905 DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
0906 DATA1 = <&pio11 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;
0907 DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>;
0908 CLKIN = <&pio10 3 ALT3 IN CLKNOTDATA 0 CLK_A>;
0909 VALID = <&pio10 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
0910 ERROR = <&pio10 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;
0911 PKCLK = <&pio10 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;
0912 };
0913 };
0914 };
0915
0916 systrace {
0917 pinctrl_systrace_default: systrace-default {
0918 st,pins {
0919 trc_data0 = <&pio11 3 ALT5 OUT>;
0920 trc_data1 = <&pio11 4 ALT5 OUT>;
0921 trc_data2 = <&pio11 5 ALT5 OUT>;
0922 trc_data3 = <&pio11 6 ALT5 OUT>;
0923 trc_clk = <&pio11 7 ALT5 OUT>;
0924 };
0925 };
0926 };
0927 };
0928
0929 pin-controller-front1@921f080 {
0930 #address-cells = <1>;
0931 #size-cells = <1>;
0932 compatible = "st,stih407-front-pinctrl";
0933 st,syscfg = <&syscfg_front>;
0934 reg = <0x0921f080 0x4>;
0935 reg-names = "irqmux";
0936 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
0937 interrupt-names = "irqmux";
0938 ranges = <0 0x09210000 0x10000>;
0939
0940 pio20: pio@9210000 {
0941 gpio-controller;
0942 #gpio-cells = <2>;
0943 interrupt-controller;
0944 #interrupt-cells = <2>;
0945 reg = <0x0 0x100>;
0946 st,bank-name = "PIO20";
0947 };
0948
0949 tsin4 {
0950 pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 {
0951 st,pins {
0952 DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0953 CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
0954 VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0955 ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0956 PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
0957 };
0958 };
0959 };
0960 };
0961
0962 pin-controller-rear@922f080 {
0963 #address-cells = <1>;
0964 #size-cells = <1>;
0965 compatible = "st,stih407-rear-pinctrl";
0966 st,syscfg = <&syscfg_rear>;
0967 reg = <0x0922f080 0x4>;
0968 reg-names = "irqmux";
0969 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
0970 interrupt-names = "irqmux";
0971 ranges = <0 0x09220000 0x6000>;
0972
0973 pio30: gpio@9220000 {
0974 gpio-controller;
0975 #gpio-cells = <2>;
0976 interrupt-controller;
0977 #interrupt-cells = <2>;
0978 reg = <0x0 0x100>;
0979 st,bank-name = "PIO30";
0980 };
0981 pio31: gpio@9221000 {
0982 gpio-controller;
0983 #gpio-cells = <2>;
0984 interrupt-controller;
0985 #interrupt-cells = <2>;
0986 reg = <0x1000 0x100>;
0987 st,bank-name = "PIO31";
0988 };
0989 pio32: gpio@9222000 {
0990 gpio-controller;
0991 #gpio-cells = <2>;
0992 interrupt-controller;
0993 #interrupt-cells = <2>;
0994 reg = <0x2000 0x100>;
0995 st,bank-name = "PIO32";
0996 };
0997 pio33: gpio@9223000 {
0998 gpio-controller;
0999 #gpio-cells = <2>;
1000 interrupt-controller;
1001 #interrupt-cells = <2>;
1002 reg = <0x3000 0x100>;
1003 st,bank-name = "PIO33";
1004 };
1005 pio34: gpio@9224000 {
1006 gpio-controller;
1007 #gpio-cells = <2>;
1008 interrupt-controller;
1009 #interrupt-cells = <2>;
1010 reg = <0x4000 0x100>;
1011 st,bank-name = "PIO34";
1012 };
1013 pio35: gpio@9225000 {
1014 gpio-controller;
1015 #gpio-cells = <2>;
1016 interrupt-controller;
1017 #interrupt-cells = <2>;
1018 reg = <0x5000 0x100>;
1019 st,bank-name = "PIO35";
1020 st,retime-pin-mask = <0x7f>;
1021 };
1022
1023 i2c4 {
1024 pinctrl_i2c4_default: i2c4-default {
1025 st,pins {
1026 sda = <&pio30 1 ALT1 BIDIR>;
1027 scl = <&pio30 0 ALT1 BIDIR>;
1028 };
1029 };
1030 };
1031
1032 i2c5 {
1033 pinctrl_i2c5_default: i2c5-default {
1034 st,pins {
1035 sda = <&pio34 4 ALT1 BIDIR>;
1036 scl = <&pio34 3 ALT1 BIDIR>;
1037 };
1038 };
1039 };
1040
1041 usb3 {
1042 pinctrl_usb3: usb3-2 {
1043 st,pins {
1044 usb-oc-detect = <&pio35 4 ALT1 IN>;
1045 usb-pwr-enable = <&pio35 5 ALT1 OUT>;
1046 usb-vbus-valid = <&pio35 6 ALT1 IN>;
1047 };
1048 };
1049 };
1050
1051 pwm0 {
1052 pinctrl_pwm0_chan0_default: pwm0-0-default {
1053 st,pins {
1054 pwm-capturein = <&pio31 0 ALT1 IN>;
1055 pwm-out = <&pio31 1 ALT1 OUT>;
1056 };
1057 };
1058 };
1059
1060 spi4 {
1061 pinctrl_spi4_default: spi4-4w-alt1-0 {
1062 st,pins {
1063 mtsr = <&pio30 1 ALT1 OUT>;
1064 mrst = <&pio30 2 ALT1 IN>;
1065 scl = <&pio30 0 ALT1 OUT>;
1066 };
1067 };
1068
1069 pinctrl_spi4_3w_alt1_0: spi4-3w-alt1-0 {
1070 st,pins {
1071 mtsr = <&pio30 1 ALT1 BIDIR_PU>;
1072 scl = <&pio30 0 ALT1 OUT>;
1073 };
1074 };
1075
1076 pinctrl_spi4_4w_alt3_0: spi4-4w-alt3-0 {
1077 st,pins {
1078 mtsr = <&pio34 1 ALT3 OUT>;
1079 mrst = <&pio34 2 ALT3 IN>;
1080 scl = <&pio34 0 ALT3 OUT>;
1081 };
1082 };
1083
1084 pinctrl_spi4_3w_alt3_0: spi4-3w-alt3-0 {
1085 st,pins {
1086 mtsr = <&pio34 1 ALT3 BIDIR_PU>;
1087 scl = <&pio34 0 ALT3 OUT>;
1088 };
1089 };
1090 };
1091
1092 i2s_out {
1093 pinctrl_i2s_8ch_out: i2s_8ch_out{
1094 st,pins {
1095 mclk = <&pio33 5 ALT1 OUT>;
1096 lrclk = <&pio33 7 ALT1 OUT>;
1097 sclk = <&pio33 6 ALT1 OUT>;
1098 data0 = <&pio33 4 ALT1 OUT>;
1099 data1 = <&pio34 0 ALT1 OUT>;
1100 data2 = <&pio34 1 ALT1 OUT>;
1101 data3 = <&pio34 2 ALT1 OUT>;
1102 };
1103 };
1104
1105 pinctrl_i2s_2ch_out: i2s_2ch_out{
1106 st,pins {
1107 mclk = <&pio33 5 ALT1 OUT>;
1108 lrclk = <&pio33 7 ALT1 OUT>;
1109 sclk = <&pio33 6 ALT1 OUT>;
1110 data0 = <&pio33 4 ALT1 OUT>;
1111 };
1112 };
1113 };
1114
1115 i2s_in {
1116 pinctrl_i2s_8ch_in: i2s_8ch_in{
1117 st,pins {
1118 mclk = <&pio32 5 ALT1 IN>;
1119 lrclk = <&pio32 7 ALT1 IN>;
1120 sclk = <&pio32 6 ALT1 IN>;
1121 data0 = <&pio32 4 ALT1 IN>;
1122 data1 = <&pio33 0 ALT1 IN>;
1123 data2 = <&pio33 1 ALT1 IN>;
1124 data3 = <&pio33 2 ALT1 IN>;
1125 data4 = <&pio33 3 ALT1 IN>;
1126 };
1127 };
1128
1129 pinctrl_i2s_2ch_in: i2s_2ch_in{
1130 st,pins {
1131 mclk = <&pio32 5 ALT1 IN>;
1132 lrclk = <&pio32 7 ALT1 IN>;
1133 sclk = <&pio32 6 ALT1 IN>;
1134 data0 = <&pio32 4 ALT1 IN>;
1135 };
1136 };
1137 };
1138
1139 spdif_out {
1140 pinctrl_spdif_out: spdif_out{
1141 st,pins {
1142 spdif_out = <&pio34 7 ALT1 OUT>;
1143 };
1144 };
1145 };
1146
1147 serial3 {
1148 pinctrl_serial3: serial3-0 {
1149 st,pins {
1150 tx = <&pio31 3 ALT1 OUT>;
1151 rx = <&pio31 4 ALT1 IN>;
1152 };
1153 };
1154 };
1155 };
1156
1157 pin-controller-flash@923f080 {
1158 #address-cells = <1>;
1159 #size-cells = <1>;
1160 compatible = "st,stih407-flash-pinctrl";
1161 st,syscfg = <&syscfg_flash>;
1162 reg = <0x0923f080 0x4>;
1163 reg-names = "irqmux";
1164 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
1165 interrupt-names = "irqmux";
1166 ranges = <0 0x09230000 0x3000>;
1167
1168 pio40: gpio@9230000 {
1169 gpio-controller;
1170 #gpio-cells = <2>;
1171 interrupt-controller;
1172 #interrupt-cells = <2>;
1173 reg = <0 0x100>;
1174 st,bank-name = "PIO40";
1175 };
1176 pio41: gpio@9231000 {
1177 gpio-controller;
1178 #gpio-cells = <2>;
1179 interrupt-controller;
1180 #interrupt-cells = <2>;
1181 reg = <0x1000 0x100>;
1182 st,bank-name = "PIO41";
1183 };
1184 pio42: gpio@9232000 {
1185 gpio-controller;
1186 #gpio-cells = <2>;
1187 interrupt-controller;
1188 #interrupt-cells = <2>;
1189 reg = <0x2000 0x100>;
1190 st,bank-name = "PIO42";
1191 };
1192
1193 mmc0 {
1194 pinctrl_mmc0: mmc0-0 {
1195 st,pins {
1196 emmc_clk = <&pio40 6 ALT1 BIDIR>;
1197 emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>;
1198 emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>;
1199 emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>;
1200 emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>;
1201 emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>;
1202 emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>;
1203 emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>;
1204 emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>;
1205 emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>;
1206 };
1207 };
1208 pinctrl_sd0: sd0-0 {
1209 st,pins {
1210 sd_clk = <&pio40 6 ALT1 BIDIR>;
1211 sd_cmd = <&pio40 7 ALT1 BIDIR_PU>;
1212 sd_dat0 = <&pio41 0 ALT1 BIDIR_PU>;
1213 sd_dat1 = <&pio41 1 ALT1 BIDIR_PU>;
1214 sd_dat2 = <&pio41 2 ALT1 BIDIR_PU>;
1215 sd_dat3 = <&pio41 3 ALT1 BIDIR_PU>;
1216 sd_led = <&pio42 0 ALT2 OUT>;
1217 sd_pwren = <&pio42 2 ALT2 OUT>;
1218 sd_vsel = <&pio42 3 ALT2 OUT>;
1219 sd_cd = <&pio42 4 ALT2 IN>;
1220 sd_wp = <&pio42 5 ALT2 IN>;
1221 };
1222 };
1223 };
1224
1225 fsm {
1226 pinctrl_fsm: fsm {
1227 st,pins {
1228 spi-fsm-clk = <&pio40 1 ALT1 OUT>;
1229 spi-fsm-cs = <&pio40 0 ALT1 OUT>;
1230 spi-fsm-mosi = <&pio40 2 ALT1 OUT>;
1231 spi-fsm-miso = <&pio40 3 ALT1 IN>;
1232 spi-fsm-hol = <&pio40 5 ALT1 OUT>;
1233 spi-fsm-wp = <&pio40 4 ALT1 OUT>;
1234 };
1235 };
1236 };
1237
1238 nand {
1239 pinctrl_nand: nand {
1240 st,pins {
1241 nand_cs1 = <&pio40 6 ALT3 OUT>;
1242 nand_cs0 = <&pio40 7 ALT3 OUT>;
1243 nand_d0 = <&pio41 0 ALT3 BIDIR>;
1244 nand_d1 = <&pio41 1 ALT3 BIDIR>;
1245 nand_d2 = <&pio41 2 ALT3 BIDIR>;
1246 nand_d3 = <&pio41 3 ALT3 BIDIR>;
1247 nand_d4 = <&pio41 4 ALT3 BIDIR>;
1248 nand_d5 = <&pio41 5 ALT3 BIDIR>;
1249 nand_d6 = <&pio41 6 ALT3 BIDIR>;
1250 nand_d7 = <&pio41 7 ALT3 BIDIR>;
1251 nand_we = <&pio42 0 ALT3 OUT>;
1252 nand_dqs = <&pio42 1 ALT3 OUT>;
1253 nand_ale = <&pio42 2 ALT3 OUT>;
1254 nand_cle = <&pio42 3 ALT3 OUT>;
1255 nand_rnb = <&pio42 4 ALT3 IN>;
1256 nand_oe = <&pio42 5 ALT3 OUT>;
1257 };
1258 };
1259 };
1260 };
1261 };
1262 };
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