0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2014 STMicroelectronics Limited.
0004 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
0005 */
0006 #include "stih407-pinctrl.dtsi"
0007 #include <dt-bindings/mfd/st-lpc.h>
0008 #include <dt-bindings/phy/phy.h>
0009 #include <dt-bindings/reset/stih407-resets.h>
0010 #include <dt-bindings/interrupt-controller/irq-st.h>
0011 / {
0012 #address-cells = <1>;
0013 #size-cells = <1>;
0014
0015 reserved-memory {
0016 #address-cells = <1>;
0017 #size-cells = <1>;
0018 ranges;
0019
0020 gp0_reserved: rproc@45000000 {
0021 compatible = "shared-dma-pool";
0022 reg = <0x45000000 0x00400000>;
0023 no-map;
0024 };
0025
0026 delta_reserved: rproc@44000000 {
0027 compatible = "shared-dma-pool";
0028 reg = <0x44000000 0x01000000>;
0029 no-map;
0030 };
0031 };
0032
0033 cpus {
0034 #address-cells = <1>;
0035 #size-cells = <0>;
0036 cpu@0 {
0037 device_type = "cpu";
0038 compatible = "arm,cortex-a9";
0039 reg = <0>;
0040
0041 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
0042 cpu-release-addr = <0x94100A4>;
0043
0044 /* kHz uV */
0045 operating-points = <1500000 0
0046 1200000 0
0047 800000 0
0048 500000 0>;
0049
0050 clocks = <&clk_m_a9>;
0051 clock-names = "cpu";
0052 clock-latency = <100000>;
0053 cpu0-supply = <&pwm_regulator>;
0054 st,syscfg = <&syscfg_core 0x8e0>;
0055 };
0056 cpu@1 {
0057 device_type = "cpu";
0058 compatible = "arm,cortex-a9";
0059 reg = <1>;
0060
0061 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
0062 cpu-release-addr = <0x94100A4>;
0063
0064 /* kHz uV */
0065 operating-points = <1500000 0
0066 1200000 0
0067 800000 0
0068 500000 0>;
0069 };
0070 };
0071
0072 intc: interrupt-controller@8761000 {
0073 compatible = "arm,cortex-a9-gic";
0074 #interrupt-cells = <3>;
0075 interrupt-controller;
0076 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
0077 };
0078
0079 scu@8760000 {
0080 compatible = "arm,cortex-a9-scu";
0081 reg = <0x08760000 0x1000>;
0082 };
0083
0084 timer@8760200 {
0085 interrupt-parent = <&intc>;
0086 compatible = "arm,cortex-a9-global-timer";
0087 reg = <0x08760200 0x100>;
0088 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
0089 clocks = <&arm_periph_clk>;
0090 };
0091
0092 l2: cache-controller@8762000 {
0093 compatible = "arm,pl310-cache";
0094 reg = <0x08762000 0x1000>;
0095 arm,data-latency = <3 3 3>;
0096 arm,tag-latency = <2 2 2>;
0097 cache-unified;
0098 cache-level = <2>;
0099 };
0100
0101 arm-pmu {
0102 interrupt-parent = <&intc>;
0103 compatible = "arm,cortex-a9-pmu";
0104 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
0105 };
0106
0107 pwm_regulator: pwm-regulator {
0108 compatible = "pwm-regulator";
0109 pwms = <&pwm1 3 8448>;
0110 regulator-name = "CPU_1V0_AVS";
0111 regulator-min-microvolt = <784000>;
0112 regulator-max-microvolt = <1299000>;
0113 regulator-always-on;
0114 max-duty-cycle = <255>;
0115 status = "okay";
0116 };
0117
0118 restart: restart-controller {
0119 compatible = "st,stih407-restart";
0120 st,syscfg = <&syscfg_sbc_reg>;
0121 status = "okay";
0122 };
0123
0124 powerdown: powerdown-controller {
0125 compatible = "st,stih407-powerdown";
0126 #reset-cells = <1>;
0127 };
0128
0129 softreset: softreset-controller {
0130 compatible = "st,stih407-softreset";
0131 #reset-cells = <1>;
0132 };
0133
0134 picophyreset: picophyreset-controller {
0135 compatible = "st,stih407-picophyreset";
0136 #reset-cells = <1>;
0137 };
0138
0139 irq-syscfg {
0140 compatible = "st,stih407-irq-syscfg";
0141 st,syscfg = <&syscfg_core>;
0142 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
0143 <ST_IRQ_SYSCFG_PMU_1>;
0144 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
0145 <ST_IRQ_SYSCFG_DISABLED>;
0146 };
0147
0148 usb2_picophy0: phy1 {
0149 compatible = "st,stih407-usb2-phy";
0150 #phy-cells = <0>;
0151 st,syscfg = <&syscfg_core 0x100 0xf4>;
0152 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
0153 <&picophyreset STIH407_PICOPHY2_RESET>;
0154 reset-names = "global", "port";
0155 };
0156
0157 miphy28lp_phy: miphy28lp {
0158 compatible = "st,miphy28lp-phy";
0159 st,syscfg = <&syscfg_core>;
0160 #address-cells = <1>;
0161 #size-cells = <1>;
0162 ranges;
0163
0164 phy_port0: port@9b22000 {
0165 reg = <0x9b22000 0xff>,
0166 <0x9b09000 0xff>,
0167 <0x9b04000 0xff>;
0168 reg-names = "sata-up",
0169 "pcie-up",
0170 "pipew";
0171
0172 st,syscfg = <0x114 0x818 0xe0 0xec>;
0173 #phy-cells = <1>;
0174
0175 reset-names = "miphy-sw-rst";
0176 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
0177 };
0178
0179 phy_port1: port@9b2a000 {
0180 reg = <0x9b2a000 0xff>,
0181 <0x9b19000 0xff>,
0182 <0x9b14000 0xff>;
0183 reg-names = "sata-up",
0184 "pcie-up",
0185 "pipew";
0186
0187 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
0188
0189 #phy-cells = <1>;
0190
0191 reset-names = "miphy-sw-rst";
0192 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
0193 };
0194
0195 phy_port2: port@8f95000 {
0196 reg = <0x8f95000 0xff>,
0197 <0x8f90000 0xff>;
0198 reg-names = "pipew",
0199 "usb3-up";
0200
0201 st,syscfg = <0x11c 0x820>;
0202
0203 #phy-cells = <1>;
0204
0205 reset-names = "miphy-sw-rst";
0206 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
0207 };
0208 };
0209
0210 st231_gp0: st231-gp0 {
0211 compatible = "st,st231-rproc";
0212 memory-region = <&gp0_reserved>;
0213 resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
0214 reset-names = "sw_reset";
0215 clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
0216 clock-frequency = <600000000>;
0217 st,syscfg = <&syscfg_core 0x22c>;
0218 #mbox-cells = <1>;
0219 mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
0220 mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>;
0221 };
0222
0223 st231_delta: st231-delta {
0224 compatible = "st,st231-rproc";
0225 memory-region = <&delta_reserved>;
0226 resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
0227 reset-names = "sw_reset";
0228 clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
0229 clock-frequency = <600000000>;
0230 st,syscfg = <&syscfg_core 0x224>;
0231 #mbox-cells = <1>;
0232 mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx";
0233 mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
0234 };
0235
0236 delta0 {
0237 compatible = "st,st-delta";
0238 clock-names = "delta",
0239 "delta-st231",
0240 "delta-flash-promip";
0241 clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
0242 <&clk_s_c0_flexgen CLK_ST231_DMU>,
0243 <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
0244 };
0245
0246 soc {
0247 #address-cells = <1>;
0248 #size-cells = <1>;
0249 interrupt-parent = <&intc>;
0250 ranges;
0251 compatible = "simple-bus";
0252
0253 syscfg_sbc: sbc-syscfg@9620000 {
0254 compatible = "st,stih407-sbc-syscfg", "syscon";
0255 reg = <0x9620000 0x1000>;
0256 };
0257
0258 syscfg_front: front-syscfg@9280000 {
0259 compatible = "st,stih407-front-syscfg", "syscon";
0260 reg = <0x9280000 0x1000>;
0261 };
0262
0263 syscfg_rear: rear-syscfg@9290000 {
0264 compatible = "st,stih407-rear-syscfg", "syscon";
0265 reg = <0x9290000 0x1000>;
0266 };
0267
0268 syscfg_flash: flash-syscfg@92a0000 {
0269 compatible = "st,stih407-flash-syscfg", "syscon";
0270 reg = <0x92a0000 0x1000>;
0271 };
0272
0273 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
0274 compatible = "st,stih407-sbc-reg-syscfg", "syscon";
0275 reg = <0x9600000 0x1000>;
0276 };
0277
0278 syscfg_core: core-syscfg@92b0000 {
0279 compatible = "st,stih407-core-syscfg", "syscon";
0280 reg = <0x92b0000 0x1000>;
0281
0282 sti_sasg_codec: sti-sasg-codec {
0283 compatible = "st,stih407-sas-codec";
0284 #sound-dai-cells = <1>;
0285 status = "disabled";
0286 st,syscfg = <&syscfg_core>;
0287 };
0288 };
0289
0290 syscfg_lpm: lpm-syscfg@94b5100 {
0291 compatible = "st,stih407-lpm-syscfg", "syscon";
0292 reg = <0x94b5100 0x1000>;
0293 };
0294
0295 /* Display */
0296 vtg_main: sti-vtg-main@8d02800 {
0297 compatible = "st,vtg";
0298 reg = <0x8d02800 0x200>;
0299 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
0300 };
0301
0302 vtg_aux: sti-vtg-aux@8d00200 {
0303 compatible = "st,vtg";
0304 reg = <0x8d00200 0x100>;
0305 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
0306 };
0307
0308 serial@9830000 {
0309 compatible = "st,asc";
0310 reg = <0x9830000 0x2c>;
0311 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
0312 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
0313 /* Pinctrl moved out to a per-board configuration */
0314
0315 status = "disabled";
0316 };
0317
0318 serial@9831000 {
0319 compatible = "st,asc";
0320 reg = <0x9831000 0x2c>;
0321 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
0322 pinctrl-names = "default";
0323 pinctrl-0 = <&pinctrl_serial1>;
0324 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
0325
0326 status = "disabled";
0327 };
0328
0329 serial@9832000 {
0330 compatible = "st,asc";
0331 reg = <0x9832000 0x2c>;
0332 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
0333 pinctrl-names = "default";
0334 pinctrl-0 = <&pinctrl_serial2>;
0335 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
0336
0337 status = "disabled";
0338 };
0339
0340 /* SBC_ASC0 - UART10 */
0341 sbc_serial0: serial@9530000 {
0342 compatible = "st,asc";
0343 reg = <0x9530000 0x2c>;
0344 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
0345 pinctrl-names = "default";
0346 pinctrl-0 = <&pinctrl_sbc_serial0>;
0347 clocks = <&clk_sysin>;
0348
0349 status = "disabled";
0350 };
0351
0352 serial@9531000 {
0353 compatible = "st,asc";
0354 reg = <0x9531000 0x2c>;
0355 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
0356 pinctrl-names = "default";
0357 pinctrl-0 = <&pinctrl_sbc_serial1>;
0358 clocks = <&clk_sysin>;
0359
0360 status = "disabled";
0361 };
0362
0363 i2c@9840000 {
0364 compatible = "st,comms-ssc4-i2c";
0365 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
0366 reg = <0x9840000 0x110>;
0367 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
0368 clock-names = "ssc";
0369 clock-frequency = <400000>;
0370 pinctrl-names = "default";
0371 pinctrl-0 = <&pinctrl_i2c0_default>;
0372 #address-cells = <1>;
0373 #size-cells = <0>;
0374
0375 status = "disabled";
0376 };
0377
0378 i2c@9841000 {
0379 compatible = "st,comms-ssc4-i2c";
0380 reg = <0x9841000 0x110>;
0381 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
0382 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
0383 clock-names = "ssc";
0384 clock-frequency = <400000>;
0385 pinctrl-names = "default";
0386 pinctrl-0 = <&pinctrl_i2c1_default>;
0387 #address-cells = <1>;
0388 #size-cells = <0>;
0389
0390 status = "disabled";
0391 };
0392
0393 i2c@9842000 {
0394 compatible = "st,comms-ssc4-i2c";
0395 reg = <0x9842000 0x110>;
0396 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0397 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
0398 clock-names = "ssc";
0399 clock-frequency = <400000>;
0400 pinctrl-names = "default";
0401 pinctrl-0 = <&pinctrl_i2c2_default>;
0402 #address-cells = <1>;
0403 #size-cells = <0>;
0404
0405 status = "disabled";
0406 };
0407
0408 i2c@9843000 {
0409 compatible = "st,comms-ssc4-i2c";
0410 reg = <0x9843000 0x110>;
0411 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
0412 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
0413 clock-names = "ssc";
0414 clock-frequency = <400000>;
0415 pinctrl-names = "default";
0416 pinctrl-0 = <&pinctrl_i2c3_default>;
0417 #address-cells = <1>;
0418 #size-cells = <0>;
0419
0420 status = "disabled";
0421 };
0422
0423 i2c@9844000 {
0424 compatible = "st,comms-ssc4-i2c";
0425 reg = <0x9844000 0x110>;
0426 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
0427 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
0428 clock-names = "ssc";
0429 clock-frequency = <400000>;
0430 pinctrl-names = "default";
0431 pinctrl-0 = <&pinctrl_i2c4_default>;
0432 #address-cells = <1>;
0433 #size-cells = <0>;
0434
0435 status = "disabled";
0436 };
0437
0438 i2c@9845000 {
0439 compatible = "st,comms-ssc4-i2c";
0440 reg = <0x9845000 0x110>;
0441 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
0442 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
0443 clock-names = "ssc";
0444 clock-frequency = <400000>;
0445 pinctrl-names = "default";
0446 pinctrl-0 = <&pinctrl_i2c5_default>;
0447 #address-cells = <1>;
0448 #size-cells = <0>;
0449
0450 status = "disabled";
0451 };
0452
0453
0454 /* SSCs on SBC */
0455 i2c@9540000 {
0456 compatible = "st,comms-ssc4-i2c";
0457 reg = <0x9540000 0x110>;
0458 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
0459 clocks = <&clk_sysin>;
0460 clock-names = "ssc";
0461 clock-frequency = <400000>;
0462 pinctrl-names = "default";
0463 pinctrl-0 = <&pinctrl_i2c10_default>;
0464 #address-cells = <1>;
0465 #size-cells = <0>;
0466
0467 status = "disabled";
0468 };
0469
0470 i2c@9541000 {
0471 compatible = "st,comms-ssc4-i2c";
0472 reg = <0x9541000 0x110>;
0473 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
0474 clocks = <&clk_sysin>;
0475 clock-names = "ssc";
0476 clock-frequency = <400000>;
0477 pinctrl-names = "default";
0478 pinctrl-0 = <&pinctrl_i2c11_default>;
0479 #address-cells = <1>;
0480 #size-cells = <0>;
0481
0482 status = "disabled";
0483 };
0484
0485 spi@9840000 {
0486 compatible = "st,comms-ssc4-spi";
0487 reg = <0x9840000 0x110>;
0488 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
0489 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
0490 clock-names = "ssc";
0491 pinctrl-0 = <&pinctrl_spi0_default>;
0492 pinctrl-names = "default";
0493 #address-cells = <1>;
0494 #size-cells = <0>;
0495
0496 status = "disabled";
0497 };
0498
0499 spi@9841000 {
0500 compatible = "st,comms-ssc4-spi";
0501 reg = <0x9841000 0x110>;
0502 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
0503 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
0504 clock-names = "ssc";
0505 pinctrl-names = "default";
0506 pinctrl-0 = <&pinctrl_spi1_default>;
0507 #address-cells = <1>;
0508 #size-cells = <0>;
0509
0510 status = "disabled";
0511 };
0512
0513 spi@9842000 {
0514 compatible = "st,comms-ssc4-spi";
0515 reg = <0x9842000 0x110>;
0516 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0517 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
0518 clock-names = "ssc";
0519 pinctrl-names = "default";
0520 pinctrl-0 = <&pinctrl_spi2_default>;
0521 #address-cells = <1>;
0522 #size-cells = <0>;
0523
0524 status = "disabled";
0525 };
0526
0527 spi@9843000 {
0528 compatible = "st,comms-ssc4-spi";
0529 reg = <0x9843000 0x110>;
0530 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
0531 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
0532 clock-names = "ssc";
0533 pinctrl-names = "default";
0534 pinctrl-0 = <&pinctrl_spi3_default>;
0535 #address-cells = <1>;
0536 #size-cells = <0>;
0537
0538 status = "disabled";
0539 };
0540
0541 spi@9844000 {
0542 compatible = "st,comms-ssc4-spi";
0543 reg = <0x9844000 0x110>;
0544 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
0545 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
0546 clock-names = "ssc";
0547 pinctrl-names = "default";
0548 pinctrl-0 = <&pinctrl_spi4_default>;
0549 #address-cells = <1>;
0550 #size-cells = <0>;
0551
0552 status = "disabled";
0553 };
0554
0555 /* SBC SSC */
0556 spi@9540000 {
0557 compatible = "st,comms-ssc4-spi";
0558 reg = <0x9540000 0x110>;
0559 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
0560 clocks = <&clk_sysin>;
0561 clock-names = "ssc";
0562 pinctrl-names = "default";
0563 pinctrl-0 = <&pinctrl_spi10_default>;
0564 #address-cells = <1>;
0565 #size-cells = <0>;
0566
0567 status = "disabled";
0568 };
0569
0570 spi@9541000 {
0571 compatible = "st,comms-ssc4-spi";
0572 reg = <0x9541000 0x110>;
0573 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
0574 clocks = <&clk_sysin>;
0575 clock-names = "ssc";
0576 pinctrl-names = "default";
0577 pinctrl-0 = <&pinctrl_spi11_default>;
0578 #address-cells = <1>;
0579 #size-cells = <0>;
0580
0581 status = "disabled";
0582 };
0583
0584 spi@9542000 {
0585 compatible = "st,comms-ssc4-spi";
0586 reg = <0x9542000 0x110>;
0587 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
0588 clocks = <&clk_sysin>;
0589 clock-names = "ssc";
0590 pinctrl-names = "default";
0591 pinctrl-0 = <&pinctrl_spi12_default>;
0592 #address-cells = <1>;
0593 #size-cells = <0>;
0594
0595 status = "disabled";
0596 };
0597
0598 mmc0: sdhci@9060000 {
0599 compatible = "st,sdhci-stih407", "st,sdhci";
0600 status = "disabled";
0601 reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
0602 reg-names = "mmc", "top-mmc-delay";
0603 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
0604 interrupt-names = "mmcirq";
0605 pinctrl-names = "default";
0606 pinctrl-0 = <&pinctrl_mmc0>;
0607 clock-names = "mmc", "icn";
0608 clocks = <&clk_s_c0_flexgen CLK_MMC_0>,
0609 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
0610 bus-width = <8>;
0611 };
0612
0613 mmc1: sdhci@9080000 {
0614 compatible = "st,sdhci-stih407", "st,sdhci";
0615 status = "disabled";
0616 reg = <0x09080000 0x7ff>;
0617 reg-names = "mmc";
0618 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0619 interrupt-names = "mmcirq";
0620 pinctrl-names = "default";
0621 pinctrl-0 = <&pinctrl_sd1>;
0622 clock-names = "mmc", "icn";
0623 clocks = <&clk_s_c0_flexgen CLK_MMC_1>,
0624 <&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
0625 resets = <&softreset STIH407_MMC1_SOFTRESET>;
0626 bus-width = <4>;
0627 };
0628
0629 /* Watchdog and Real-Time Clock */
0630 lpc@8787000 {
0631 compatible = "st,stih407-lpc";
0632 reg = <0x8787000 0x1000>;
0633 interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
0634 clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
0635 timeout-sec = <120>;
0636 st,syscfg = <&syscfg_core>;
0637 st,lpc-mode = <ST_LPC_MODE_WDT>;
0638 };
0639
0640 lpc@8788000 {
0641 compatible = "st,stih407-lpc";
0642 reg = <0x8788000 0x1000>;
0643 interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
0644 clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
0645 st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
0646 };
0647
0648 spifsm: spifsm@9022000{
0649 compatible = "st,spi-fsm";
0650 reg = <0x9022000 0x1000>;
0651 reg-names = "spi-fsm";
0652 clocks = <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
0653 clock-names = "emi_clk";
0654 pinctrl-names = "default";
0655 pinctrl-0 = <&pinctrl_fsm>;
0656 st,syscfg = <&syscfg_core>;
0657 st,boot-device-reg = <0x8c4>;
0658 st,boot-device-spi = <0x68>;
0659
0660 status = "disabled";
0661 };
0662
0663 sata0: sata@9b20000 {
0664 compatible = "st,ahci";
0665 reg = <0x9b20000 0x1000>;
0666
0667 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
0668 interrupt-names = "hostc";
0669
0670 phys = <&phy_port0 PHY_TYPE_SATA>;
0671 phy-names = "ahci_phy";
0672
0673 resets = <&powerdown STIH407_SATA0_POWERDOWN>,
0674 <&softreset STIH407_SATA0_SOFTRESET>,
0675 <&softreset STIH407_SATA0_PWR_SOFTRESET>;
0676 reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
0677
0678 clock-names = "ahci_clk";
0679 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
0680
0681 ports-implemented = <0x1>;
0682
0683 status = "disabled";
0684 };
0685
0686 sata1: sata@9b28000 {
0687 compatible = "st,ahci";
0688 reg = <0x9b28000 0x1000>;
0689
0690 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
0691 interrupt-names = "hostc";
0692
0693 phys = <&phy_port1 PHY_TYPE_SATA>;
0694 phy-names = "ahci_phy";
0695
0696 resets = <&powerdown STIH407_SATA1_POWERDOWN>,
0697 <&softreset STIH407_SATA1_SOFTRESET>,
0698 <&softreset STIH407_SATA1_PWR_SOFTRESET>;
0699 reset-names = "pwr-dwn",
0700 "sw-rst",
0701 "pwr-rst";
0702
0703 clock-names = "ahci_clk";
0704 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
0705
0706 ports-implemented = <0x1>;
0707
0708 status = "disabled";
0709 };
0710
0711
0712 st_dwc3: dwc3@8f94000 {
0713 compatible = "st,stih407-dwc3";
0714 reg = <0x08f94000 0x1000>, <0x110 0x4>;
0715 reg-names = "reg-glue", "syscfg-reg";
0716 st,syscfg = <&syscfg_core>;
0717 resets = <&powerdown STIH407_USB3_POWERDOWN>,
0718 <&softreset STIH407_MIPHY2_SOFTRESET>;
0719 reset-names = "powerdown", "softreset";
0720 #address-cells = <1>;
0721 #size-cells = <1>;
0722 pinctrl-names = "default";
0723 pinctrl-0 = <&pinctrl_usb3>;
0724 ranges;
0725
0726 status = "disabled";
0727
0728 dwc3: usb@9900000 {
0729 compatible = "snps,dwc3";
0730 reg = <0x09900000 0x100000>;
0731 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
0732 dr_mode = "host";
0733 phy-names = "usb2-phy", "usb3-phy";
0734 phys = <&usb2_picophy0>,
0735 <&phy_port2 PHY_TYPE_USB3>;
0736 snps,dis_u3_susphy_quirk;
0737 };
0738 };
0739
0740 /* COMMS PWM Module */
0741 pwm0: pwm@9810000 {
0742 compatible = "st,sti-pwm";
0743 #pwm-cells = <2>;
0744 reg = <0x9810000 0x68>;
0745 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
0746 pinctrl-names = "default";
0747 pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
0748 clock-names = "pwm";
0749 clocks = <&clk_sysin>;
0750 st,pwm-num-chan = <1>;
0751
0752 status = "disabled";
0753 };
0754
0755 /* SBC PWM Module */
0756 pwm1: pwm@9510000 {
0757 compatible = "st,sti-pwm";
0758 #pwm-cells = <2>;
0759 reg = <0x9510000 0x68>;
0760 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
0761 pinctrl-names = "default";
0762 pinctrl-0 = <&pinctrl_pwm1_chan0_default
0763 &pinctrl_pwm1_chan1_default
0764 &pinctrl_pwm1_chan2_default
0765 &pinctrl_pwm1_chan3_default>;
0766 clock-names = "pwm";
0767 clocks = <&clk_sysin>;
0768 st,pwm-num-chan = <4>;
0769
0770 status = "disabled";
0771 };
0772
0773 rng10: rng@8a89000 {
0774 compatible = "st,rng";
0775 reg = <0x08a89000 0x1000>;
0776 clocks = <&clk_sysin>;
0777 status = "okay";
0778 };
0779
0780 rng11: rng@8a8a000 {
0781 compatible = "st,rng";
0782 reg = <0x08a8a000 0x1000>;
0783 clocks = <&clk_sysin>;
0784 status = "okay";
0785 };
0786
0787 ethernet0: dwmac@9630000 {
0788 device_type = "network";
0789 status = "disabled";
0790 compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
0791 reg = <0x9630000 0x8000>, <0x80 0x4>;
0792 reg-names = "stmmaceth", "sti-ethconf";
0793
0794 st,syscon = <&syscfg_sbc_reg 0x80>;
0795 st,gmac_en;
0796 resets = <&softreset STIH407_ETH1_SOFTRESET>;
0797 reset-names = "stmmaceth";
0798
0799 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
0800 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
0801 interrupt-names = "macirq", "eth_wake_irq";
0802
0803 /* DMA Bus Mode */
0804 snps,pbl = <8>;
0805
0806 pinctrl-names = "default";
0807 pinctrl-0 = <&pinctrl_rgmii1>;
0808
0809 clock-names = "stmmaceth", "sti-ethclk";
0810 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
0811 <&clk_s_c0_flexgen CLK_ETH_PHY>;
0812 };
0813
0814 mailbox0: mailbox@8f00000 {
0815 compatible = "st,stih407-mailbox";
0816 reg = <0x8f00000 0x1000>;
0817 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0818 #mbox-cells = <2>;
0819 mbox-name = "a9";
0820 status = "okay";
0821 };
0822
0823 mailbox1: mailbox@8f01000 {
0824 compatible = "st,stih407-mailbox";
0825 reg = <0x8f01000 0x1000>;
0826 #mbox-cells = <2>;
0827 mbox-name = "st231_gp_1";
0828 status = "okay";
0829 };
0830
0831 mailbox2: mailbox@8f02000 {
0832 compatible = "st,stih407-mailbox";
0833 reg = <0x8f02000 0x1000>;
0834 #mbox-cells = <2>;
0835 mbox-name = "st231_gp_0";
0836 status = "okay";
0837 };
0838
0839 mailbox3: mailbox@8f03000 {
0840 compatible = "st,stih407-mailbox";
0841 reg = <0x8f03000 0x1000>;
0842 #mbox-cells = <2>;
0843 mbox-name = "st231_audio_video";
0844 status = "okay";
0845 };
0846
0847 /* fdma audio */
0848 fdma0: dma-controller@8e20000 {
0849 compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
0850 reg = <0x8e20000 0x8000>,
0851 <0x8e30000 0x3000>,
0852 <0x8e37000 0x1000>,
0853 <0x8e38000 0x8000>;
0854 reg-names = "slimcore", "dmem", "peripherals", "imem";
0855 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
0856 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
0857 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
0858 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
0859 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
0860 dma-channels = <16>;
0861 #dma-cells = <3>;
0862 };
0863
0864 /* fdma app */
0865 fdma1: dma-controller@8e40000 {
0866 compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc";
0867 reg = <0x8e40000 0x8000>,
0868 <0x8e50000 0x3000>,
0869 <0x8e57000 0x1000>,
0870 <0x8e58000 0x8000>;
0871 reg-names = "slimcore", "dmem", "peripherals", "imem";
0872 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
0873 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
0874 <&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
0875 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
0876
0877 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0878 dma-channels = <16>;
0879 #dma-cells = <3>;
0880
0881 status = "disabled";
0882 };
0883
0884 /* fdma free running */
0885 fdma2: dma-controller@8e60000 {
0886 compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc";
0887 reg = <0x8e60000 0x8000>,
0888 <0x8e70000 0x3000>,
0889 <0x8e77000 0x1000>,
0890 <0x8e78000 0x8000>;
0891 reg-names = "slimcore", "dmem", "peripherals", "imem";
0892 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
0893 dma-channels = <16>;
0894 #dma-cells = <3>;
0895 clocks = <&clk_s_c0_flexgen CLK_FDMA>,
0896 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
0897 <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
0898 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
0899
0900 status = "disabled";
0901 };
0902
0903 sti_uni_player0: sti-uni-player@8d80000 {
0904 compatible = "st,stih407-uni-player-hdmi";
0905 #sound-dai-cells = <0>;
0906 st,syscfg = <&syscfg_core>;
0907 clocks = <&clk_s_d0_flexgen CLK_PCM_0>;
0908 assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>;
0909 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>;
0910 assigned-clock-rates = <50000000>;
0911 reg = <0x8d80000 0x158>;
0912 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0913 dmas = <&fdma0 2 0 1>;
0914 dma-names = "tx";
0915
0916 status = "disabled";
0917 };
0918
0919 sti_uni_player1: sti-uni-player@8d81000 {
0920 compatible = "st,stih407-uni-player-pcm-out";
0921 #sound-dai-cells = <0>;
0922 st,syscfg = <&syscfg_core>;
0923 clocks = <&clk_s_d0_flexgen CLK_PCM_1>;
0924 assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>;
0925 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>;
0926 assigned-clock-rates = <50000000>;
0927 reg = <0x8d81000 0x158>;
0928 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
0929 dmas = <&fdma0 3 0 1>;
0930 dma-names = "tx";
0931
0932 status = "disabled";
0933 };
0934
0935 sti_uni_player2: sti-uni-player@8d82000 {
0936 compatible = "st,stih407-uni-player-dac";
0937 #sound-dai-cells = <0>;
0938 st,syscfg = <&syscfg_core>;
0939 clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
0940 assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>;
0941 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>;
0942 assigned-clock-rates = <50000000>;
0943 reg = <0x8d82000 0x158>;
0944 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
0945 dmas = <&fdma0 4 0 1>;
0946 dma-names = "tx";
0947
0948 status = "disabled";
0949 };
0950
0951 sti_uni_player3: sti-uni-player@8d85000 {
0952 compatible = "st,stih407-uni-player-spdif";
0953 #sound-dai-cells = <0>;
0954 st,syscfg = <&syscfg_core>;
0955 clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
0956 assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>;
0957 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>;
0958 assigned-clock-rates = <50000000>;
0959 reg = <0x8d85000 0x158>;
0960 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0961 dmas = <&fdma0 7 0 1>;
0962 dma-names = "tx";
0963
0964 status = "disabled";
0965 };
0966
0967 sti_uni_reader0: sti-uni-reader@8d83000 {
0968 compatible = "st,stih407-uni-reader-pcm_in";
0969 #sound-dai-cells = <0>;
0970 st,syscfg = <&syscfg_core>;
0971 reg = <0x8d83000 0x158>;
0972 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
0973 dmas = <&fdma0 5 0 1>;
0974 dma-names = "rx";
0975
0976 status = "disabled";
0977 };
0978
0979 sti_uni_reader1: sti-uni-reader@8d84000 {
0980 compatible = "st,stih407-uni-reader-hdmi";
0981 #sound-dai-cells = <0>;
0982 st,syscfg = <&syscfg_core>;
0983 reg = <0x8d84000 0x158>;
0984 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
0985 dmas = <&fdma0 6 0 1>;
0986 dma-names = "rx";
0987
0988 status = "disabled";
0989 };
0990 };
0991 };
