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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2014 STMicroelectronics R&D Limited
0004 */
0005 #include <dt-bindings/clock/stih407-clks.h>
0006 / {
0007 /*
0008 * Fixed 30MHz oscillator inputs to SoC
0009 */
0010 clk_sysin: clk-sysin {
0011 #clock-cells = <0>;
0012 compatible = "fixed-clock";
0013 clock-frequency = <30000000>;
0014 };
0015
0016 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
0017 #clock-cells = <0>;
0018 compatible = "fixed-clock";
0019 clock-frequency = <0>;
0020 };
0021
0022 clocks {
0023 #address-cells = <1>;
0024 #size-cells = <1>;
0025 ranges;
0026
0027 /*
0028 * A9 PLL.
0029 */
0030 clockgen-a9@92b0000 {
0031 compatible = "st,clkgen-c32";
0032 reg = <0x92b0000 0x10000>;
0033
0034 clockgen_a9_pll: clockgen-a9-pll {
0035 #clock-cells = <1>;
0036 compatible = "st,stih407-clkgen-plla9";
0037
0038 clocks = <&clk_sysin>;
0039 };
0040
0041 clk_m_a9: clk-m-a9 {
0042 #clock-cells = <0>;
0043 compatible = "st,stih407-clkgen-a9-mux";
0044
0045 clocks = <&clockgen_a9_pll 0>,
0046 <&clockgen_a9_pll 0>,
0047 <&clk_s_c0_flexgen 13>,
0048 <&clk_m_a9_ext2f_div2>;
0049
0050 /*
0051 * ARM Peripheral clock for timers
0052 */
0053 arm_periph_clk: clk-m-a9-periphs {
0054 #clock-cells = <0>;
0055 compatible = "fixed-factor-clock";
0056
0057 clocks = <&clk_m_a9>;
0058 clock-div = <2>;
0059 clock-mult = <1>;
0060 };
0061 };
0062 };
0063
0064 clockgen-a@90ff000 {
0065 compatible = "st,clkgen-c32";
0066 reg = <0x90ff000 0x1000>;
0067
0068 clk_s_a0_pll: clk-s-a0-pll {
0069 #clock-cells = <1>;
0070 compatible = "st,clkgen-pll0-a0";
0071
0072 clocks = <&clk_sysin>;
0073 };
0074
0075 clk_s_a0_flexgen: clk-s-a0-flexgen {
0076 compatible = "st,flexgen", "st,flexgen-stih407-a0";
0077
0078 #clock-cells = <1>;
0079
0080 clocks = <&clk_s_a0_pll 0>,
0081 <&clk_sysin>;
0082 };
0083 };
0084
0085 clk_s_c0: clockgen-c@9103000 {
0086 compatible = "st,clkgen-c32";
0087 reg = <0x9103000 0x1000>;
0088
0089 clk_s_c0_pll0: clk-s-c0-pll0 {
0090 #clock-cells = <1>;
0091 compatible = "st,clkgen-pll0-c0";
0092
0093 clocks = <&clk_sysin>;
0094 };
0095
0096 clk_s_c0_pll1: clk-s-c0-pll1 {
0097 #clock-cells = <1>;
0098 compatible = "st,clkgen-pll1-c0";
0099
0100 clocks = <&clk_sysin>;
0101 };
0102
0103 clk_s_c0_quadfs: clk-s-c0-quadfs {
0104 #clock-cells = <1>;
0105 compatible = "st,quadfs-pll";
0106
0107 clocks = <&clk_sysin>;
0108 };
0109
0110 clk_s_c0_flexgen: clk-s-c0-flexgen {
0111 #clock-cells = <1>;
0112 compatible = "st,flexgen", "st,flexgen-stih407-c0";
0113
0114 clocks = <&clk_s_c0_pll0 0>,
0115 <&clk_s_c0_pll1 0>,
0116 <&clk_s_c0_quadfs 0>,
0117 <&clk_s_c0_quadfs 1>,
0118 <&clk_s_c0_quadfs 2>,
0119 <&clk_s_c0_quadfs 3>,
0120 <&clk_sysin>;
0121
0122 /*
0123 * ARM Peripheral clock for timers
0124 */
0125 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
0126 #clock-cells = <0>;
0127 compatible = "fixed-factor-clock";
0128
0129 clocks = <&clk_s_c0_flexgen 13>;
0130
0131 clock-output-names = "clk-m-a9-ext2f-div2";
0132
0133 clock-div = <2>;
0134 clock-mult = <1>;
0135 };
0136 };
0137 };
0138
0139 clockgen-d0@9104000 {
0140 compatible = "st,clkgen-c32";
0141 reg = <0x9104000 0x1000>;
0142
0143 clk_s_d0_quadfs: clk-s-d0-quadfs {
0144 #clock-cells = <1>;
0145 compatible = "st,quadfs-d0";
0146
0147 clocks = <&clk_sysin>;
0148 };
0149
0150 clk_s_d0_flexgen: clk-s-d0-flexgen {
0151 #clock-cells = <1>;
0152 compatible = "st,flexgen", "st,flexgen-stih407-d0";
0153
0154 clocks = <&clk_s_d0_quadfs 0>,
0155 <&clk_s_d0_quadfs 1>,
0156 <&clk_s_d0_quadfs 2>,
0157 <&clk_s_d0_quadfs 3>,
0158 <&clk_sysin>;
0159 };
0160 };
0161
0162 clockgen-d2@9106000 {
0163 compatible = "st,clkgen-c32";
0164 reg = <0x9106000 0x1000>;
0165
0166 clk_s_d2_quadfs: clk-s-d2-quadfs {
0167 #clock-cells = <1>;
0168 compatible = "st,quadfs-d2";
0169
0170 clocks = <&clk_sysin>;
0171 };
0172
0173 clk_s_d2_flexgen: clk-s-d2-flexgen {
0174 #clock-cells = <1>;
0175 compatible = "st,flexgen", "st,flexgen-stih407-d2";
0176
0177 clocks = <&clk_s_d2_quadfs 0>,
0178 <&clk_s_d2_quadfs 1>,
0179 <&clk_s_d2_quadfs 2>,
0180 <&clk_s_d2_quadfs 3>,
0181 <&clk_sysin>,
0182 <&clk_sysin>,
0183 <&clk_tmdsout_hdmi>;
0184 };
0185 };
0186
0187 clockgen-d3@9107000 {
0188 compatible = "st,clkgen-c32";
0189 reg = <0x9107000 0x1000>;
0190
0191 clk_s_d3_quadfs: clk-s-d3-quadfs {
0192 #clock-cells = <1>;
0193 compatible = "st,quadfs-d3";
0194
0195 clocks = <&clk_sysin>;
0196 };
0197
0198 clk_s_d3_flexgen: clk-s-d3-flexgen {
0199 #clock-cells = <1>;
0200 compatible = "st,flexgen", "st,flexgen-stih407-d3";
0201
0202 clocks = <&clk_s_d3_quadfs 0>,
0203 <&clk_s_d3_quadfs 1>,
0204 <&clk_s_d3_quadfs 2>,
0205 <&clk_s_d3_quadfs 3>,
0206 <&clk_sysin>;
0207 };
0208 };
0209 };
0210 };
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