0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 * Copyright 2012 Linaro Ltd
0004 */
0005
0006 #include <dt-bindings/interrupt-controller/irq.h>
0007 #include <dt-bindings/interrupt-controller/arm-gic.h>
0008 #include <dt-bindings/reset/stericsson,db8500-prcc-reset.h>
0009 #include <dt-bindings/mfd/dbx500-prcmu.h>
0010 #include <dt-bindings/arm/ux500_pm_domains.h>
0011 #include <dt-bindings/gpio/gpio.h>
0012 #include <dt-bindings/thermal/thermal.h>
0013
0014 / {
0015 #address-cells = <1>;
0016 #size-cells = <1>;
0017
0018 /* This stablilizes the device enumeration */
0019 aliases {
0020 i2c0 = &i2c0;
0021 i2c1 = &i2c1;
0022 i2c2 = &i2c2;
0023 i2c3 = &i2c3;
0024 i2c4 = &i2c4;
0025 spi0 = &spi0;
0026 spi1 = &spi1;
0027 spi2 = &spi2;
0028 spi3 = &spi3;
0029 serial0 = &serial0;
0030 serial1 = &serial1;
0031 serial2 = &serial2;
0032 };
0033
0034 chosen {
0035 };
0036
0037 cpus {
0038 #address-cells = <1>;
0039 #size-cells = <0>;
0040 enable-method = "ste,dbx500-smp";
0041
0042 cpu-map {
0043 cluster0 {
0044 core0 {
0045 cpu = <&CPU0>;
0046 };
0047 core1 {
0048 cpu = <&CPU1>;
0049 };
0050 };
0051 };
0052 CPU0: cpu@300 {
0053 device_type = "cpu";
0054 compatible = "arm,cortex-a9";
0055 reg = <0x300>;
0056 clocks = <&prcmu_clk PRCMU_ARMSS>;
0057 clock-names = "cpu";
0058 clock-latency = <20000>;
0059 #cooling-cells = <2>;
0060 };
0061 CPU1: cpu@301 {
0062 device_type = "cpu";
0063 compatible = "arm,cortex-a9";
0064 reg = <0x301>;
0065 };
0066 };
0067
0068 thermal-zones {
0069 /*
0070 * Thermal zone for the SoC, using the thermal sensor in the
0071 * PRCMU for temperature and the cpufreq driver for passive
0072 * cooling.
0073 */
0074 cpu_thermal: cpu-thermal {
0075 polling-delay-passive = <250>;
0076 /*
0077 * This sensor fires interrupts to update the thermal
0078 * zone, so no polling is needed.
0079 */
0080 polling-delay = <0>;
0081
0082 thermal-sensors = <&thermal>;
0083
0084 trips {
0085 cpu_alert: cpu-alert {
0086 temperature = <70000>;
0087 hysteresis = <2000>;
0088 type = "passive";
0089 };
0090 cpu-crit {
0091 temperature = <85000>;
0092 hysteresis = <0>;
0093 type = "critical";
0094 };
0095 };
0096
0097 cooling-maps {
0098 trip = <&cpu_alert>;
0099 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
0100 contribution = <100>;
0101 };
0102 };
0103 };
0104
0105 soc {
0106 #address-cells = <1>;
0107 #size-cells = <1>;
0108 compatible = "stericsson,db8500", "simple-bus";
0109 interrupt-parent = <&intc>;
0110 ranges;
0111
0112 ptm@801ae000 {
0113 compatible = "arm,coresight-etm3x", "arm,primecell";
0114 reg = <0x801ae000 0x1000>;
0115
0116 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
0117 clock-names = "apb_pclk", "atclk";
0118 cpu = <&CPU0>;
0119 out-ports {
0120 port {
0121 ptm0_out_port: endpoint {
0122 remote-endpoint = <&funnel_in_port0>;
0123 };
0124 };
0125 };
0126 };
0127
0128 ptm@801af000 {
0129 compatible = "arm,coresight-etm3x", "arm,primecell";
0130 reg = <0x801af000 0x1000>;
0131
0132 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
0133 clock-names = "apb_pclk", "atclk";
0134 cpu = <&CPU1>;
0135 out-ports {
0136 port {
0137 ptm1_out_port: endpoint {
0138 remote-endpoint = <&funnel_in_port1>;
0139 };
0140 };
0141 };
0142 };
0143
0144 funnel@801a6000 {
0145 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
0146 reg = <0x801a6000 0x1000>;
0147
0148 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
0149 clock-names = "apb_pclk", "atclk";
0150 out-ports {
0151 port {
0152 funnel_out_port: endpoint {
0153 remote-endpoint =
0154 <&replicator_in_port0>;
0155 };
0156 };
0157 };
0158
0159 in-ports {
0160 #address-cells = <1>;
0161 #size-cells = <0>;
0162
0163 port@0 {
0164 reg = <0>;
0165 funnel_in_port0: endpoint {
0166 remote-endpoint = <&ptm0_out_port>;
0167 };
0168 };
0169
0170 port@1 {
0171 reg = <1>;
0172 funnel_in_port1: endpoint {
0173 remote-endpoint = <&ptm1_out_port>;
0174 };
0175 };
0176 };
0177 };
0178
0179 replicator {
0180 compatible = "arm,coresight-static-replicator";
0181 clocks = <&prcmu_clk PRCMU_APEATCLK>;
0182 clock-names = "atclk";
0183
0184 out-ports {
0185 #address-cells = <1>;
0186 #size-cells = <0>;
0187
0188 port@0 {
0189 reg = <0>;
0190 replicator_out_port0: endpoint {
0191 remote-endpoint = <&tpiu_in_port>;
0192 };
0193 };
0194 port@1 {
0195 reg = <1>;
0196 replicator_out_port1: endpoint {
0197 remote-endpoint = <&etb_in_port>;
0198 };
0199 };
0200 };
0201
0202 in-ports {
0203 port {
0204 replicator_in_port0: endpoint {
0205 remote-endpoint = <&funnel_out_port>;
0206 };
0207 };
0208 };
0209 };
0210
0211 tpiu@80190000 {
0212 compatible = "arm,coresight-tpiu", "arm,primecell";
0213 reg = <0x80190000 0x1000>;
0214
0215 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
0216 clock-names = "apb_pclk", "atclk";
0217 in-ports {
0218 port {
0219 tpiu_in_port: endpoint {
0220 remote-endpoint = <&replicator_out_port0>;
0221 };
0222 };
0223 };
0224 };
0225
0226 etb@801a4000 {
0227 compatible = "arm,coresight-etb10", "arm,primecell";
0228 reg = <0x801a4000 0x1000>;
0229
0230 clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;
0231 clock-names = "apb_pclk", "atclk";
0232 in-ports {
0233 port {
0234 etb_in_port: endpoint {
0235 remote-endpoint = <&replicator_out_port1>;
0236 };
0237 };
0238 };
0239 };
0240
0241 intc: interrupt-controller@a0411000 {
0242 compatible = "arm,cortex-a9-gic";
0243 #interrupt-cells = <3>;
0244 #address-cells = <1>;
0245 interrupt-controller;
0246 reg = <0xa0411000 0x1000>,
0247 <0xa0410100 0x100>;
0248 };
0249
0250 scu@a0410000 {
0251 compatible = "arm,cortex-a9-scu";
0252 reg = <0xa0410000 0x100>;
0253 };
0254
0255 /*
0256 * The backup RAM is used for retention during sleep
0257 * and various things like spin tables
0258 */
0259 backupram@80150000 {
0260 compatible = "ste,dbx500-backupram";
0261 reg = <0x80150000 0x2000>;
0262 };
0263
0264 L2: cache-controller {
0265 compatible = "arm,pl310-cache";
0266 reg = <0xa0412000 0x1000>;
0267 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0268 cache-unified;
0269 cache-level = <2>;
0270 };
0271
0272 pmu {
0273 compatible = "arm,cortex-a9-pmu";
0274 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0275 };
0276
0277 pm_domains: pm_domains0 {
0278 compatible = "stericsson,ux500-pm-domains";
0279 #power-domain-cells = <1>;
0280 };
0281
0282 clocks {
0283 compatible = "stericsson,u8500-clks";
0284 /*
0285 * Registers for the CLKRST block on peripheral
0286 * groups 1, 2, 3, 5, 6,
0287 */
0288 reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
0289 <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
0290 <0xa03cf000 0x1000>;
0291
0292 prcmu_clk: prcmu-clock {
0293 #clock-cells = <1>;
0294 };
0295
0296 prcc_pclk: prcc-periph-clock {
0297 #clock-cells = <2>;
0298 };
0299
0300 prcc_kclk: prcc-kernel-clock {
0301 #clock-cells = <2>;
0302 };
0303
0304 prcc_reset: prcc-reset-controller {
0305 #reset-cells = <2>;
0306 };
0307
0308 rtc_clk: rtc32k-clock {
0309 #clock-cells = <0>;
0310 };
0311
0312 smp_twd_clk: smp-twd-clock {
0313 #clock-cells = <0>;
0314 };
0315 };
0316
0317 mtu@a03c6000 {
0318 /* Nomadik System Timer */
0319 compatible = "st,nomadik-mtu";
0320 reg = <0xa03c6000 0x1000>;
0321 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
0322
0323 clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
0324 clock-names = "timclk", "apb_pclk";
0325 };
0326
0327 timer@a0410600 {
0328 compatible = "arm,cortex-a9-twd-timer";
0329 reg = <0xa0410600 0x20>;
0330 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
0331
0332 clocks = <&smp_twd_clk>;
0333 };
0334
0335 watchdog@a0410620 {
0336 compatible = "arm,cortex-a9-twd-wdt";
0337 reg = <0xa0410620 0x20>;
0338 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
0339 clocks = <&smp_twd_clk>;
0340 };
0341
0342 rtc@80154000 {
0343 compatible = "arm,pl031", "arm,primecell";
0344 reg = <0x80154000 0x1000>;
0345 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
0346
0347 clocks = <&rtc_clk>;
0348 clock-names = "apb_pclk";
0349 };
0350
0351 gpio0: gpio@8012e000 {
0352 compatible = "stericsson,db8500-gpio",
0353 "st,nomadik-gpio";
0354 reg = <0x8012e000 0x80>;
0355 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
0356 interrupt-controller;
0357 #interrupt-cells = <2>;
0358 st,supports-sleepmode;
0359 gpio-controller;
0360 #gpio-cells = <2>;
0361 gpio-bank = <0>;
0362 gpio-ranges = <&pinctrl 0 0 32>;
0363 clocks = <&prcc_pclk 1 9>;
0364 };
0365
0366 gpio1: gpio@8012e080 {
0367 compatible = "stericsson,db8500-gpio",
0368 "st,nomadik-gpio";
0369 reg = <0x8012e080 0x80>;
0370 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
0371 interrupt-controller;
0372 #interrupt-cells = <2>;
0373 st,supports-sleepmode;
0374 gpio-controller;
0375 #gpio-cells = <2>;
0376 gpio-bank = <1>;
0377 gpio-ranges = <&pinctrl 0 32 5>;
0378 clocks = <&prcc_pclk 1 9>;
0379 };
0380
0381 gpio2: gpio@8000e000 {
0382 compatible = "stericsson,db8500-gpio",
0383 "st,nomadik-gpio";
0384 reg = <0x8000e000 0x80>;
0385 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
0386 interrupt-controller;
0387 #interrupt-cells = <2>;
0388 st,supports-sleepmode;
0389 gpio-controller;
0390 #gpio-cells = <2>;
0391 gpio-bank = <2>;
0392 gpio-ranges = <&pinctrl 0 64 32>;
0393 clocks = <&prcc_pclk 3 8>;
0394 };
0395
0396 gpio3: gpio@8000e080 {
0397 compatible = "stericsson,db8500-gpio",
0398 "st,nomadik-gpio";
0399 reg = <0x8000e080 0x80>;
0400 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
0401 interrupt-controller;
0402 #interrupt-cells = <2>;
0403 st,supports-sleepmode;
0404 gpio-controller;
0405 #gpio-cells = <2>;
0406 gpio-bank = <3>;
0407 gpio-ranges = <&pinctrl 0 96 2>;
0408 clocks = <&prcc_pclk 3 8>;
0409 };
0410
0411 gpio4: gpio@8000e100 {
0412 compatible = "stericsson,db8500-gpio",
0413 "st,nomadik-gpio";
0414 reg = <0x8000e100 0x80>;
0415 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
0416 interrupt-controller;
0417 #interrupt-cells = <2>;
0418 st,supports-sleepmode;
0419 gpio-controller;
0420 #gpio-cells = <2>;
0421 gpio-bank = <4>;
0422 gpio-ranges = <&pinctrl 0 128 32>;
0423 clocks = <&prcc_pclk 3 8>;
0424 };
0425
0426 gpio5: gpio@8000e180 {
0427 compatible = "stericsson,db8500-gpio",
0428 "st,nomadik-gpio";
0429 reg = <0x8000e180 0x80>;
0430 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
0431 interrupt-controller;
0432 #interrupt-cells = <2>;
0433 st,supports-sleepmode;
0434 gpio-controller;
0435 #gpio-cells = <2>;
0436 gpio-bank = <5>;
0437 gpio-ranges = <&pinctrl 0 160 12>;
0438 clocks = <&prcc_pclk 3 8>;
0439 };
0440
0441 gpio6: gpio@8011e000 {
0442 compatible = "stericsson,db8500-gpio",
0443 "st,nomadik-gpio";
0444 reg = <0x8011e000 0x80>;
0445 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
0446 interrupt-controller;
0447 #interrupt-cells = <2>;
0448 st,supports-sleepmode;
0449 gpio-controller;
0450 #gpio-cells = <2>;
0451 gpio-bank = <6>;
0452 gpio-ranges = <&pinctrl 0 192 32>;
0453 clocks = <&prcc_pclk 2 11>;
0454 };
0455
0456 gpio7: gpio@8011e080 {
0457 compatible = "stericsson,db8500-gpio",
0458 "st,nomadik-gpio";
0459 reg = <0x8011e080 0x80>;
0460 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
0461 interrupt-controller;
0462 #interrupt-cells = <2>;
0463 st,supports-sleepmode;
0464 gpio-controller;
0465 #gpio-cells = <2>;
0466 gpio-bank = <7>;
0467 gpio-ranges = <&pinctrl 0 224 7>;
0468 clocks = <&prcc_pclk 2 11>;
0469 };
0470
0471 gpio8: gpio@a03fe000 {
0472 compatible = "stericsson,db8500-gpio",
0473 "st,nomadik-gpio";
0474 reg = <0xa03fe000 0x80>;
0475 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
0476 interrupt-controller;
0477 #interrupt-cells = <2>;
0478 st,supports-sleepmode;
0479 gpio-controller;
0480 #gpio-cells = <2>;
0481 gpio-bank = <8>;
0482 gpio-ranges = <&pinctrl 0 256 12>;
0483 clocks = <&prcc_pclk 5 1>;
0484 };
0485
0486 pinctrl: pinctrl {
0487 compatible = "stericsson,db8500-pinctrl";
0488 nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>,
0489 <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>,
0490 <&gpio8>;
0491 prcm = <&prcmu>;
0492 };
0493
0494 usb_per5@a03e0000 {
0495 compatible = "stericsson,db8500-musb";
0496 reg = <0xa03e0000 0x10000>;
0497 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0498 interrupt-names = "mc";
0499
0500 dr_mode = "otg";
0501
0502 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
0503 <&dma 38 0 0x0>, /* Logical - MemToDev */
0504 <&dma 37 0 0x2>, /* Logical - DevToMem */
0505 <&dma 37 0 0x0>, /* Logical - MemToDev */
0506 <&dma 36 0 0x2>, /* Logical - DevToMem */
0507 <&dma 36 0 0x0>, /* Logical - MemToDev */
0508 <&dma 19 0 0x2>, /* Logical - DevToMem */
0509 <&dma 19 0 0x0>, /* Logical - MemToDev */
0510 <&dma 18 0 0x2>, /* Logical - DevToMem */
0511 <&dma 18 0 0x0>, /* Logical - MemToDev */
0512 <&dma 17 0 0x2>, /* Logical - DevToMem */
0513 <&dma 17 0 0x0>, /* Logical - MemToDev */
0514 <&dma 16 0 0x2>, /* Logical - DevToMem */
0515 <&dma 16 0 0x0>, /* Logical - MemToDev */
0516 <&dma 39 0 0x2>, /* Logical - DevToMem */
0517 <&dma 39 0 0x0>; /* Logical - MemToDev */
0518
0519 dma-names = "iep_1_9", "oep_1_9",
0520 "iep_2_10", "oep_2_10",
0521 "iep_3_11", "oep_3_11",
0522 "iep_4_12", "oep_4_12",
0523 "iep_5_13", "oep_5_13",
0524 "iep_6_14", "oep_6_14",
0525 "iep_7_15", "oep_7_15",
0526 "iep_8", "oep_8";
0527
0528 clocks = <&prcc_pclk 5 0>;
0529 };
0530
0531 dma: dma-controller@801C0000 {
0532 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
0533 reg = <0x801C0000 0x1000 0x40010000 0x800>;
0534 reg-names = "base", "lcpa";
0535 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
0536
0537 #dma-cells = <3>;
0538 memcpy-channels = <56 57 58 59 60>;
0539
0540 clocks = <&prcmu_clk PRCMU_DMACLK>;
0541 };
0542
0543 prcmu: prcmu@80157000 {
0544 compatible = "stericsson,db8500-prcmu", "syscon";
0545 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
0546 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
0547 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
0548 #address-cells = <1>;
0549 #size-cells = <1>;
0550 interrupt-controller;
0551 #interrupt-cells = <2>;
0552 ranges;
0553
0554 prcmu-timer-4@80157450 {
0555 compatible = "stericsson,db8500-prcmu-timer-4";
0556 reg = <0x80157450 0xC>;
0557 };
0558
0559 thermal: thermal@801573c0 {
0560 compatible = "stericsson,db8500-thermal";
0561 reg = <0x801573c0 0x40>;
0562 interrupt-parent = <&prcmu>;
0563 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
0564 <22 IRQ_TYPE_LEVEL_HIGH>;
0565 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
0566 #thermal-sensor-cells = <0>;
0567 };
0568
0569 db8500-prcmu-regulators {
0570 compatible = "stericsson,db8500-prcmu-regulator";
0571
0572 // DB8500_REGULATOR_VAPE
0573 db8500_vape_reg: db8500_vape {
0574 regulator-always-on;
0575 };
0576
0577 // DB8500_REGULATOR_VARM
0578 db8500_varm_reg: db8500_varm {
0579 };
0580
0581 // DB8500_REGULATOR_VMODEM
0582 db8500_vmodem_reg: db8500_vmodem {
0583 };
0584
0585 // DB8500_REGULATOR_VPLL
0586 db8500_vpll_reg: db8500_vpll {
0587 };
0588
0589 // DB8500_REGULATOR_VSMPS1
0590 db8500_vsmps1_reg: db8500_vsmps1 {
0591 };
0592
0593 // DB8500_REGULATOR_VSMPS2
0594 db8500_vsmps2_reg: db8500_vsmps2 {
0595 };
0596
0597 // DB8500_REGULATOR_VSMPS3
0598 db8500_vsmps3_reg: db8500_vsmps3 {
0599 };
0600
0601 // DB8500_REGULATOR_VRF1
0602 db8500_vrf1_reg: db8500_vrf1 {
0603 };
0604
0605 // DB8500_REGULATOR_SWITCH_SVAMMDSP
0606 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
0607 };
0608
0609 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
0610 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
0611 };
0612
0613 // DB8500_REGULATOR_SWITCH_SVAPIPE
0614 db8500_sva_pipe_reg: db8500_sva_pipe {
0615 };
0616
0617 // DB8500_REGULATOR_SWITCH_SIAMMDSP
0618 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
0619 };
0620
0621 // DB8500_REGULATOR_SWITCH_SIAMMDSPRET
0622 db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
0623 };
0624
0625 // DB8500_REGULATOR_SWITCH_SIAPIPE
0626 db8500_sia_pipe_reg: db8500_sia_pipe {
0627 };
0628
0629 // DB8500_REGULATOR_SWITCH_SGA
0630 db8500_sga_reg: db8500_sga {
0631 vin-supply = <&db8500_vape_reg>;
0632 };
0633
0634 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
0635 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
0636 vin-supply = <&db8500_vape_reg>;
0637 };
0638
0639 // DB8500_REGULATOR_SWITCH_ESRAM12
0640 db8500_esram12_reg: db8500_esram12 {
0641 };
0642
0643 // DB8500_REGULATOR_SWITCH_ESRAM12RET
0644 db8500_esram12_ret_reg: db8500_esram12_ret {
0645 };
0646
0647 // DB8500_REGULATOR_SWITCH_ESRAM34
0648 db8500_esram34_reg: db8500_esram34 {
0649 };
0650
0651 // DB8500_REGULATOR_SWITCH_ESRAM34RET
0652 db8500_esram34_ret_reg: db8500_esram34_ret {
0653 };
0654 };
0655 };
0656
0657 i2c0: i2c@80004000 {
0658 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
0659 reg = <0x80004000 0x1000>;
0660 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
0661
0662 #address-cells = <1>;
0663 #size-cells = <0>;
0664
0665 clock-frequency = <400000>;
0666 clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
0667 clock-names = "i2cclk", "apb_pclk";
0668 power-domains = <&pm_domains DOMAIN_VAPE>;
0669 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_I2C0>;
0670
0671 status = "disabled";
0672 };
0673
0674 i2c1: i2c@80122000 {
0675 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
0676 reg = <0x80122000 0x1000>;
0677 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0678
0679 #address-cells = <1>;
0680 #size-cells = <0>;
0681
0682 clock-frequency = <400000>;
0683
0684 clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
0685 clock-names = "i2cclk", "apb_pclk";
0686 power-domains = <&pm_domains DOMAIN_VAPE>;
0687 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C1>;
0688
0689 status = "disabled";
0690 };
0691
0692 i2c2: i2c@80128000 {
0693 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
0694 reg = <0x80128000 0x1000>;
0695 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
0696
0697 #address-cells = <1>;
0698 #size-cells = <0>;
0699
0700 clock-frequency = <400000>;
0701
0702 clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
0703 clock-names = "i2cclk", "apb_pclk";
0704 power-domains = <&pm_domains DOMAIN_VAPE>;
0705 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C2>;
0706
0707 status = "disabled";
0708 };
0709
0710 i2c3: i2c@80110000 {
0711 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
0712 reg = <0x80110000 0x1000>;
0713 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0714
0715 #address-cells = <1>;
0716 #size-cells = <0>;
0717
0718 clock-frequency = <400000>;
0719
0720 clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
0721 clock-names = "i2cclk", "apb_pclk";
0722 power-domains = <&pm_domains DOMAIN_VAPE>;
0723 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_I2C3>;
0724
0725 status = "disabled";
0726 };
0727
0728 i2c4: i2c@8012a000 {
0729 compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
0730 reg = <0x8012a000 0x1000>;
0731 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
0732
0733 #address-cells = <1>;
0734 #size-cells = <0>;
0735
0736 clock-frequency = <400000>;
0737
0738 clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
0739 clock-names = "i2cclk", "apb_pclk";
0740 power-domains = <&pm_domains DOMAIN_VAPE>;
0741 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_I2C4>;
0742
0743 status = "disabled";
0744 };
0745
0746 ssp0: spi@80002000 {
0747 compatible = "arm,pl022", "arm,primecell";
0748 reg = <0x80002000 0x1000>;
0749 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
0750 #address-cells = <1>;
0751 #size-cells = <0>;
0752 clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
0753 clock-names = "sspclk", "apb_pclk";
0754 dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
0755 <&dma 8 0 0x0>; /* Logical - MemToDev */
0756 dma-names = "rx", "tx";
0757 power-domains = <&pm_domains DOMAIN_VAPE>;
0758 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP0>;
0759
0760 status = "disabled";
0761 };
0762
0763 ssp1: spi@80003000 {
0764 compatible = "arm,pl022", "arm,primecell";
0765 reg = <0x80003000 0x1000>;
0766 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
0767 #address-cells = <1>;
0768 #size-cells = <0>;
0769 clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
0770 clock-names = "sspclk", "apb_pclk";
0771 dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
0772 <&dma 9 0 0x0>; /* Logical - MemToDev */
0773 dma-names = "rx", "tx";
0774 power-domains = <&pm_domains DOMAIN_VAPE>;
0775 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SSP1>;
0776
0777 status = "disabled";
0778 };
0779
0780 spi0: spi@8011a000 {
0781 compatible = "arm,pl022", "arm,primecell";
0782 reg = <0x8011a000 0x1000>;
0783 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0784 #address-cells = <1>;
0785 #size-cells = <0>;
0786 /* Same clock wired to kernel and pclk */
0787 clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
0788 clock-names = "sspclk", "apb_pclk";
0789 dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
0790 <&dma 0 0 0x0>; /* Logical - MemToDev */
0791 dma-names = "rx", "tx";
0792 power-domains = <&pm_domains DOMAIN_VAPE>;
0793
0794 status = "disabled";
0795 };
0796
0797 spi1: spi@80112000 {
0798 compatible = "arm,pl022", "arm,primecell";
0799 reg = <0x80112000 0x1000>;
0800 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0801 #address-cells = <1>;
0802 #size-cells = <0>;
0803 /* Same clock wired to kernel and pclk */
0804 clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
0805 clock-names = "sspclk", "apb_pclk";
0806 dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
0807 <&dma 35 0 0x0>; /* Logical - MemToDev */
0808 dma-names = "rx", "tx";
0809 power-domains = <&pm_domains DOMAIN_VAPE>;
0810
0811 status = "disabled";
0812 };
0813
0814 spi2: spi@80111000 {
0815 compatible = "arm,pl022", "arm,primecell";
0816 reg = <0x80111000 0x1000>;
0817 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
0818 #address-cells = <1>;
0819 #size-cells = <0>;
0820 /* Same clock wired to kernel and pclk */
0821 clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
0822 clock-names = "sspclk", "apb_pclk";
0823 dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
0824 <&dma 33 0 0x0>; /* Logical - MemToDev */
0825 dma-names = "rx", "tx";
0826 power-domains = <&pm_domains DOMAIN_VAPE>;
0827
0828 status = "disabled";
0829 };
0830
0831 spi3: spi@80129000 {
0832 compatible = "arm,pl022", "arm,primecell";
0833 reg = <0x80129000 0x1000>;
0834 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0835 #address-cells = <1>;
0836 #size-cells = <0>;
0837 /* Same clock wired to kernel and pclk */
0838 clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
0839 clock-names = "sspclk", "apb_pclk";
0840 dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
0841 <&dma 40 0 0x0>; /* Logical - MemToDev */
0842 dma-names = "rx", "tx";
0843 power-domains = <&pm_domains DOMAIN_VAPE>;
0844 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SPI3>;
0845
0846 status = "disabled";
0847 };
0848
0849 serial0: uart@80120000 {
0850 compatible = "arm,pl011", "arm,primecell";
0851 reg = <0x80120000 0x1000>;
0852 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
0853
0854 dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
0855 <&dma 13 0 0x0>; /* Logical - MemToDev */
0856 dma-names = "rx", "tx";
0857
0858 clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
0859 clock-names = "uart", "apb_pclk";
0860 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART0>;
0861
0862 status = "disabled";
0863 };
0864
0865 serial1: uart@80121000 {
0866 compatible = "arm,pl011", "arm,primecell";
0867 reg = <0x80121000 0x1000>;
0868 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
0869
0870 dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
0871 <&dma 12 0 0x0>; /* Logical - MemToDev */
0872 dma-names = "rx", "tx";
0873
0874 clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
0875 clock-names = "uart", "apb_pclk";
0876 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_UART1>;
0877
0878 status = "disabled";
0879 };
0880
0881 serial2: uart@80007000 {
0882 compatible = "arm,pl011", "arm,primecell";
0883 reg = <0x80007000 0x1000>;
0884 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0885
0886 dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
0887 <&dma 11 0 0x0>; /* Logical - MemToDev */
0888 dma-names = "rx", "tx";
0889
0890 clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
0891 clock-names = "uart", "apb_pclk";
0892 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_UART2>;
0893
0894 status = "disabled";
0895 };
0896
0897 mmc@80126000 {
0898 compatible = "arm,pl18x", "arm,primecell";
0899 reg = <0x80126000 0x1000>;
0900 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
0901
0902 dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
0903 <&dma 29 0 0x0>; /* Logical - MemToDev */
0904 dma-names = "rx", "tx";
0905
0906 clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
0907 clock-names = "sdi", "apb_pclk";
0908 power-domains = <&pm_domains DOMAIN_VAPE>;
0909 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_SDI0>;
0910
0911 status = "disabled";
0912 };
0913
0914 mmc@80118000 {
0915 compatible = "arm,pl18x", "arm,primecell";
0916 reg = <0x80118000 0x1000>;
0917 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
0918
0919 dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
0920 <&dma 32 0 0x0>; /* Logical - MemToDev */
0921 dma-names = "rx", "tx";
0922
0923 clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
0924 clock-names = "sdi", "apb_pclk";
0925 power-domains = <&pm_domains DOMAIN_VAPE>;
0926 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI1>;
0927
0928 status = "disabled";
0929 };
0930
0931 mmc@80005000 {
0932 compatible = "arm,pl18x", "arm,primecell";
0933 reg = <0x80005000 0x1000>;
0934 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
0935
0936 dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
0937 <&dma 28 0 0x0>; /* Logical - MemToDev */
0938 dma-names = "rx", "tx";
0939
0940 clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
0941 clock-names = "sdi", "apb_pclk";
0942 power-domains = <&pm_domains DOMAIN_VAPE>;
0943 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI2>;
0944
0945 status = "disabled";
0946 };
0947
0948 mmc@80119000 {
0949 compatible = "arm,pl18x", "arm,primecell";
0950 reg = <0x80119000 0x1000>;
0951 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
0952
0953 dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
0954 <&dma 41 0 0x0>; /* Logical - MemToDev */
0955 dma-names = "rx", "tx";
0956
0957 clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
0958 clock-names = "sdi", "apb_pclk";
0959 power-domains = <&pm_domains DOMAIN_VAPE>;
0960 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI3>;
0961
0962 status = "disabled";
0963 };
0964
0965 mmc@80114000 {
0966 compatible = "arm,pl18x", "arm,primecell";
0967 reg = <0x80114000 0x1000>;
0968 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
0969
0970 dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
0971 <&dma 42 0 0x0>; /* Logical - MemToDev */
0972 dma-names = "rx", "tx";
0973
0974 clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
0975 clock-names = "sdi", "apb_pclk";
0976 power-domains = <&pm_domains DOMAIN_VAPE>;
0977 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_SDI4>;
0978
0979 status = "disabled";
0980 };
0981
0982 mmc@80008000 {
0983 compatible = "arm,pl18x", "arm,primecell";
0984 reg = <0x80008000 0x1000>;
0985 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
0986
0987 dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
0988 <&dma 43 0 0x0>; /* Logical - MemToDev */
0989 dma-names = "rx", "tx";
0990
0991 clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
0992 clock-names = "sdi", "apb_pclk";
0993 power-domains = <&pm_domains DOMAIN_VAPE>;
0994 resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_SDI5>;
0995
0996 status = "disabled";
0997 };
0998
0999 sound {
1000 compatible = "stericsson,snd-soc-mop500";
1001 stericsson,cpu-dai = <&msp1 &msp3>;
1002 };
1003
1004 msp0: msp@80123000 {
1005 compatible = "stericsson,ux500-msp-i2s";
1006 reg = <0x80123000 0x1000>;
1007 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1008 v-ape-supply = <&db8500_vape_reg>;
1009
1010 dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
1011 <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
1012 dma-names = "rx", "tx";
1013
1014 clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
1015 clock-names = "msp", "apb_pclk";
1016 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP0>;
1017
1018 status = "disabled";
1019 };
1020
1021 msp1: msp@80124000 {
1022 compatible = "stericsson,ux500-msp-i2s";
1023 reg = <0x80124000 0x1000>;
1024 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1025 v-ape-supply = <&db8500_vape_reg>;
1026
1027 /* This DMA channel only exist on DB8500 v1 */
1028 dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
1029 dma-names = "tx";
1030
1031 clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
1032 clock-names = "msp", "apb_pclk";
1033 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP1>;
1034
1035 status = "disabled";
1036 };
1037
1038 // HDMI sound
1039 msp2: msp@80117000 {
1040 compatible = "stericsson,ux500-msp-i2s";
1041 reg = <0x80117000 0x1000>;
1042 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1043 v-ape-supply = <&db8500_vape_reg>;
1044
1045 dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */
1046 <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
1047 HighPrio - Fixed */
1048 dma-names = "rx", "tx";
1049
1050 clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
1051 clock-names = "msp", "apb_pclk";
1052 resets = <&prcc_reset DB8500_PRCC_2 DB8500_PRCC_2_RESET_MSP2>;
1053
1054 status = "disabled";
1055 };
1056
1057 msp3: msp@80125000 {
1058 compatible = "stericsson,ux500-msp-i2s";
1059 reg = <0x80125000 0x1000>;
1060 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1061 v-ape-supply = <&db8500_vape_reg>;
1062
1063 /* This DMA channel only exist on DB8500 v2 */
1064 dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
1065 dma-names = "rx";
1066
1067 clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
1068 clock-names = "msp", "apb_pclk";
1069 resets = <&prcc_reset DB8500_PRCC_1 DB8500_PRCC_1_RESET_MSP3>;
1070
1071 status = "disabled";
1072 };
1073
1074 external-bus@50000000 {
1075 compatible = "simple-bus";
1076 reg = <0x50000000 0x4000000>;
1077 #address-cells = <1>;
1078 #size-cells = <1>;
1079 ranges = <0 0x50000000 0x4000000>;
1080 status = "disabled";
1081 };
1082
1083 gpu@a0300000 {
1084 /*
1085 * This block is referred to as "Smart Graphics Adapter SGA500"
1086 * in documentation but is in practice a pretty straight-forward
1087 * MALI-400 GPU block.
1088 */
1089 compatible = "stericsson,db8500-mali", "arm,mali-400";
1090 reg = <0xa0300000 0x10000>;
1091 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1092 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1093 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1094 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1095 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1096 interrupt-names = "gp",
1097 "gpmmu",
1098 "pp0",
1099 "ppmmu0",
1100 "combined";
1101 clocks = <&prcmu_clk PRCMU_ACLK>, <&prcmu_clk PRCMU_SGACLK>;
1102 clock-names = "bus", "core";
1103 mali-supply = <&db8500_sga_reg>;
1104 power-domains = <&pm_domains DOMAIN_VAPE>;
1105 };
1106
1107 mcde@a0350000 {
1108 compatible = "ste,mcde";
1109 reg = <0xa0350000 0x1000>;
1110 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1111 epod-supply = <&db8500_b2r2_mcde_reg>;
1112 clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1113 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1114 <&prcmu_clk PRCMU_PLLDSI>; /* HDMI clock */
1115 clock-names = "mcde", "lcd", "hdmi";
1116 #address-cells = <1>;
1117 #size-cells = <1>;
1118 ranges;
1119 status = "disabled";
1120
1121 dsi0: dsi@a0351000 {
1122 compatible = "ste,mcde-dsi";
1123 reg = <0xa0351000 0x1000>;
1124 clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
1125 clock-names = "hs", "lp";
1126 #address-cells = <1>;
1127 #size-cells = <0>;
1128 };
1129 dsi1: dsi@a0352000 {
1130 compatible = "ste,mcde-dsi";
1131 reg = <0xa0352000 0x1000>;
1132 clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>;
1133 clock-names = "hs", "lp";
1134 #address-cells = <1>;
1135 #size-cells = <0>;
1136 };
1137 dsi2: dsi@a0353000 {
1138 compatible = "ste,mcde-dsi";
1139 reg = <0xa0353000 0x1000>;
1140 /* This DSI port only has the Low Power / Energy Save clock */
1141 clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>;
1142 clock-names = "lp";
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1145 };
1146 };
1147
1148 cryp@a03cb000 {
1149 compatible = "stericsson,ux500-cryp";
1150 reg = <0xa03cb000 0x1000>;
1151 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1152
1153 v-ape-supply = <&db8500_vape_reg>;
1154 clocks = <&prcc_pclk 6 1>;
1155 };
1156
1157 hash@a03c2000 {
1158 compatible = "stericsson,ux500-hash";
1159 reg = <0xa03c2000 0x1000>;
1160
1161 v-ape-supply = <&db8500_vape_reg>;
1162 clocks = <&prcc_pclk 6 2>;
1163 };
1164 };
1165 };
