boot/dts/st-pincfg.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ST_PINCFG_H_
0003 #define _ST_PINCFG_H_
0004
0005 /* Alternate functions */
0006 #define ALT1    1
0007 #define ALT2    2
0008 #define ALT3    3
0009 #define ALT4    4
0010 #define ALT5    5
0011 #define ALT6    6
0012 #define ALT7    7
0013
0014 /* Output enable */
0015 #define OE          (1 << 27)
0016 /* Pull Up */
0017 #define PU          (1 << 26)
0018 /* Open Drain */
0019 #define OD          (1 << 25)
0020 #define RT          (1 << 23)
0021 #define INVERTCLK       (1 << 22)
0022 #define CLKNOTDATA      (1 << 21)
0023 #define DOUBLE_EDGE     (1 << 20)
0024 #define CLK_A           (0 << 18)
0025 #define CLK_B           (1 << 18)
0026 #define CLK_C           (2 << 18)
0027 #define CLK_D           (3 << 18)
0028
0029 /* User-frendly defines for Pin Direction */
0030         /* oe = 0, pu = 0, od = 0 */
0031 #define IN          (0)
0032         /* oe = 0, pu = 1, od = 0 */
0033 #define IN_PU           (PU)
0034         /* oe = 1, pu = 0, od = 0 */
0035 #define OUT         (OE)
0036         /* oe = 1, pu = 0, od = 1 */
0037 #define BIDIR           (OE | OD)
0038         /* oe = 1, pu = 1, od = 1 */
0039 #define BIDIR_PU        (OE | PU | OD)
0040
0041 /* RETIME_TYPE */
0042 /*
0043  * B Mode
0044  * Bypass retime with optional delay parameter
0045  */
0046 #define BYPASS      (0)
0047 /*
0048  * R0, R1, R0D, R1D modes
0049  * single-edge data non inverted clock, retime data with clk
0050  */
0051 #define SE_NICLK_IO (RT)
0052 /*
0053  * RIV0, RIV1, RIV0D, RIV1D modes
0054  * single-edge data inverted clock, retime data with clk
0055  */
0056 #define SE_ICLK_IO  (RT | INVERTCLK)
0057 /*
0058  * R0E, R1E, R0ED, R1ED modes
0059  * double-edge data, retime data with clk
0060  */
0061 #define DE_IO       (RT | DOUBLE_EDGE)
0062 /*
0063  * CIV0, CIV1 modes with inverted clock
0064  * Retiming the clk pins will park clock & reduce the noise within the core.
0065  */
0066 #define ICLK        (RT | CLKNOTDATA | INVERTCLK)
0067 /*
0068  * CLK0, CLK1 modes with non-inverted clock
0069  * Retiming the clk pins will park clock & reduce the noise within the core.
0070  */
0071 #define NICLK       (RT | CLKNOTDATA)
0072 #endif /* _ST_PINCFG_H_ */