0001 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
0002 /*
0003 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
0004 */
0005
0006 #include "socfpga_cyclone5.dtsi"
0007 #include <dt-bindings/gpio/gpio.h>
0008 #include <dt-bindings/input/input.h>
0009
0010 / {
0011 model = "samtec VIN|ING FPGA";
0012 compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
0013
0014 chosen {
0015 bootargs = "earlyprintk";
0016 stdout-path = "serial0:115200n8";
0017 };
0018
0019 memory@0 {
0020 name = "memory";
0021 device_type = "memory";
0022 reg = <0x0 0x40000000>; /* 1GB */
0023 };
0024
0025 aliases {
0026 /*
0027 * This allow the ethaddr uboot environment variable contents
0028 * to be added to the gmac1 device tree blob.
0029 */
0030 ethernet0 = &gmac1;
0031 ethernet1 = &gmac0;
0032 };
0033
0034 gpio-keys {
0035 compatible = "gpio-keys";
0036
0037 hps_temp0 {
0038 label = "BTN_0"; /* TEMP_OS */
0039 gpios = <&portc 18 GPIO_ACTIVE_LOW>; /* HPS_GPI5 */
0040 linux,code = <BTN_0>;
0041 };
0042
0043 hps_hkey0 {
0044 label = "GP_SWITCH"; /* GP_SWITCH */
0045 gpios = <&portc 19 GPIO_ACTIVE_LOW>; /* HPS_GPI6 */
0046 linux,code = <BTN_1>;
0047 };
0048
0049 hps_hkey1 {
0050 label = "RESET_SWITCH"; /* RESET_SWITCH */
0051 gpios = <&portc 20 GPIO_ACTIVE_LOW>; /* HPS_GPI7 */
0052 linux,code = <BTN_2>;
0053 };
0054
0055 hps_hkey2 {
0056 label = "POWER_DOWN"; /* POWER_DOWN */
0057 gpios = <&portc 4 GPIO_ACTIVE_LOW>; /* HPS_GPIO62 */
0058 linux,code = <KEY_POWER>;
0059 };
0060
0061 hps_hkey3 {
0062 label = "SENSE"; /* SENSE */
0063 gpios = <&porta 9 GPIO_ACTIVE_LOW>; /* HPS_GPIO9 */
0064 linux,code = <BTN_3>;
0065 };
0066 };
0067
0068 regulator-usb-nrst {
0069 compatible = "regulator-fixed";
0070 regulator-name = "usb_nrst";
0071 regulator-min-microvolt = <5000000>;
0072 regulator-max-microvolt = <5000000>;
0073 gpio = <&portb 5 GPIO_ACTIVE_HIGH>;
0074 startup-delay-us = <70000>;
0075 enable-active-high;
0076 regulator-always-on;
0077 };
0078 };
0079
0080 &gmac1 {
0081 status = "okay";
0082 phy-mode = "rgmii";
0083 phy-handle = <&phy1>;
0084
0085 snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>;
0086 snps,reset-active-low;
0087 snps,reset-delays-us = <10000 10000 10000>;
0088
0089 mdio0 {
0090 #address-cells = <1>;
0091 #size-cells = <0>;
0092 compatible = "snps,dwmac-mdio";
0093 phy1: ethernet-phy@1 {
0094 reg = <1>;
0095 rxd0-skew-ps = <0>;
0096 rxd1-skew-ps = <0>;
0097 rxd2-skew-ps = <0>;
0098 rxd3-skew-ps = <0>;
0099 txd0-skew-ps = <0>;
0100 txd1-skew-ps = <0>;
0101 txd2-skew-ps = <0>;
0102 txd3-skew-ps = <0>;
0103 txen-skew-ps = <0>;
0104 txc-skew-ps = <1860>;
0105 rxdv-skew-ps = <0>;
0106 rxc-skew-ps = <1860>;
0107 };
0108 };
0109 };
0110
0111 &gpio0 { /* GPIO 0..29 */
0112 status = "okay";
0113 };
0114
0115 &gpio1 { /* GPIO 30..57 */
0116 status = "okay";
0117 };
0118
0119 &gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */
0120 status = "okay";
0121 };
0122
0123 &i2c0 {
0124 status = "okay";
0125
0126 gpio: pca9557@1f {
0127 compatible = "nxp,pca9557";
0128 reg = <0x1f>;
0129 gpio-controller;
0130 #gpio-cells = <2>;
0131 };
0132
0133 temp: lm75@48 {
0134 compatible = "lm75";
0135 reg = <0x48>;
0136 };
0137
0138 at24@50 {
0139 compatible = "atmel,24c01";
0140 pagesize = <8>;
0141 reg = <0x50>;
0142 };
0143
0144 i2cswitch@70 {
0145 compatible = "nxp,pca9548";
0146 #address-cells = <1>;
0147 #size-cells = <0>;
0148 reg = <0x70>;
0149
0150 i2c@0 {
0151 #address-cells = <1>;
0152 #size-cells = <0>;
0153 reg = <0>;
0154 };
0155
0156 i2c@1 {
0157 #address-cells = <1>;
0158 #size-cells = <0>;
0159 reg = <1>;
0160 };
0161
0162 i2c@2 {
0163 #address-cells = <1>;
0164 #size-cells = <0>;
0165 reg = <2>;
0166 };
0167
0168 i2c@3 {
0169 #address-cells = <1>;
0170 #size-cells = <0>;
0171 reg = <3>;
0172 };
0173
0174 i2c@4 {
0175 #address-cells = <1>;
0176 #size-cells = <0>;
0177 reg = <4>;
0178 };
0179
0180 i2c@5 {
0181 #address-cells = <1>;
0182 #size-cells = <0>;
0183 reg = <5>;
0184 };
0185
0186 i2c@6 { /* Backplane EEPROM */
0187 #address-cells = <1>;
0188 #size-cells = <0>;
0189 reg = <6>;
0190 eeprom@51 {
0191 compatible = "atmel,24c01";
0192 pagesize = <8>;
0193 reg = <0x51>;
0194 };
0195 };
0196
0197 i2c@7 { /* Power board EEPROM */
0198 #address-cells = <1>;
0199 #size-cells = <0>;
0200 reg = <7>;
0201 eeprom@51 {
0202 compatible = "atmel,24c01";
0203 pagesize = <8>;
0204 reg = <0x51>;
0205 };
0206 };
0207 };
0208 };
0209
0210 &i2c1 {
0211 status = "okay";
0212 clock-frequency = <100000>;
0213
0214 at24@50 {
0215 compatible = "atmel,24c02";
0216 pagesize = <8>;
0217 reg = <0x50>;
0218 };
0219 };
0220
0221 &qspi {
0222 status = "okay";
0223
0224 flash@0 {
0225 #address-cells = <1>;
0226 #size-cells = <1>;
0227 compatible = "micron,n25q128", "jedec,spi-nor";
0228 reg = <0>; /* chip select */
0229 spi-max-frequency = <100000000>;
0230 m25p,fast-read;
0231
0232 cdns,page-size = <256>;
0233 cdns,block-size = <16>;
0234 cdns,read-delay = <4>;
0235 cdns,tshsl-ns = <50>;
0236 cdns,tsd2d-ns = <50>;
0237 cdns,tchsh-ns = <4>;
0238 cdns,tslch-ns = <4>;
0239 };
0240
0241 flash@1 {
0242 #address-cells = <1>;
0243 #size-cells = <1>;
0244 compatible = "micron,mt25qu02g", "jedec,spi-nor";
0245 reg = <1>; /* chip select */
0246 spi-max-frequency = <100000000>;
0247 m25p,fast-read;
0248
0249 cdns,page-size = <256>;
0250 cdns,block-size = <16>;
0251 cdns,read-delay = <4>;
0252 cdns,tshsl-ns = <50>;
0253 cdns,tsd2d-ns = <50>;
0254 cdns,tchsh-ns = <4>;
0255 cdns,tslch-ns = <4>;
0256 };
0257 };
0258
0259 &usb0 {
0260 dr_mode = "host";
0261 status = "okay";
0262 };
0263
0264 &usb1 {
0265 dr_mode = "peripheral";
0266 status = "okay";
0267 };
