OSCL-LXR |
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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003 * Copyright (C) 2012 Altera <www.altera.com>
0004 */
0005
0006 #include <dt-bindings/reset/altr,rst-mgr.h>
0007
0008 / {
0009 #address-cells = <1>;
0010 #size-cells = <1>;
0011
0012 aliases {
0013 serial0 = &uart0;
0014 serial1 = &uart1;
0015 timer0 = &timer0;
0016 timer1 = &timer1;
0017 timer2 = &timer2;
0018 timer3 = &timer3;
0019 };
0020
0021 cpus {
0022 #address-cells = <1>;
0023 #size-cells = <0>;
0024 enable-method = "altr,socfpga-smp";
0025
0026 cpu0: cpu@0 {
0027 compatible = "arm,cortex-a9";
0028 device_type = "cpu";
0029 reg = <0>;
0030 next-level-cache = <&L2>;
0031 };
0032 cpu1: cpu@1 {
0033 compatible = "arm,cortex-a9";
0034 device_type = "cpu";
0035 reg = <1>;
0036 next-level-cache = <&L2>;
0037 };
0038 };
0039
0040 pmu: pmu@ff111000 {
0041 compatible = "arm,cortex-a9-pmu";
0042 interrupt-parent = <&intc>;
0043 interrupts = <0 176 4>, <0 177 4>;
0044 interrupt-affinity = <&cpu0>, <&cpu1>;
0045 reg = <0xff111000 0x1000>,
0046 <0xff113000 0x1000>;
0047 };
0048
0049 intc: interrupt-controller@fffed000 {
0050 compatible = "arm,cortex-a9-gic";
0051 #interrupt-cells = <3>;
0052 interrupt-controller;
0053 reg = <0xfffed000 0x1000>,
0054 <0xfffec100 0x100>;
0055 };
0056
0057 soc {
0058 #address-cells = <1>;
0059 #size-cells = <1>;
0060 compatible = "simple-bus";
0061 device_type = "soc";
0062 interrupt-parent = <&intc>;
0063 ranges;
0064
0065 amba {
0066 compatible = "simple-bus";
0067 #address-cells = <1>;
0068 #size-cells = <1>;
0069 ranges;
0070
0071 pdma: pdma@ffe01000 {
0072 compatible = "arm,pl330", "arm,primecell";
0073 reg = <0xffe01000 0x1000>;
0074 interrupts = <0 104 4>,
0075 <0 105 4>,
0076 <0 106 4>,
0077 <0 107 4>,
0078 <0 108 4>,
0079 <0 109 4>,
0080 <0 110 4>,
0081 <0 111 4>;
0082 #dma-cells = <1>;
0083 clocks = <&l4_main_clk>;
0084 clock-names = "apb_pclk";
0085 resets = <&rst DMA_RESET>;
0086 reset-names = "dma";
0087 };
0088 };
0089
0090 base_fpga_region {
0091 compatible = "fpga-region";
0092 fpga-mgr = <&fpgamgr0>;
0093
0094 #address-cells = <0x1>;
0095 #size-cells = <0x1>;
0096 };
0097
0098 can0: can@ffc00000 {
0099 compatible = "bosch,d_can";
0100 reg = <0xffc00000 0x1000>;
0101 interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
0102 clocks = <&can0_clk>;
0103 resets = <&rst CAN0_RESET>;
0104 status = "disabled";
0105 };
0106
0107 can1: can@ffc01000 {
0108 compatible = "bosch,d_can";
0109 reg = <0xffc01000 0x1000>;
0110 interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
0111 clocks = <&can1_clk>;
0112 resets = <&rst CAN1_RESET>;
0113 status = "disabled";
0114 };
0115
0116 clkmgr@ffd04000 {
0117 compatible = "altr,clk-mgr";
0118 reg = <0xffd04000 0x1000>;
0119
0120 clocks {
0121 #address-cells = <1>;
0122 #size-cells = <0>;
0123
0124 osc1: osc1 {
0125 #clock-cells = <0>;
0126 compatible = "fixed-clock";
0127 };
0128
0129 osc2: osc2 {
0130 #clock-cells = <0>;
0131 compatible = "fixed-clock";
0132 };
0133
0134 f2s_periph_ref_clk: f2s_periph_ref_clk {
0135 #clock-cells = <0>;
0136 compatible = "fixed-clock";
0137 };
0138
0139 f2s_sdram_ref_clk: f2s_sdram_ref_clk {
0140 #clock-cells = <0>;
0141 compatible = "fixed-clock";
0142 };
0143
0144 main_pll: main_pll@40 {
0145 #address-cells = <1>;
0146 #size-cells = <0>;
0147 #clock-cells = <0>;
0148 compatible = "altr,socfpga-pll-clock";
0149 clocks = <&osc1>;
0150 reg = <0x40>;
0151
0152 mpuclk: mpuclk@48 {
0153 #clock-cells = <0>;
0154 compatible = "altr,socfpga-perip-clk";
0155 clocks = <&main_pll>;
0156 div-reg = <0xe0 0 9>;
0157 reg = <0x48>;
0158 };
0159
0160 mainclk: mainclk@4c {
0161 #clock-cells = <0>;
0162 compatible = "altr,socfpga-perip-clk";
0163 clocks = <&main_pll>;
0164 div-reg = <0xe4 0 9>;
0165 reg = <0x4C>;
0166 };
0167
0168 dbg_base_clk: dbg_base_clk@50 {
0169 #clock-cells = <0>;
0170 compatible = "altr,socfpga-perip-clk";
0171 clocks = <&main_pll>, <&osc1>;
0172 div-reg = <0xe8 0 9>;
0173 reg = <0x50>;
0174 };
0175
0176 main_qspi_clk: main_qspi_clk@54 {
0177 #clock-cells = <0>;
0178 compatible = "altr,socfpga-perip-clk";
0179 clocks = <&main_pll>;
0180 reg = <0x54>;
0181 };
0182
0183 main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
0184 #clock-cells = <0>;
0185 compatible = "altr,socfpga-perip-clk";
0186 clocks = <&main_pll>;
0187 reg = <0x58>;
0188 };
0189
0190 cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
0191 #clock-cells = <0>;
0192 compatible = "altr,socfpga-perip-clk";
0193 clocks = <&main_pll>;
0194 reg = <0x5C>;
0195 };
0196 };
0197
0198 periph_pll: periph_pll@80 {
0199 #address-cells = <1>;
0200 #size-cells = <0>;
0201 #clock-cells = <0>;
0202 compatible = "altr,socfpga-pll-clock";
0203 clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
0204 reg = <0x80>;
0205
0206 emac0_clk: emac0_clk@88 {
0207 #clock-cells = <0>;
0208 compatible = "altr,socfpga-perip-clk";
0209 clocks = <&periph_pll>;
0210 reg = <0x88>;
0211 };
0212
0213 emac1_clk: emac1_clk@8c {
0214 #clock-cells = <0>;
0215 compatible = "altr,socfpga-perip-clk";
0216 clocks = <&periph_pll>;
0217 reg = <0x8C>;
0218 };
0219
0220 per_qspi_clk: per_qsi_clk@90 {
0221 #clock-cells = <0>;
0222 compatible = "altr,socfpga-perip-clk";
0223 clocks = <&periph_pll>;
0224 reg = <0x90>;
0225 };
0226
0227 per_nand_mmc_clk: per_nand_mmc_clk@94 {
0228 #clock-cells = <0>;
0229 compatible = "altr,socfpga-perip-clk";
0230 clocks = <&periph_pll>;
0231 reg = <0x94>;
0232 };
0233
0234 per_base_clk: per_base_clk@98 {
0235 #clock-cells = <0>;
0236 compatible = "altr,socfpga-perip-clk";
0237 clocks = <&periph_pll>;
0238 reg = <0x98>;
0239 };
0240
0241 h2f_usr1_clk: h2f_usr1_clk@9c {
0242 #clock-cells = <0>;
0243 compatible = "altr,socfpga-perip-clk";
0244 clocks = <&periph_pll>;
0245 reg = <0x9C>;
0246 };
0247 };
0248
0249 sdram_pll: sdram_pll@c0 {
0250 #address-cells = <1>;
0251 #size-cells = <0>;
0252 #clock-cells = <0>;
0253 compatible = "altr,socfpga-pll-clock";
0254 clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
0255 reg = <0xC0>;
0256
0257 ddr_dqs_clk: ddr_dqs_clk@c8 {
0258 #clock-cells = <0>;
0259 compatible = "altr,socfpga-perip-clk";
0260 clocks = <&sdram_pll>;
0261 reg = <0xC8>;
0262 };
0263
0264 ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
0265 #clock-cells = <0>;
0266 compatible = "altr,socfpga-perip-clk";
0267 clocks = <&sdram_pll>;
0268 reg = <0xCC>;
0269 };
0270
0271 ddr_dq_clk: ddr_dq_clk@d0 {
0272 #clock-cells = <0>;
0273 compatible = "altr,socfpga-perip-clk";
0274 clocks = <&sdram_pll>;
0275 reg = <0xD0>;
0276 };
0277
0278 h2f_usr2_clk: h2f_usr2_clk@d4 {
0279 #clock-cells = <0>;
0280 compatible = "altr,socfpga-perip-clk";
0281 clocks = <&sdram_pll>;
0282 reg = <0xD4>;
0283 };
0284 };
0285
0286 mpu_periph_clk: mpu_periph_clk {
0287 #clock-cells = <0>;
0288 compatible = "altr,socfpga-perip-clk";
0289 clocks = <&mpuclk>;
0290 fixed-divider = <4>;
0291 };
0292
0293 mpu_l2_ram_clk: mpu_l2_ram_clk {
0294 #clock-cells = <0>;
0295 compatible = "altr,socfpga-perip-clk";
0296 clocks = <&mpuclk>;
0297 fixed-divider = <2>;
0298 };
0299
0300 l4_main_clk: l4_main_clk {
0301 #clock-cells = <0>;
0302 compatible = "altr,socfpga-gate-clk";
0303 clocks = <&mainclk>;
0304 clk-gate = <0x60 0>;
0305 };
0306
0307 l3_main_clk: l3_main_clk {
0308 #clock-cells = <0>;
0309 compatible = "altr,socfpga-perip-clk";
0310 clocks = <&mainclk>;
0311 fixed-divider = <1>;
0312 };
0313
0314 l3_mp_clk: l3_mp_clk {
0315 #clock-cells = <0>;
0316 compatible = "altr,socfpga-gate-clk";
0317 clocks = <&mainclk>;
0318 div-reg = <0x64 0 2>;
0319 clk-gate = <0x60 1>;
0320 };
0321
0322 l3_sp_clk: l3_sp_clk {
0323 #clock-cells = <0>;
0324 compatible = "altr,socfpga-gate-clk";
0325 clocks = <&l3_mp_clk>;
0326 div-reg = <0x64 2 2>;
0327 };
0328
0329 l4_mp_clk: l4_mp_clk {
0330 #clock-cells = <0>;
0331 compatible = "altr,socfpga-gate-clk";
0332 clocks = <&mainclk>, <&per_base_clk>;
0333 div-reg = <0x64 4 3>;
0334 clk-gate = <0x60 2>;
0335 };
0336
0337 l4_sp_clk: l4_sp_clk {
0338 #clock-cells = <0>;
0339 compatible = "altr,socfpga-gate-clk";
0340 clocks = <&mainclk>, <&per_base_clk>;
0341 div-reg = <0x64 7 3>;
0342 clk-gate = <0x60 3>;
0343 };
0344
0345 dbg_at_clk: dbg_at_clk {
0346 #clock-cells = <0>;
0347 compatible = "altr,socfpga-gate-clk";
0348 clocks = <&dbg_base_clk>;
0349 div-reg = <0x68 0 2>;
0350 clk-gate = <0x60 4>;
0351 };
0352
0353 dbg_clk: dbg_clk {
0354 #clock-cells = <0>;
0355 compatible = "altr,socfpga-gate-clk";
0356 clocks = <&dbg_at_clk>;
0357 div-reg = <0x68 2 2>;
0358 clk-gate = <0x60 5>;
0359 };
0360
0361 dbg_trace_clk: dbg_trace_clk {
0362 #clock-cells = <0>;
0363 compatible = "altr,socfpga-gate-clk";
0364 clocks = <&dbg_base_clk>;
0365 div-reg = <0x6C 0 3>;
0366 clk-gate = <0x60 6>;
0367 };
0368
0369 dbg_timer_clk: dbg_timer_clk {
0370 #clock-cells = <0>;
0371 compatible = "altr,socfpga-gate-clk";
0372 clocks = <&dbg_base_clk>;
0373 clk-gate = <0x60 7>;
0374 };
0375
0376 cfg_clk: cfg_clk {
0377 #clock-cells = <0>;
0378 compatible = "altr,socfpga-gate-clk";
0379 clocks = <&cfg_h2f_usr0_clk>;
0380 clk-gate = <0x60 8>;
0381 };
0382
0383 h2f_user0_clk: h2f_user0_clk {
0384 #clock-cells = <0>;
0385 compatible = "altr,socfpga-gate-clk";
0386 clocks = <&cfg_h2f_usr0_clk>;
0387 clk-gate = <0x60 9>;
0388 };
0389
0390 emac_0_clk: emac_0_clk {
0391 #clock-cells = <0>;
0392 compatible = "altr,socfpga-gate-clk";
0393 clocks = <&emac0_clk>;
0394 clk-gate = <0xa0 0>;
0395 };
0396
0397 emac_1_clk: emac_1_clk {
0398 #clock-cells = <0>;
0399 compatible = "altr,socfpga-gate-clk";
0400 clocks = <&emac1_clk>;
0401 clk-gate = <0xa0 1>;
0402 };
0403
0404 usb_mp_clk: usb_mp_clk {
0405 #clock-cells = <0>;
0406 compatible = "altr,socfpga-gate-clk";
0407 clocks = <&per_base_clk>;
0408 clk-gate = <0xa0 2>;
0409 div-reg = <0xa4 0 3>;
0410 };
0411
0412 spi_m_clk: spi_m_clk {
0413 #clock-cells = <0>;
0414 compatible = "altr,socfpga-gate-clk";
0415 clocks = <&per_base_clk>;
0416 clk-gate = <0xa0 3>;
0417 div-reg = <0xa4 3 3>;
0418 };
0419
0420 can0_clk: can0_clk {
0421 #clock-cells = <0>;
0422 compatible = "altr,socfpga-gate-clk";
0423 clocks = <&per_base_clk>;
0424 clk-gate = <0xa0 4>;
0425 div-reg = <0xa4 6 3>;
0426 };
0427
0428 can1_clk: can1_clk {
0429 #clock-cells = <0>;
0430 compatible = "altr,socfpga-gate-clk";
0431 clocks = <&per_base_clk>;
0432 clk-gate = <0xa0 5>;
0433 div-reg = <0xa4 9 3>;
0434 };
0435
0436 gpio_db_clk: gpio_db_clk {
0437 #clock-cells = <0>;
0438 compatible = "altr,socfpga-gate-clk";
0439 clocks = <&per_base_clk>;
0440 clk-gate = <0xa0 6>;
0441 div-reg = <0xa8 0 24>;
0442 };
0443
0444 h2f_user1_clk: h2f_user1_clk {
0445 #clock-cells = <0>;
0446 compatible = "altr,socfpga-gate-clk";
0447 clocks = <&h2f_usr1_clk>;
0448 clk-gate = <0xa0 7>;
0449 };
0450
0451 sdmmc_clk: sdmmc_clk {
0452 #clock-cells = <0>;
0453 compatible = "altr,socfpga-gate-clk";
0454 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
0455 clk-gate = <0xa0 8>;
0456 clk-phase = <0 135>;
0457 };
0458
0459 sdmmc_clk_divided: sdmmc_clk_divided {
0460 #clock-cells = <0>;
0461 compatible = "altr,socfpga-gate-clk";
0462 clocks = <&sdmmc_clk>;
0463 clk-gate = <0xa0 8>;
0464 fixed-divider = <4>;
0465 };
0466
0467 nand_x_clk: nand_x_clk {
0468 #clock-cells = <0>;
0469 compatible = "altr,socfpga-gate-clk";
0470 clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
0471 clk-gate = <0xa0 9>;
0472 };
0473
0474 nand_ecc_clk: nand_ecc_clk {
0475 #clock-cells = <0>;
0476 compatible = "altr,socfpga-gate-clk";
0477 clocks = <&nand_x_clk>;
0478 clk-gate = <0xa0 9>;
0479 };
0480
0481 nand_clk: nand_clk {
0482 #clock-cells = <0>;
0483 compatible = "altr,socfpga-gate-clk";
0484 clocks = <&nand_x_clk>;
0485 clk-gate = <0xa0 10>;
0486 fixed-divider = <4>;
0487 };
0488
0489 qspi_clk: qspi_clk {
0490 #clock-cells = <0>;
0491 compatible = "altr,socfpga-gate-clk";
0492 clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
0493 clk-gate = <0xa0 11>;
0494 };
0495
0496 ddr_dqs_clk_gate: ddr_dqs_clk_gate {
0497 #clock-cells = <0>;
0498 compatible = "altr,socfpga-gate-clk";
0499 clocks = <&ddr_dqs_clk>;
0500 clk-gate = <0xd8 0>;
0501 };
0502
0503 ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
0504 #clock-cells = <0>;
0505 compatible = "altr,socfpga-gate-clk";
0506 clocks = <&ddr_2x_dqs_clk>;
0507 clk-gate = <0xd8 1>;
0508 };
0509
0510 ddr_dq_clk_gate: ddr_dq_clk_gate {
0511 #clock-cells = <0>;
0512 compatible = "altr,socfpga-gate-clk";
0513 clocks = <&ddr_dq_clk>;
0514 clk-gate = <0xd8 2>;
0515 };
0516
0517 h2f_user2_clk: h2f_user2_clk {
0518 #clock-cells = <0>;
0519 compatible = "altr,socfpga-gate-clk";
0520 clocks = <&h2f_usr2_clk>;
0521 clk-gate = <0xd8 3>;
0522 };
0523
0524 };
0525 };
0526
0527 fpga_bridge0: fpga_bridge@ff400000 {
0528 compatible = "altr,socfpga-lwhps2fpga-bridge";
0529 reg = <0xff400000 0x100000>;
0530 resets = <&rst LWHPS2FPGA_RESET>;
0531 clocks = <&l4_main_clk>;
0532 status = "disabled";
0533 };
0534
0535 fpga_bridge1: fpga_bridge@ff500000 {
0536 compatible = "altr,socfpga-hps2fpga-bridge";
0537 reg = <0xff500000 0x10000>;
0538 resets = <&rst HPS2FPGA_RESET>;
0539 clocks = <&l4_main_clk>;
0540 status = "disabled";
0541 };
0542
0543 fpga_bridge2: fpga-bridge@ff600000 {
0544 compatible = "altr,socfpga-fpga2hps-bridge";
0545 reg = <0xff600000 0x100000>;
0546 resets = <&rst FPGA2HPS_RESET>;
0547 clocks = <&l4_main_clk>;
0548 status = "disabled";
0549 };
0550
0551 fpga_bridge3: fpga-bridge@ffc25080 {
0552 compatible = "altr,socfpga-fpga2sdram-bridge";
0553 reg = <0xffc25080 0x4>;
0554 status = "disabled";
0555 };
0556
0557 fpgamgr0: fpgamgr@ff706000 {
0558 compatible = "altr,socfpga-fpga-mgr";
0559 reg = <0xff706000 0x1000
0560 0xffb90000 0x4>;
0561 interrupts = <0 175 4>;
0562 };
0563
0564 socfpga_axi_setup: stmmac-axi-config {
0565 snps,wr_osr_lmt = <0xf>;
0566 snps,rd_osr_lmt = <0xf>;
0567 snps,blen = <0 0 0 0 16 0 0>;
0568 };
0569
0570 gmac0: ethernet@ff700000 {
0571 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
0572 altr,sysmgr-syscon = <&sysmgr 0x60 0>;
0573 reg = <0xff700000 0x2000>;
0574 interrupts = <0 115 4>;
0575 interrupt-names = "macirq";
0576 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
0577 clocks = <&emac_0_clk>;
0578 clock-names = "stmmaceth";
0579 resets = <&rst EMAC0_RESET>;
0580 reset-names = "stmmaceth";
0581 snps,multicast-filter-bins = <256>;
0582 snps,perfect-filter-entries = <128>;
0583 tx-fifo-depth = <4096>;
0584 rx-fifo-depth = <4096>;
0585 snps,axi-config = <&socfpga_axi_setup>;
0586 status = "disabled";
0587 };
0588
0589 gmac1: ethernet@ff702000 {
0590 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
0591 altr,sysmgr-syscon = <&sysmgr 0x60 2>;
0592 reg = <0xff702000 0x2000>;
0593 interrupts = <0 120 4>;
0594 interrupt-names = "macirq";
0595 mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
0596 clocks = <&emac_1_clk>;
0597 clock-names = "stmmaceth";
0598 resets = <&rst EMAC1_RESET>;
0599 reset-names = "stmmaceth";
0600 snps,multicast-filter-bins = <256>;
0601 snps,perfect-filter-entries = <128>;
0602 tx-fifo-depth = <4096>;
0603 rx-fifo-depth = <4096>;
0604 snps,axi-config = <&socfpga_axi_setup>;
0605 status = "disabled";
0606 };
0607
0608 gpio0: gpio@ff708000 {
0609 #address-cells = <1>;
0610 #size-cells = <0>;
0611 compatible = "snps,dw-apb-gpio";
0612 reg = <0xff708000 0x1000>;
0613 clocks = <&l4_mp_clk>;
0614 resets = <&rst GPIO0_RESET>;
0615 status = "disabled";
0616
0617 porta: gpio-controller@0 {
0618 compatible = "snps,dw-apb-gpio-port";
0619 gpio-controller;
0620 #gpio-cells = <2>;
0621 snps,nr-gpios = <29>;
0622 reg = <0>;
0623 interrupt-controller;
0624 #interrupt-cells = <2>;
0625 interrupts = <0 164 4>;
0626 };
0627 };
0628
0629 gpio1: gpio@ff709000 {
0630 #address-cells = <1>;
0631 #size-cells = <0>;
0632 compatible = "snps,dw-apb-gpio";
0633 reg = <0xff709000 0x1000>;
0634 clocks = <&l4_mp_clk>;
0635 resets = <&rst GPIO1_RESET>;
0636 status = "disabled";
0637
0638 portb: gpio-controller@0 {
0639 compatible = "snps,dw-apb-gpio-port";
0640 gpio-controller;
0641 #gpio-cells = <2>;
0642 snps,nr-gpios = <29>;
0643 reg = <0>;
0644 interrupt-controller;
0645 #interrupt-cells = <2>;
0646 interrupts = <0 165 4>;
0647 };
0648 };
0649
0650 gpio2: gpio@ff70a000 {
0651 #address-cells = <1>;
0652 #size-cells = <0>;
0653 compatible = "snps,dw-apb-gpio";
0654 reg = <0xff70a000 0x1000>;
0655 clocks = <&l4_mp_clk>;
0656 resets = <&rst GPIO2_RESET>;
0657 status = "disabled";
0658
0659 portc: gpio-controller@0 {
0660 compatible = "snps,dw-apb-gpio-port";
0661 gpio-controller;
0662 #gpio-cells = <2>;
0663 snps,nr-gpios = <27>;
0664 reg = <0>;
0665 interrupt-controller;
0666 #interrupt-cells = <2>;
0667 interrupts = <0 166 4>;
0668 };
0669 };
0670
0671 i2c0: i2c@ffc04000 {
0672 #address-cells = <1>;
0673 #size-cells = <0>;
0674 compatible = "snps,designware-i2c";
0675 reg = <0xffc04000 0x1000>;
0676 resets = <&rst I2C0_RESET>;
0677 clocks = <&l4_sp_clk>;
0678 interrupts = <0 158 0x4>;
0679 status = "disabled";
0680 };
0681
0682 i2c1: i2c@ffc05000 {
0683 #address-cells = <1>;
0684 #size-cells = <0>;
0685 compatible = "snps,designware-i2c";
0686 reg = <0xffc05000 0x1000>;
0687 resets = <&rst I2C1_RESET>;
0688 clocks = <&l4_sp_clk>;
0689 interrupts = <0 159 0x4>;
0690 status = "disabled";
0691 };
0692
0693 i2c2: i2c@ffc06000 {
0694 #address-cells = <1>;
0695 #size-cells = <0>;
0696 compatible = "snps,designware-i2c";
0697 reg = <0xffc06000 0x1000>;
0698 resets = <&rst I2C2_RESET>;
0699 clocks = <&l4_sp_clk>;
0700 interrupts = <0 160 0x4>;
0701 status = "disabled";
0702 };
0703
0704 i2c3: i2c@ffc07000 {
0705 #address-cells = <1>;
0706 #size-cells = <0>;
0707 compatible = "snps,designware-i2c";
0708 reg = <0xffc07000 0x1000>;
0709 resets = <&rst I2C3_RESET>;
0710 clocks = <&l4_sp_clk>;
0711 interrupts = <0 161 0x4>;
0712 status = "disabled";
0713 };
0714
0715 eccmgr: eccmgr {
0716 compatible = "altr,socfpga-ecc-manager";
0717 #address-cells = <1>;
0718 #size-cells = <1>;
0719 ranges;
0720
0721 l2-ecc@ffd08140 {
0722 compatible = "altr,socfpga-l2-ecc";
0723 reg = <0xffd08140 0x4>;
0724 interrupts = <0 36 1>, <0 37 1>;
0725 };
0726
0727 ocram-ecc@ffd08144 {
0728 compatible = "altr,socfpga-ocram-ecc";
0729 reg = <0xffd08144 0x4>;
0730 iram = <&ocram>;
0731 interrupts = <0 178 1>, <0 179 1>;
0732 };
0733 };
0734
0735 L2: cache-controller@fffef000 {
0736 compatible = "arm,pl310-cache";
0737 reg = <0xfffef000 0x1000>;
0738 interrupts = <0 38 0x04>;
0739 cache-unified;
0740 cache-level = <2>;
0741 arm,tag-latency = <1 1 1>;
0742 arm,data-latency = <2 1 1>;
0743 prefetch-data = <1>;
0744 prefetch-instr = <1>;
0745 arm,shared-override;
0746 arm,double-linefill = <1>;
0747 arm,double-linefill-incr = <0>;
0748 arm,double-linefill-wrap = <1>;
0749 arm,prefetch-drop = <0>;
0750 arm,prefetch-offset = <7>;
0751 };
0752
0753 l3regs@0xff800000 {
0754 compatible = "altr,l3regs", "syscon";
0755 reg = <0xff800000 0x1000>;
0756 };
0757
0758 mmc: dwmmc0@ff704000 {
0759 compatible = "altr,socfpga-dw-mshc";
0760 reg = <0xff704000 0x1000>;
0761 interrupts = <0 139 4>;
0762 fifo-depth = <0x400>;
0763 #address-cells = <1>;
0764 #size-cells = <0>;
0765 clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
0766 clock-names = "biu", "ciu";
0767 resets = <&rst SDMMC_RESET>;
0768 status = "disabled";
0769 };
0770
0771 nand0: nand@ff900000 {
0772 #address-cells = <0x1>;
0773 #size-cells = <0x0>;
0774 compatible = "altr,socfpga-denali-nand";
0775 reg = <0xff900000 0x100000>,
0776 <0xffb80000 0x10000>;
0777 reg-names = "nand_data", "denali_reg";
0778 interrupts = <0x0 0x90 0x4>;
0779 clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
0780 clock-names = "nand", "nand_x", "ecc";
0781 resets = <&rst NAND_RESET>;
0782 status = "disabled";
0783 };
0784
0785 ocram: sram@ffff0000 {
0786 compatible = "mmio-sram";
0787 reg = <0xffff0000 0x10000>;
0788 };
0789
0790 qspi: spi@ff705000 {
0791 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
0792 #address-cells = <1>;
0793 #size-cells = <0>;
0794 reg = <0xff705000 0x1000>,
0795 <0xffa00000 0x1000>;
0796 interrupts = <0 151 4>;
0797 cdns,fifo-depth = <128>;
0798 cdns,fifo-width = <4>;
0799 cdns,trigger-address = <0x00000000>;
0800 clocks = <&qspi_clk>;
0801 resets = <&rst QSPI_RESET>;
0802 status = "disabled";
0803 };
0804
0805 rst: rstmgr@ffd05000 {
0806 #reset-cells = <1>;
0807 compatible = "altr,rst-mgr";
0808 reg = <0xffd05000 0x1000>;
0809 altr,modrst-offset = <0x10>;
0810 };
0811
0812 scu: snoop-control-unit@fffec000 {
0813 compatible = "arm,cortex-a9-scu";
0814 reg = <0xfffec000 0x100>;
0815 };
0816
0817 sdr: sdr@ffc25000 {
0818 compatible = "altr,sdr-ctl", "syscon";
0819 reg = <0xffc25000 0x1000>;
0820 resets = <&rst SDR_RESET>;
0821 };
0822
0823 sdramedac {
0824 compatible = "altr,sdram-edac";
0825 altr,sdr-syscon = <&sdr>;
0826 interrupts = <0 39 4>;
0827 };
0828
0829 spi0: spi@fff00000 {
0830 compatible = "snps,dw-apb-ssi";
0831 #address-cells = <1>;
0832 #size-cells = <0>;
0833 reg = <0xfff00000 0x1000>;
0834 interrupts = <0 154 4>;
0835 num-cs = <4>;
0836 clocks = <&spi_m_clk>;
0837 resets = <&rst SPIM0_RESET>;
0838 reset-names = "spi";
0839 status = "disabled";
0840 };
0841
0842 spi1: spi@fff01000 {
0843 compatible = "snps,dw-apb-ssi";
0844 #address-cells = <1>;
0845 #size-cells = <0>;
0846 reg = <0xfff01000 0x1000>;
0847 interrupts = <0 155 4>;
0848 num-cs = <4>;
0849 clocks = <&spi_m_clk>;
0850 resets = <&rst SPIM1_RESET>;
0851 reset-names = "spi";
0852 status = "disabled";
0853 };
0854
0855 sysmgr: sysmgr@ffd08000 {
0856 compatible = "altr,sys-mgr", "syscon";
0857 reg = <0xffd08000 0x4000>;
0858 };
0859
0860 /* Local timer */
0861 timer@fffec600 {
0862 compatible = "arm,cortex-a9-twd-timer";
0863 reg = <0xfffec600 0x100>;
0864 interrupts = <1 13 0xf01>;
0865 clocks = <&mpu_periph_clk>;
0866 };
0867
0868 timer0: timer0@ffc08000 {
0869 compatible = "snps,dw-apb-timer";
0870 interrupts = <0 167 4>;
0871 reg = <0xffc08000 0x1000>;
0872 clocks = <&l4_sp_clk>;
0873 clock-names = "timer";
0874 resets = <&rst SPTIMER0_RESET>;
0875 reset-names = "timer";
0876 };
0877
0878 timer1: timer1@ffc09000 {
0879 compatible = "snps,dw-apb-timer";
0880 interrupts = <0 168 4>;
0881 reg = <0xffc09000 0x1000>;
0882 clocks = <&l4_sp_clk>;
0883 clock-names = "timer";
0884 resets = <&rst SPTIMER1_RESET>;
0885 reset-names = "timer";
0886 };
0887
0888 timer2: timer2@ffd00000 {
0889 compatible = "snps,dw-apb-timer";
0890 interrupts = <0 169 4>;
0891 reg = <0xffd00000 0x1000>;
0892 clocks = <&osc1>;
0893 clock-names = "timer";
0894 resets = <&rst OSC1TIMER0_RESET>;
0895 reset-names = "timer";
0896 };
0897
0898 timer3: timer3@ffd01000 {
0899 compatible = "snps,dw-apb-timer";
0900 interrupts = <0 170 4>;
0901 reg = <0xffd01000 0x1000>;
0902 clocks = <&osc1>;
0903 clock-names = "timer";
0904 resets = <&rst OSC1TIMER1_RESET>;
0905 reset-names = "timer";
0906 };
0907
0908 uart0: serial0@ffc02000 {
0909 compatible = "snps,dw-apb-uart";
0910 reg = <0xffc02000 0x1000>;
0911 interrupts = <0 162 4>;
0912 reg-shift = <2>;
0913 reg-io-width = <4>;
0914 clocks = <&l4_sp_clk>;
0915 dmas = <&pdma 28>,
0916 <&pdma 29>;
0917 dma-names = "tx", "rx";
0918 resets = <&rst UART0_RESET>;
0919 };
0920
0921 uart1: serial1@ffc03000 {
0922 compatible = "snps,dw-apb-uart";
0923 reg = <0xffc03000 0x1000>;
0924 interrupts = <0 163 4>;
0925 reg-shift = <2>;
0926 reg-io-width = <4>;
0927 clocks = <&l4_sp_clk>;
0928 dmas = <&pdma 30>,
0929 <&pdma 31>;
0930 dma-names = "tx", "rx";
0931 resets = <&rst UART1_RESET>;
0932 };
0933
0934 usbphy0: usbphy {
0935 #phy-cells = <0>;
0936 compatible = "usb-nop-xceiv";
0937 status = "okay";
0938 };
0939
0940 usb0: usb@ffb00000 {
0941 compatible = "snps,dwc2";
0942 reg = <0xffb00000 0xffff>;
0943 interrupts = <0 125 4>;
0944 clocks = <&usb_mp_clk>;
0945 clock-names = "otg";
0946 resets = <&rst USB0_RESET>;
0947 reset-names = "dwc2";
0948 phys = <&usbphy0>;
0949 phy-names = "usb2-phy";
0950 status = "disabled";
0951 };
0952
0953 usb1: usb@ffb40000 {
0954 compatible = "snps,dwc2";
0955 reg = <0xffb40000 0xffff>;
0956 interrupts = <0 128 4>;
0957 clocks = <&usb_mp_clk>;
0958 clock-names = "otg";
0959 resets = <&rst USB1_RESET>;
0960 reset-names = "dwc2";
0961 phys = <&usbphy0>;
0962 phy-names = "usb2-phy";
0963 status = "disabled";
0964 };
0965
0966 watchdog0: watchdog@ffd02000 {
0967 compatible = "snps,dw-wdt";
0968 reg = <0xffd02000 0x1000>;
0969 interrupts = <0 171 4>;
0970 clocks = <&osc1>;
0971 resets = <&rst L4WD0_RESET>;
0972 status = "disabled";
0973 };
0974
0975 watchdog1: watchdog@ffd03000 {
0976 compatible = "snps,dw-wdt";
0977 reg = <0xffd03000 0x1000>;
0978 interrupts = <0 172 4>;
0979 clocks = <&osc1>;
0980 resets = <&rst L4WD1_RESET>;
0981 status = "disabled";
0982 };
0983 };
0984 };
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