0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003 * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
0004 *
0005 * Copyright (C) 2012 Renesas Solutions Corp.
0006 */
0007
0008 #include <dt-bindings/clock/sh73a0-clock.h>
0009 #include <dt-bindings/interrupt-controller/arm-gic.h>
0010 #include <dt-bindings/interrupt-controller/irq.h>
0011
0012 / {
0013 compatible = "renesas,sh73a0";
0014 interrupt-parent = <&gic>;
0015 #address-cells = <1>;
0016 #size-cells = <1>;
0017
0018 cpus {
0019 #address-cells = <1>;
0020 #size-cells = <0>;
0021
0022 cpu0: cpu@0 {
0023 device_type = "cpu";
0024 compatible = "arm,cortex-a9";
0025 reg = <0>;
0026 clock-frequency = <1196000000>;
0027 clocks = <&cpg_clocks SH73A0_CLK_Z>;
0028 power-domains = <&pd_a2sl>;
0029 next-level-cache = <&L2>;
0030 };
0031 cpu1: cpu@1 {
0032 device_type = "cpu";
0033 compatible = "arm,cortex-a9";
0034 reg = <1>;
0035 clock-frequency = <1196000000>;
0036 clocks = <&cpg_clocks SH73A0_CLK_Z>;
0037 power-domains = <&pd_a2sl>;
0038 next-level-cache = <&L2>;
0039 };
0040 };
0041
0042 timer@f0000200 {
0043 compatible = "arm,cortex-a9-global-timer";
0044 reg = <0xf0000200 0x100>;
0045 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
0046 clocks = <&periph_clk>;
0047 };
0048
0049 timer@f0000600 {
0050 compatible = "arm,cortex-a9-twd-timer";
0051 reg = <0xf0000600 0x20>;
0052 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
0053 clocks = <&periph_clk>;
0054 };
0055
0056 gic: interrupt-controller@f0001000 {
0057 compatible = "arm,cortex-a9-gic";
0058 #interrupt-cells = <3>;
0059 interrupt-controller;
0060 reg = <0xf0001000 0x1000>,
0061 <0xf0000100 0x100>;
0062 };
0063
0064 L2: cache-controller@f0100000 {
0065 compatible = "arm,pl310-cache";
0066 reg = <0xf0100000 0x1000>;
0067 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
0068 power-domains = <&pd_a3sm>;
0069 arm,data-latency = <3 3 3>;
0070 arm,tag-latency = <2 2 2>;
0071 arm,shared-override;
0072 cache-unified;
0073 cache-level = <2>;
0074 };
0075
0076 sbsc2: memory-controller@fb400000 {
0077 compatible = "renesas,sbsc-sh73a0";
0078 reg = <0xfb400000 0x400>;
0079 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
0080 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0081 interrupt-names = "sec", "temp";
0082 power-domains = <&pd_a4bc1>;
0083 };
0084
0085 sbsc1: memory-controller@fe400000 {
0086 compatible = "renesas,sbsc-sh73a0";
0087 reg = <0xfe400000 0x400>;
0088 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
0089 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
0090 interrupt-names = "sec", "temp";
0091 power-domains = <&pd_a4bc0>;
0092 };
0093
0094 pmu {
0095 compatible = "arm,cortex-a9-pmu";
0096 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
0097 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0098 interrupt-affinity = <&cpu0>, <&cpu1>;
0099 };
0100
0101 cmt1: timer@e6138000 {
0102 compatible = "renesas,sh73a0-cmt1";
0103 reg = <0xe6138000 0x200>;
0104 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0105 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
0106 clock-names = "fck";
0107 power-domains = <&pd_c5>;
0108 status = "disabled";
0109 };
0110
0111 irqpin0: interrupt-controller@e6900000 {
0112 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
0113 #interrupt-cells = <2>;
0114 interrupt-controller;
0115 reg = <0xe6900000 4>,
0116 <0xe6900010 4>,
0117 <0xe6900020 1>,
0118 <0xe6900040 1>,
0119 <0xe6900060 1>;
0120 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
0121 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
0122 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
0123 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
0124 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
0125 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
0126 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
0127 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0128 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
0129 power-domains = <&pd_a4s>;
0130 control-parent;
0131 };
0132
0133 irqpin1: interrupt-controller@e6900004 {
0134 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
0135 #interrupt-cells = <2>;
0136 interrupt-controller;
0137 reg = <0xe6900004 4>,
0138 <0xe6900014 4>,
0139 <0xe6900024 1>,
0140 <0xe6900044 1>,
0141 <0xe6900064 1>;
0142 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
0143 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
0144 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0145 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
0146 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0147 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
0148 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
0149 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
0150 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
0151 power-domains = <&pd_a4s>;
0152 control-parent;
0153 };
0154
0155 irqpin2: interrupt-controller@e6900008 {
0156 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
0157 #interrupt-cells = <2>;
0158 interrupt-controller;
0159 reg = <0xe6900008 4>,
0160 <0xe6900018 4>,
0161 <0xe6900028 1>,
0162 <0xe6900048 1>,
0163 <0xe6900068 1>;
0164 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
0165 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
0166 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
0167 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
0168 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
0169 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
0170 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
0171 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
0172 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
0173 power-domains = <&pd_a4s>;
0174 control-parent;
0175 };
0176
0177 irqpin3: interrupt-controller@e690000c {
0178 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
0179 #interrupt-cells = <2>;
0180 interrupt-controller;
0181 reg = <0xe690000c 4>,
0182 <0xe690001c 4>,
0183 <0xe690002c 1>,
0184 <0xe690004c 1>,
0185 <0xe690006c 1>;
0186 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
0187 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
0188 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
0189 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
0190 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
0191 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
0192 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
0193 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0194 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
0195 power-domains = <&pd_a4s>;
0196 control-parent;
0197 };
0198
0199 i2c0: i2c@e6820000 {
0200 #address-cells = <1>;
0201 #size-cells = <0>;
0202 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
0203 reg = <0xe6820000 0x425>;
0204 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
0205 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
0206 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
0207 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
0208 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
0209 power-domains = <&pd_a3sp>;
0210 status = "disabled";
0211 };
0212
0213 i2c1: i2c@e6822000 {
0214 #address-cells = <1>;
0215 #size-cells = <0>;
0216 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
0217 reg = <0xe6822000 0x425>;
0218 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
0219 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
0220 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
0221 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
0222 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
0223 power-domains = <&pd_a3sp>;
0224 status = "disabled";
0225 };
0226
0227 i2c2: i2c@e6824000 {
0228 #address-cells = <1>;
0229 #size-cells = <0>;
0230 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
0231 reg = <0xe6824000 0x425>;
0232 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
0233 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
0234 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
0235 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
0236 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
0237 power-domains = <&pd_a3sp>;
0238 status = "disabled";
0239 };
0240
0241 i2c3: i2c@e6826000 {
0242 #address-cells = <1>;
0243 #size-cells = <0>;
0244 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
0245 reg = <0xe6826000 0x425>;
0246 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
0247 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
0248 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
0249 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
0250 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
0251 power-domains = <&pd_a3sp>;
0252 status = "disabled";
0253 };
0254
0255 i2c4: i2c@e6828000 {
0256 #address-cells = <1>;
0257 #size-cells = <0>;
0258 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
0259 reg = <0xe6828000 0x425>;
0260 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
0261 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
0262 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
0263 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
0264 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
0265 power-domains = <&pd_c5>;
0266 status = "disabled";
0267 };
0268
0269 mmcif: mmc@e6bd0000 {
0270 compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif";
0271 reg = <0xe6bd0000 0x100>;
0272 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
0273 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
0274 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
0275 power-domains = <&pd_a3sp>;
0276 reg-io-width = <4>;
0277 status = "disabled";
0278 };
0279
0280 msiof0: spi@e6e20000 {
0281 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
0282 reg = <0xe6e20000 0x0064>;
0283 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
0284 clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>;
0285 power-domains = <&pd_a3sp>;
0286 #address-cells = <1>;
0287 #size-cells = <0>;
0288 status = "disabled";
0289 };
0290
0291 msiof1: spi@e6e10000 {
0292 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
0293 reg = <0xe6e10000 0x0064>;
0294 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0295 clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>;
0296 power-domains = <&pd_a3sp>;
0297 #address-cells = <1>;
0298 #size-cells = <0>;
0299 status = "disabled";
0300 };
0301
0302 msiof2: spi@e6e00000 {
0303 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
0304 reg = <0xe6e00000 0x0064>;
0305 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
0306 clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>;
0307 power-domains = <&pd_a3sp>;
0308 #address-cells = <1>;
0309 #size-cells = <0>;
0310 status = "disabled";
0311 };
0312
0313 msiof3: spi@e6c90000 {
0314 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
0315 reg = <0xe6c90000 0x0064>;
0316 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
0317 clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>;
0318 power-domains = <&pd_a3sp>;
0319 #address-cells = <1>;
0320 #size-cells = <0>;
0321 status = "disabled";
0322 };
0323
0324 sdhi0: mmc@ee100000 {
0325 compatible = "renesas,sdhi-sh73a0";
0326 reg = <0xee100000 0x100>;
0327 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
0328 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
0329 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
0330 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
0331 power-domains = <&pd_a3sp>;
0332 cap-sd-highspeed;
0333 status = "disabled";
0334 };
0335
0336 /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
0337 sdhi1: mmc@ee120000 {
0338 compatible = "renesas,sdhi-sh73a0";
0339 reg = <0xee120000 0x100>;
0340 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
0341 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
0342 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
0343 power-domains = <&pd_a3sp>;
0344 disable-wp;
0345 cap-sd-highspeed;
0346 status = "disabled";
0347 };
0348
0349 sdhi2: mmc@ee140000 {
0350 compatible = "renesas,sdhi-sh73a0";
0351 reg = <0xee140000 0x100>;
0352 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
0353 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
0354 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
0355 power-domains = <&pd_a3sp>;
0356 disable-wp;
0357 cap-sd-highspeed;
0358 status = "disabled";
0359 };
0360
0361 scifa0: serial@e6c40000 {
0362 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
0363 reg = <0xe6c40000 0x100>;
0364 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0365 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
0366 clock-names = "fck";
0367 power-domains = <&pd_a3sp>;
0368 status = "disabled";
0369 };
0370
0371 scifa1: serial@e6c50000 {
0372 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
0373 reg = <0xe6c50000 0x100>;
0374 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
0375 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
0376 clock-names = "fck";
0377 power-domains = <&pd_a3sp>;
0378 status = "disabled";
0379 };
0380
0381 scifa2: serial@e6c60000 {
0382 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
0383 reg = <0xe6c60000 0x100>;
0384 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
0385 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
0386 clock-names = "fck";
0387 power-domains = <&pd_a3sp>;
0388 status = "disabled";
0389 };
0390
0391 scifa3: serial@e6c70000 {
0392 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
0393 reg = <0xe6c70000 0x100>;
0394 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
0395 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
0396 clock-names = "fck";
0397 power-domains = <&pd_a3sp>;
0398 status = "disabled";
0399 };
0400
0401 scifa4: serial@e6c80000 {
0402 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
0403 reg = <0xe6c80000 0x100>;
0404 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
0405 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
0406 clock-names = "fck";
0407 power-domains = <&pd_a3sp>;
0408 status = "disabled";
0409 };
0410
0411 scifa5: serial@e6cb0000 {
0412 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
0413 reg = <0xe6cb0000 0x100>;
0414 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0415 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
0416 clock-names = "fck";
0417 power-domains = <&pd_a3sp>;
0418 status = "disabled";
0419 };
0420
0421 scifa6: serial@e6cc0000 {
0422 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
0423 reg = <0xe6cc0000 0x100>;
0424 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
0425 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
0426 clock-names = "fck";
0427 power-domains = <&pd_a3sp>;
0428 status = "disabled";
0429 };
0430
0431 scifa7: serial@e6cd0000 {
0432 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
0433 reg = <0xe6cd0000 0x100>;
0434 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
0435 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
0436 clock-names = "fck";
0437 power-domains = <&pd_a3sp>;
0438 status = "disabled";
0439 };
0440
0441 scifb: serial@e6c30000 {
0442 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
0443 reg = <0xe6c30000 0x100>;
0444 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
0445 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
0446 clock-names = "fck";
0447 power-domains = <&pd_a3sp>;
0448 status = "disabled";
0449 };
0450
0451 pfc: pinctrl@e6050000 {
0452 compatible = "renesas,pfc-sh73a0";
0453 reg = <0xe6050000 0x8000>,
0454 <0xe605801c 0x1c>;
0455 gpio-controller;
0456 #gpio-cells = <2>;
0457 gpio-ranges =
0458 <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>,
0459 <&pfc 288 288 22>;
0460 interrupts-extended =
0461 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
0462 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
0463 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
0464 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
0465 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
0466 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
0467 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
0468 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
0469 power-domains = <&pd_c5>;
0470 };
0471
0472 sysc: system-controller@e6180000 {
0473 compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
0474 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
0475
0476 pm-domains {
0477 pd_c5: c5 {
0478 #address-cells = <1>;
0479 #size-cells = <0>;
0480 #power-domain-cells = <0>;
0481
0482 pd_c4: c4@0 {
0483 reg = <0>;
0484 #power-domain-cells = <0>;
0485 };
0486
0487 pd_d4: d4@1 {
0488 reg = <1>;
0489 #power-domain-cells = <0>;
0490 };
0491
0492 pd_a4bc0: a4bc0@4 {
0493 reg = <4>;
0494 #power-domain-cells = <0>;
0495 };
0496
0497 pd_a4bc1: a4bc1@5 {
0498 reg = <5>;
0499 #power-domain-cells = <0>;
0500 };
0501
0502 pd_a4lc0: a4lc0@6 {
0503 reg = <6>;
0504 #power-domain-cells = <0>;
0505 };
0506
0507 pd_a4lc1: a4lc1@7 {
0508 reg = <7>;
0509 #power-domain-cells = <0>;
0510 };
0511
0512 pd_a4mp: a4mp@8 {
0513 reg = <8>;
0514 #address-cells = <1>;
0515 #size-cells = <0>;
0516 #power-domain-cells = <0>;
0517
0518 pd_a3mp: a3mp@9 {
0519 reg = <9>;
0520 #power-domain-cells = <0>;
0521 };
0522
0523 pd_a3vc: a3vc@10 {
0524 reg = <10>;
0525 #power-domain-cells = <0>;
0526 };
0527 };
0528
0529 pd_a4rm: a4rm@12 {
0530 reg = <12>;
0531 #address-cells = <1>;
0532 #size-cells = <0>;
0533 #power-domain-cells = <0>;
0534
0535 pd_a3r: a3r@13 {
0536 reg = <13>;
0537 #address-cells = <1>;
0538 #size-cells = <0>;
0539 #power-domain-cells = <0>;
0540
0541 pd_a2rv: a2rv@14 {
0542 reg = <14>;
0543 #address-cells = <1>;
0544 #size-cells = <0>;
0545 #power-domain-cells = <0>;
0546 };
0547 };
0548 };
0549
0550 pd_a4s: a4s@16 {
0551 reg = <16>;
0552 #address-cells = <1>;
0553 #size-cells = <0>;
0554 #power-domain-cells = <0>;
0555
0556 pd_a3sp: a3sp@17 {
0557 reg = <17>;
0558 #power-domain-cells = <0>;
0559 };
0560
0561 pd_a3sg: a3sg@18 {
0562 reg = <18>;
0563 #power-domain-cells = <0>;
0564 };
0565
0566 pd_a3sm: a3sm@19 {
0567 reg = <19>;
0568 #address-cells = <1>;
0569 #size-cells = <0>;
0570 #power-domain-cells = <0>;
0571
0572 pd_a2sl: a2sl@20 {
0573 reg = <20>;
0574 #power-domain-cells = <0>;
0575 };
0576 };
0577 };
0578 };
0579 };
0580 };
0581
0582 sh_fsi2: sound@ec230000 {
0583 #sound-dai-cells = <1>;
0584 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
0585 reg = <0xec230000 0x400>;
0586 interrupts = <GIC_SPI 146 0x4>;
0587 clocks = <&mstp3_clks SH73A0_CLK_FSI>;
0588 power-domains = <&pd_a4mp>;
0589 status = "disabled";
0590 };
0591
0592 bsc: bus@fec10000 {
0593 compatible = "renesas,bsc-sh73a0", "renesas,bsc",
0594 "simple-pm-bus";
0595 #address-cells = <1>;
0596 #size-cells = <1>;
0597 ranges = <0 0 0x20000000>;
0598 reg = <0xfec10000 0x400>;
0599 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
0600 clocks = <&zb_clk>;
0601 power-domains = <&pd_a4s>;
0602 };
0603
0604 clocks {
0605 #address-cells = <1>;
0606 #size-cells = <1>;
0607 ranges;
0608
0609 /* External root clocks */
0610 extalr_clk: extalr {
0611 compatible = "fixed-clock";
0612 #clock-cells = <0>;
0613 clock-frequency = <32768>;
0614 };
0615 extal1_clk: extal1 {
0616 compatible = "fixed-clock";
0617 #clock-cells = <0>;
0618 clock-frequency = <26000000>;
0619 };
0620 extal2_clk: extal2 {
0621 compatible = "fixed-clock";
0622 #clock-cells = <0>;
0623 /* This value must be overridden by the board. */
0624 clock-frequency = <0>;
0625 };
0626 extcki_clk: extcki {
0627 compatible = "fixed-clock";
0628 #clock-cells = <0>;
0629 /* This value can be overridden by the board. */
0630 clock-frequency = <0>;
0631 };
0632 fsiack_clk: fsiack {
0633 compatible = "fixed-clock";
0634 #clock-cells = <0>;
0635 /* This value can be overridden by the board. */
0636 clock-frequency = <0>;
0637 };
0638 fsibck_clk: fsibck {
0639 compatible = "fixed-clock";
0640 #clock-cells = <0>;
0641 /* This value can be overridden by the board. */
0642 clock-frequency = <0>;
0643 };
0644
0645 /* Special CPG clocks */
0646 cpg_clocks: cpg_clocks@e6150000 {
0647 compatible = "renesas,sh73a0-cpg-clocks";
0648 reg = <0xe6150000 0x10000>;
0649 clocks = <&extal1_clk>, <&extal2_clk>;
0650 #clock-cells = <1>;
0651 clock-output-names = "main", "pll0", "pll1", "pll2",
0652 "pll3", "dsi0phy", "dsi1phy",
0653 "zg", "m3", "b", "m1", "m2",
0654 "z", "zx", "hp";
0655 };
0656
0657 /* Variable factor clocks (DIV6) */
0658 vclk1_clk: vclk1@e6150008 {
0659 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
0660 reg = <0xe6150008 4>;
0661 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
0662 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
0663 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
0664 <0>;
0665 #clock-cells = <0>;
0666 };
0667 vclk2_clk: vclk2@e615000c {
0668 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
0669 reg = <0xe615000c 4>;
0670 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
0671 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
0672 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
0673 <0>;
0674 #clock-cells = <0>;
0675 };
0676 vclk3_clk: vclk3@e615001c {
0677 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
0678 reg = <0xe615001c 4>;
0679 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
0680 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
0681 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
0682 <0>;
0683 #clock-cells = <0>;
0684 };
0685 zb_clk: zb_clk@e6150010 {
0686 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
0687 reg = <0xe6150010 4>;
0688 clocks = <&pll1_div2_clk>, <0>,
0689 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
0690 #clock-cells = <0>;
0691 clock-output-names = "zb";
0692 };
0693 flctl_clk: flctlck@e6150014 {
0694 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
0695 reg = <0xe6150014 4>;
0696 clocks = <&pll1_div2_clk>, <0>,
0697 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
0698 #clock-cells = <0>;
0699 };
0700 sdhi0_clk: sdhi0ck@e6150074 {
0701 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
0702 reg = <0xe6150074 4>;
0703 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
0704 <&pll1_div13_clk>, <0>;
0705 #clock-cells = <0>;
0706 };
0707 sdhi1_clk: sdhi1ck@e6150078 {
0708 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
0709 reg = <0xe6150078 4>;
0710 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
0711 <&pll1_div13_clk>, <0>;
0712 #clock-cells = <0>;
0713 };
0714 sdhi2_clk: sdhi2ck@e615007c {
0715 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
0716 reg = <0xe615007c 4>;
0717 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
0718 <&pll1_div13_clk>, <0>;
0719 #clock-cells = <0>;
0720 };
0721 fsia_clk: fsia@e6150018 {
0722 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
0723 reg = <0xe6150018 4>;
0724 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
0725 <&fsiack_clk>, <&fsiack_clk>;
0726 #clock-cells = <0>;
0727 };
0728 fsib_clk: fsib@e6150090 {
0729 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
0730 reg = <0xe6150090 4>;
0731 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
0732 <&fsibck_clk>, <&fsibck_clk>;
0733 #clock-cells = <0>;
0734 };
0735 sub_clk: sub@e6150080 {
0736 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
0737 reg = <0xe6150080 4>;
0738 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
0739 <&extal2_clk>, <&extal2_clk>;
0740 #clock-cells = <0>;
0741 };
0742 spua_clk: spua@e6150084 {
0743 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
0744 reg = <0xe6150084 4>;
0745 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
0746 <&extal2_clk>, <&extal2_clk>;
0747 #clock-cells = <0>;
0748 };
0749 spuv_clk: spuv@e6150094 {
0750 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
0751 reg = <0xe6150094 4>;
0752 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
0753 <&extal2_clk>, <&extal2_clk>;
0754 #clock-cells = <0>;
0755 };
0756 msu_clk: msu@e6150088 {
0757 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
0758 reg = <0xe6150088 4>;
0759 clocks = <&pll1_div2_clk>, <0>,
0760 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
0761 #clock-cells = <0>;
0762 };
0763 hsi_clk: hsi@e615008c {
0764 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
0765 reg = <0xe615008c 4>;
0766 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
0767 <&pll1_div7_clk>, <0>;
0768 #clock-cells = <0>;
0769 };
0770 mfg1_clk: mfg1@e6150098 {
0771 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
0772 reg = <0xe6150098 4>;
0773 clocks = <&pll1_div2_clk>, <0>,
0774 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
0775 #clock-cells = <0>;
0776 };
0777 mfg2_clk: mfg2@e615009c {
0778 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
0779 reg = <0xe615009c 4>;
0780 clocks = <&pll1_div2_clk>, <0>,
0781 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
0782 #clock-cells = <0>;
0783 };
0784 dsit_clk: dsit@e6150060 {
0785 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
0786 reg = <0xe6150060 4>;
0787 clocks = <&pll1_div2_clk>, <0>,
0788 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
0789 #clock-cells = <0>;
0790 };
0791 dsi0p_clk: dsi0pck@e6150064 {
0792 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
0793 reg = <0xe6150064 4>;
0794 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
0795 <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
0796 <&extcki_clk>, <0>, <0>, <0>;
0797 #clock-cells = <0>;
0798 };
0799
0800 /* Fixed factor clocks */
0801 main_div2_clk: main_div2 {
0802 compatible = "fixed-factor-clock";
0803 clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
0804 #clock-cells = <0>;
0805 clock-div = <2>;
0806 clock-mult = <1>;
0807 };
0808 pll1_div2_clk: pll1_div2 {
0809 compatible = "fixed-factor-clock";
0810 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
0811 #clock-cells = <0>;
0812 clock-div = <2>;
0813 clock-mult = <1>;
0814 };
0815 pll1_div7_clk: pll1_div7 {
0816 compatible = "fixed-factor-clock";
0817 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
0818 #clock-cells = <0>;
0819 clock-div = <7>;
0820 clock-mult = <1>;
0821 };
0822 pll1_div13_clk: pll1_div13 {
0823 compatible = "fixed-factor-clock";
0824 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
0825 #clock-cells = <0>;
0826 clock-div = <13>;
0827 clock-mult = <1>;
0828 };
0829 periph_clk: periph {
0830 compatible = "fixed-factor-clock";
0831 clocks = <&cpg_clocks SH73A0_CLK_Z>;
0832 #clock-cells = <0>;
0833 clock-div = <4>;
0834 clock-mult = <1>;
0835 };
0836
0837 /* Gate clocks */
0838 mstp0_clks: mstp0_clks@e6150130 {
0839 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
0840 reg = <0xe6150130 4>, <0xe6150030 4>;
0841 clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>;
0842 #clock-cells = <1>;
0843 clock-indices = <
0844 SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0
0845 >;
0846 clock-output-names =
0847 "iic2", "msiof0";
0848 };
0849 mstp1_clks: mstp1_clks@e6150134 {
0850 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
0851 reg = <0xe6150134 4>, <0xe6150038 4>;
0852 clocks = <&cpg_clocks SH73A0_CLK_B>,
0853 <&cpg_clocks SH73A0_CLK_B>,
0854 <&cpg_clocks SH73A0_CLK_B>,
0855 <&cpg_clocks SH73A0_CLK_B>,
0856 <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
0857 <&cpg_clocks SH73A0_CLK_HP>,
0858 <&cpg_clocks SH73A0_CLK_ZG>,
0859 <&cpg_clocks SH73A0_CLK_B>;
0860 #clock-cells = <1>;
0861 clock-indices = <
0862 SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
0863 SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
0864 SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
0865 SH73A0_CLK_IIC0 SH73A0_CLK_SGX
0866 SH73A0_CLK_LCDC0
0867 >;
0868 clock-output-names =
0869 "ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
0870 "tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
0871 };
0872 mstp2_clks: mstp2_clks@e6150138 {
0873 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
0874 reg = <0xe6150138 4>, <0xe6150040 4>;
0875 clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
0876 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
0877 <&sub_clk>, <&sub_clk>, <&sub_clk>,
0878 <&sub_clk>, <&sub_clk>, <&sub_clk>,
0879 <&sub_clk>, <&sub_clk>, <&sub_clk>;
0880 #clock-cells = <1>;
0881 clock-indices = <
0882 SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
0883 SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3
0884 SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5
0885 SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2
0886 SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1
0887 SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3
0888 SH73A0_CLK_SCIFA4
0889 >;
0890 clock-output-names =
0891 "scifa7", "sy_dmac", "mp_dmac", "msiof3",
0892 "msiof1", "scifa5", "scifb", "msiof2",
0893 "scifa0", "scifa1", "scifa2", "scifa3",
0894 "scifa4";
0895 };
0896 mstp3_clks: mstp3_clks@e615013c {
0897 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
0898 reg = <0xe615013c 4>, <0xe6150048 4>;
0899 clocks = <&sub_clk>, <&extalr_clk>,
0900 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
0901 <&cpg_clocks SH73A0_CLK_HP>,
0902 <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
0903 <&sdhi0_clk>, <&sdhi1_clk>,
0904 <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
0905 <&main_div2_clk>, <&main_div2_clk>,
0906 <&main_div2_clk>, <&main_div2_clk>,
0907 <&main_div2_clk>;
0908 #clock-cells = <1>;
0909 clock-indices = <
0910 SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
0911 SH73A0_CLK_FSI SH73A0_CLK_IRDA
0912 SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
0913 SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
0914 SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
0915 SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
0916 SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
0917 SH73A0_CLK_TPU4
0918 >;
0919 clock-output-names =
0920 "scifa6", "cmt1", "fsi", "irda", "iic1",
0921 "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
0922 "tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
0923 };
0924 mstp4_clks: mstp4_clks@e6150140 {
0925 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
0926 reg = <0xe6150140 4>, <0xe615004c 4>;
0927 clocks = <&cpg_clocks SH73A0_CLK_HP>,
0928 <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
0929 #clock-cells = <1>;
0930 clock-indices = <
0931 SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
0932 SH73A0_CLK_KEYSC
0933 >;
0934 clock-output-names =
0935 "iic3", "iic4", "keysc";
0936 };
0937 mstp5_clks: mstp5_clks@e6150144 {
0938 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
0939 reg = <0xe6150144 4>, <0xe615003c 4>;
0940 clocks = <&cpg_clocks SH73A0_CLK_HP>;
0941 #clock-cells = <1>;
0942 clock-indices = <
0943 SH73A0_CLK_INTCA0
0944 >;
0945 clock-output-names =
0946 "intca0";
0947 };
0948 };
0949 };
