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OSCL-LXR

 
 

    


0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2020 HiSilicon Limited.
0004  *
0005  * DTS file for Hisilicon SD5203 Board
0006  */
0007 
0008 /dts-v1/;
0009 
0010 / {
0011         model = "Hisilicon SD5203";
0012         compatible = "H836ASDJ", "hisilicon,sd5203";
0013         interrupt-parent = <&vic>;
0014         #address-cells = <1>;
0015         #size-cells = <1>;
0016 
0017         chosen {
0018                 bootargs = "console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
0019         };
0020 
0021         aliases {
0022                 serial0 = &uart0;
0023         };
0024 
0025         cpus {
0026                 #address-cells = <1>;
0027                 #size-cells = <0>;
0028 
0029                 cpu0 {
0030                         device_type = "cpu";
0031                         compatible = "arm,arm926ej-s";
0032                         reg = <0x0>;
0033                 };
0034         };
0035 
0036         memory@30000000 {
0037                 device_type = "memory";
0038                 reg = <0x30000000 0x8000000>;
0039         };
0040 
0041         soc {
0042                 #address-cells = <1>;
0043                 #size-cells = <1>;
0044                 compatible = "simple-bus";
0045                 ranges;
0046 
0047                 vic: interrupt-controller@10130000 {
0048                         compatible = "snps,dw-apb-ictl";
0049                         reg = <0x10130000 0x1000>;
0050                         interrupt-controller;
0051                         #interrupt-cells = <1>;
0052                 };
0053 
0054                 refclk125mhz: refclk125mhz {
0055                         compatible = "fixed-clock";
0056                         #clock-cells = <0>;
0057                         clock-frequency = <125000000>;
0058                 };
0059 
0060                 timer0: timer@16002000 {
0061                         compatible = "arm,sp804", "arm,primecell";
0062                         reg = <0x16002000 0x1000>;
0063                         interrupts = <4>;
0064                         clocks = <&refclk125mhz>;
0065                         clock-names = "apb_pclk";
0066                 };
0067 
0068                 timer1: timer@16003000 {
0069                         compatible = "arm,sp804", "arm,primecell";
0070                         reg = <0x16003000 0x1000>;
0071                         interrupts = <5>;
0072                         clocks = <&refclk125mhz>;
0073                         clock-names = "apb_pclk";
0074                 };
0075 
0076                 uart0: serial@1600d000 {
0077                         compatible = "snps,dw-apb-uart";
0078                         reg = <0x1600d000 0x1000>;
0079                         bus_id = "uart0";
0080                         clocks = <&refclk125mhz>;
0081                         clock-names = "baudclk", "apb_pclk";
0082                         reg-shift = <2>;
0083                         interrupts = <17>;
0084                 };
0085 
0086                 uart1: serial@1600c000 {
0087                         compatible = "snps,dw-apb-uart";
0088                         reg = <0x1600c000 0x1000>;
0089                         clocks = <&refclk125mhz>;
0090                         clock-names = "baudclk", "apb_pclk";
0091                         reg-shift = <2>;
0092                         interrupts = <16>;
0093                         status = "disabled";
0094                 };
0095         };
0096 };