0001 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 /*
0003 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC
0004 *
0005 * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries
0006 *
0007 * Author: Eugen Hristev <eugen.hristev@microchip.com>
0008 * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
0009 *
0010 */
0011
0012 #include <dt-bindings/interrupt-controller/irq.h>
0013 #include <dt-bindings/interrupt-controller/arm-gic.h>
0014 #include <dt-bindings/clock/at91.h>
0015 #include <dt-bindings/dma/at91.h>
0016 #include <dt-bindings/gpio/gpio.h>
0017
0018 / {
0019 model = "Microchip SAMA7G5 family SoC";
0020 compatible = "microchip,sama7g5";
0021 #address-cells = <1>;
0022 #size-cells = <1>;
0023 interrupt-parent = <&gic>;
0024
0025 cpus {
0026 #address-cells = <1>;
0027 #size-cells = <0>;
0028
0029 cpu0: cpu@0 {
0030 device_type = "cpu";
0031 compatible = "arm,cortex-a7";
0032 reg = <0x0>;
0033 clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>;
0034 clock-names = "cpu";
0035 operating-points-v2 = <&cpu_opp_table>;
0036 };
0037 };
0038
0039 cpu_opp_table: opp-table {
0040 compatible = "operating-points-v2";
0041
0042 opp-90000000 {
0043 opp-hz = /bits/ 64 <90000000>;
0044 opp-microvolt = <1050000 1050000 1225000>;
0045 clock-latency-ns = <320000>;
0046 };
0047
0048 opp-250000000 {
0049 opp-hz = /bits/ 64 <250000000>;
0050 opp-microvolt = <1050000 1050000 1225000>;
0051 clock-latency-ns = <320000>;
0052 };
0053
0054 opp-600000000 {
0055 opp-hz = /bits/ 64 <600000000>;
0056 opp-microvolt = <1050000 1050000 1225000>;
0057 clock-latency-ns = <320000>;
0058 opp-suspend;
0059 };
0060
0061 opp-800000000 {
0062 opp-hz = /bits/ 64 <800000000>;
0063 opp-microvolt = <1150000 1125000 1225000>;
0064 clock-latency-ns = <320000>;
0065 };
0066
0067 opp-1000000002 {
0068 opp-hz = /bits/ 64 <1000000002>;
0069 opp-microvolt = <1250000 1225000 1300000>;
0070 clock-latency-ns = <320000>;
0071 };
0072 };
0073
0074 clocks {
0075 slow_xtal: slow_xtal {
0076 compatible = "fixed-clock";
0077 #clock-cells = <0>;
0078 };
0079
0080 main_xtal: main_xtal {
0081 compatible = "fixed-clock";
0082 #clock-cells = <0>;
0083 };
0084
0085 usb_clk: usb_clk {
0086 compatible = "fixed-clock";
0087 #clock-cells = <0>;
0088 clock-frequency = <48000000>;
0089 };
0090 };
0091
0092 vddout25: fixed-regulator-vddout25 {
0093 compatible = "regulator-fixed";
0094
0095 regulator-name = "VDDOUT25";
0096 regulator-min-microvolt = <2500000>;
0097 regulator-max-microvolt = <2500000>;
0098 regulator-boot-on;
0099 status = "disabled";
0100 };
0101
0102 ns_sram: sram@100000 {
0103 compatible = "mmio-sram";
0104 #address-cells = <1>;
0105 #size-cells = <1>;
0106 reg = <0x100000 0x20000>;
0107 ranges;
0108 };
0109
0110 soc {
0111 compatible = "simple-bus";
0112 #address-cells = <1>;
0113 #size-cells = <1>;
0114 ranges;
0115
0116 nfc_sram: sram@600000 {
0117 compatible = "mmio-sram";
0118 no-memory-wc;
0119 reg = <0x00600000 0x2400>;
0120 #address-cells = <1>;
0121 #size-cells = <1>;
0122 ranges = <0 0x00600000 0x2400>;
0123 };
0124
0125 nfc_io: nfc-io@10000000 {
0126 compatible = "atmel,sama5d3-nfc-io", "syscon";
0127 reg = <0x10000000 0x8000000>;
0128 };
0129
0130 ebi: ebi@40000000 {
0131 compatible = "atmel,sama5d3-ebi";
0132 #address-cells = <2>;
0133 #size-cells = <1>;
0134 atmel,smc = <&hsmc>;
0135 reg = <0x40000000 0x20000000>;
0136 ranges = <0x0 0x0 0x40000000 0x8000000
0137 0x1 0x0 0x48000000 0x8000000
0138 0x2 0x0 0x50000000 0x8000000
0139 0x3 0x0 0x58000000 0x8000000>;
0140 clocks = <&pmc PMC_TYPE_CORE PMC_MCK1>;
0141 status = "disabled";
0142
0143 nand_controller: nand-controller {
0144 compatible = "atmel,sama5d3-nand-controller";
0145 atmel,nfc-sram = <&nfc_sram>;
0146 atmel,nfc-io = <&nfc_io>;
0147 ecc-engine = <&pmecc>;
0148 #address-cells = <2>;
0149 #size-cells = <1>;
0150 ranges;
0151 status = "disabled";
0152 };
0153 };
0154
0155 securam: securam@e0000000 {
0156 compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram";
0157 reg = <0xe0000000 0x4000>;
0158 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
0159 #address-cells = <1>;
0160 #size-cells = <1>;
0161 ranges = <0 0xe0000000 0x4000>;
0162 no-memory-wc;
0163 };
0164
0165 secumod: secumod@e0004000 {
0166 compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon";
0167 reg = <0xe0004000 0x4000>;
0168 gpio-controller;
0169 #gpio-cells = <2>;
0170 };
0171
0172 sfrbu: sfr@e0008000 {
0173 compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon";
0174 reg = <0xe0008000 0x20>;
0175 };
0176
0177 pioA: pinctrl@e0014000 {
0178 compatible = "microchip,sama7g5-pinctrl";
0179 reg = <0xe0014000 0x800>;
0180 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0181 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
0182 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
0183 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
0184 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
0185 interrupt-controller;
0186 #interrupt-cells = <2>;
0187 gpio-controller;
0188 #gpio-cells = <2>;
0189 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
0190 };
0191
0192 pmc: pmc@e0018000 {
0193 compatible = "microchip,sama7g5-pmc", "syscon";
0194 reg = <0xe0018000 0x200>;
0195 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
0196 #clock-cells = <2>;
0197 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>;
0198 clock-names = "td_slck", "md_slck", "main_xtal";
0199 };
0200
0201 reset_controller: reset-controller@e001d000 {
0202 compatible = "microchip,sama7g5-rstc";
0203 reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>;
0204 #reset-cells = <1>;
0205 clocks = <&clk32k 0>;
0206 };
0207
0208 shdwc: shdwc@e001d010 {
0209 compatible = "microchip,sama7g5-shdwc", "syscon";
0210 reg = <0xe001d010 0x10>;
0211 clocks = <&clk32k 0>;
0212 #address-cells = <1>;
0213 #size-cells = <0>;
0214 atmel,wakeup-rtc-timer;
0215 atmel,wakeup-rtt-timer;
0216 status = "disabled";
0217 };
0218
0219 rtt: rtc@e001d020 {
0220 compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
0221 reg = <0xe001d020 0x30>;
0222 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
0223 clocks = <&clk32k 0>;
0224 };
0225
0226 clk32k: clock-controller@e001d050 {
0227 compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc";
0228 reg = <0xe001d050 0x4>;
0229 clocks = <&slow_xtal>;
0230 #clock-cells = <1>;
0231 };
0232
0233 gpbr: gpbr@e001d060 {
0234 compatible = "microchip,sama7g5-gpbr", "syscon";
0235 reg = <0xe001d060 0x48>;
0236 };
0237
0238 rtc: rtc@e001d0a8 {
0239 compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc";
0240 reg = <0xe001d0a8 0x30>;
0241 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
0242 clocks = <&clk32k 1>;
0243 };
0244
0245 ps_wdt: watchdog@e001d180 {
0246 compatible = "microchip,sama7g5-wdt";
0247 reg = <0xe001d180 0x24>;
0248 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0249 clocks = <&clk32k 0>;
0250 };
0251
0252 chipid@e0020000 {
0253 compatible = "microchip,sama7g5-chipid";
0254 reg = <0xe0020000 0x8>;
0255 };
0256
0257 tcb1: timer@e0800000 {
0258 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
0259 #address-cells = <1>;
0260 #size-cells = <0>;
0261 reg = <0xe0800000 0x100>;
0262 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
0263 clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>;
0264 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
0265 };
0266
0267 hsmc: hsmc@e0808000 {
0268 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
0269 reg = <0xe0808000 0x1000>;
0270 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
0271 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
0272 #address-cells = <1>;
0273 #size-cells = <1>;
0274 ranges;
0275
0276 pmecc: ecc-engine@e0808070 {
0277 compatible = "atmel,sama5d2-pmecc";
0278 reg = <0xe0808070 0x490>,
0279 <0xe0808500 0x200>;
0280 };
0281 };
0282
0283 qspi0: spi@e080c000 {
0284 compatible = "microchip,sama7g5-ospi";
0285 reg = <0xe080c000 0x400>, <0x20000000 0x10000000>;
0286 reg-names = "qspi_base", "qspi_mmap";
0287 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
0288 dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>,
0289 <&dma0 AT91_XDMAC_DT_PERID(40)>;
0290 dma-names = "tx", "rx";
0291 clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>;
0292 clock-names = "pclk", "gclk";
0293 #address-cells = <1>;
0294 #size-cells = <0>;
0295 status = "disabled";
0296 };
0297
0298 qspi1: spi@e0810000 {
0299 compatible = "microchip,sama7g5-qspi";
0300 reg = <0xe0810000 0x400>, <0x30000000 0x10000000>;
0301 reg-names = "qspi_base", "qspi_mmap";
0302 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
0303 dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>,
0304 <&dma0 AT91_XDMAC_DT_PERID(42)>;
0305 dma-names = "tx", "rx";
0306 clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>;
0307 clock-names = "pclk", "gclk";
0308 #address-cells = <1>;
0309 #size-cells = <0>;
0310 status = "disabled";
0311 };
0312
0313 can0: can@e0828000 {
0314 compatible = "bosch,m_can";
0315 reg = <0xe0828000 0x100>, <0x100000 0x7800>;
0316 reg-names = "m_can", "message_ram";
0317 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH
0318 GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
0319 interrupt-names = "int0", "int1";
0320 clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>;
0321 clock-names = "hclk", "cclk";
0322 assigned-clocks = <&pmc PMC_TYPE_GCK 61>;
0323 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
0324 assigned-clock-rates = <40000000>;
0325 bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
0326 status = "disabled";
0327 };
0328
0329 can1: can@e082c000 {
0330 compatible = "bosch,m_can";
0331 reg = <0xe082c000 0x100>, <0x100000 0xbc00>;
0332 reg-names = "m_can", "message_ram";
0333 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH
0334 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
0335 interrupt-names = "int0", "int1";
0336 clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>;
0337 clock-names = "hclk", "cclk";
0338 assigned-clocks = <&pmc PMC_TYPE_GCK 62>;
0339 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
0340 assigned-clock-rates = <40000000>;
0341 bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
0342 status = "disabled";
0343 };
0344
0345 can2: can@e0830000 {
0346 compatible = "bosch,m_can";
0347 reg = <0xe0830000 0x100>, <0x100000 0x10000>;
0348 reg-names = "m_can", "message_ram";
0349 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH
0350 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
0351 interrupt-names = "int0", "int1";
0352 clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>;
0353 clock-names = "hclk", "cclk";
0354 assigned-clocks = <&pmc PMC_TYPE_GCK 63>;
0355 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
0356 assigned-clock-rates = <40000000>;
0357 bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>;
0358 status = "disabled";
0359 };
0360
0361 can3: can@e0834000 {
0362 compatible = "bosch,m_can";
0363 reg = <0xe0834000 0x100>, <0x110000 0x4400>;
0364 reg-names = "m_can", "message_ram";
0365 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH
0366 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
0367 interrupt-names = "int0", "int1";
0368 clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>;
0369 clock-names = "hclk", "cclk";
0370 assigned-clocks = <&pmc PMC_TYPE_GCK 64>;
0371 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
0372 assigned-clock-rates = <40000000>;
0373 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
0374 status = "disabled";
0375 };
0376
0377 can4: can@e0838000 {
0378 compatible = "bosch,m_can";
0379 reg = <0xe0838000 0x100>, <0x110000 0x8800>;
0380 reg-names = "m_can", "message_ram";
0381 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH
0382 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
0383 interrupt-names = "int0", "int1";
0384 clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>;
0385 clock-names = "hclk", "cclk";
0386 assigned-clocks = <&pmc PMC_TYPE_GCK 65>;
0387 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
0388 assigned-clock-rates = <40000000>;
0389 bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>;
0390 status = "disabled";
0391 };
0392
0393 can5: can@e083c000 {
0394 compatible = "bosch,m_can";
0395 reg = <0xe083c000 0x100>, <0x110000 0xcc00>;
0396 reg-names = "m_can", "message_ram";
0397 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH
0398 GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
0399 interrupt-names = "int0", "int1";
0400 clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>;
0401 clock-names = "hclk", "cclk";
0402 assigned-clocks = <&pmc PMC_TYPE_GCK 66>;
0403 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
0404 assigned-clock-rates = <40000000>;
0405 bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>;
0406 status = "disabled";
0407 };
0408
0409 adc: adc@e1000000 {
0410 compatible = "microchip,sama7g5-adc";
0411 reg = <0xe1000000 0x200>;
0412 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
0413 clocks = <&pmc PMC_TYPE_GCK 26>;
0414 assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
0415 assigned-clock-rates = <100000000>;
0416 clock-names = "adc_clk";
0417 dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>;
0418 dma-names = "rx";
0419 atmel,min-sample-rate-hz = <200000>;
0420 atmel,max-sample-rate-hz = <20000000>;
0421 atmel,startup-time-ms = <4>;
0422 status = "disabled";
0423 };
0424
0425 sdmmc0: mmc@e1204000 {
0426 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
0427 reg = <0xe1204000 0x4000>;
0428 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
0429 clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>;
0430 clock-names = "hclock", "multclk";
0431 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
0432 assigned-clocks = <&pmc PMC_TYPE_GCK 80>;
0433 assigned-clock-rates = <200000000>;
0434 microchip,sdcal-inverted;
0435 status = "disabled";
0436 };
0437
0438 sdmmc1: mmc@e1208000 {
0439 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
0440 reg = <0xe1208000 0x4000>;
0441 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
0442 clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>;
0443 clock-names = "hclock", "multclk";
0444 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
0445 assigned-clocks = <&pmc PMC_TYPE_GCK 81>;
0446 assigned-clock-rates = <200000000>;
0447 microchip,sdcal-inverted;
0448 status = "disabled";
0449 };
0450
0451 sdmmc2: mmc@e120c000 {
0452 compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
0453 reg = <0xe120c000 0x4000>;
0454 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
0455 clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>;
0456 clock-names = "hclock", "multclk";
0457 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
0458 assigned-clocks = <&pmc PMC_TYPE_GCK 82>;
0459 assigned-clock-rates = <200000000>;
0460 microchip,sdcal-inverted;
0461 status = "disabled";
0462 };
0463
0464 pwm: pwm@e1604000 {
0465 compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm";
0466 reg = <0xe1604000 0x4000>;
0467 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
0468 #pwm-cells = <3>;
0469 clocks = <&pmc PMC_TYPE_PERIPHERAL 77>;
0470 status = "disabled";
0471 };
0472
0473 pdmc0: sound@e1608000 {
0474 compatible = "microchip,sama7g5-pdmc";
0475 reg = <0xe1608000 0x1000>;
0476 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
0477 #sound-dai-cells = <0>;
0478 dmas = <&dma0 AT91_XDMAC_DT_PERID(37)>;
0479 dma-names = "rx";
0480 clocks = <&pmc PMC_TYPE_PERIPHERAL 68>, <&pmc PMC_TYPE_GCK 68>;
0481 clock-names = "pclk", "gclk";
0482 status = "disabled";
0483 };
0484
0485 pdmc1: sound@e160c000 {
0486 compatible = "microchip,sama7g5-pdmc";
0487 reg = <0xe160c000 0x1000>;
0488 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
0489 #sound-dai-cells = <0>;
0490 dmas = <&dma0 AT91_XDMAC_DT_PERID(38)>;
0491 dma-names = "rx";
0492 clocks = <&pmc PMC_TYPE_PERIPHERAL 69>, <&pmc PMC_TYPE_GCK 69>;
0493 clock-names = "pclk", "gclk";
0494 status = "disabled";
0495 };
0496
0497 spdifrx: spdifrx@e1614000 {
0498 #sound-dai-cells = <0>;
0499 compatible = "microchip,sama7g5-spdifrx";
0500 reg = <0xe1614000 0x4000>;
0501 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
0502 dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>;
0503 dma-names = "rx";
0504 clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>;
0505 clock-names = "pclk", "gclk";
0506 status = "disabled";
0507 };
0508
0509 spdiftx: spdiftx@e1618000 {
0510 #sound-dai-cells = <0>;
0511 compatible = "microchip,sama7g5-spdiftx";
0512 reg = <0xe1618000 0x4000>;
0513 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
0514 dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>;
0515 dma-names = "tx";
0516 clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>;
0517 clock-names = "pclk", "gclk";
0518 };
0519
0520 i2s0: i2s@e161c000 {
0521 compatible = "microchip,sama7g5-i2smcc";
0522 #sound-dai-cells = <0>;
0523 reg = <0xe161c000 0x4000>;
0524 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
0525 dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>;
0526 dma-names = "tx", "rx";
0527 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>;
0528 clock-names = "pclk", "gclk";
0529 status = "disabled";
0530 };
0531
0532 i2s1: i2s@e1620000 {
0533 compatible = "microchip,sama7g5-i2smcc";
0534 #sound-dai-cells = <0>;
0535 reg = <0xe1620000 0x4000>;
0536 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
0537 dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>;
0538 dma-names = "tx", "rx";
0539 clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>;
0540 clock-names = "pclk", "gclk";
0541 status = "disabled";
0542 };
0543
0544 eic: interrupt-controller@e1628000 {
0545 compatible = "microchip,sama7g5-eic";
0546 reg = <0xe1628000 0xec>;
0547 interrupt-parent = <&gic>;
0548 interrupt-controller;
0549 #interrupt-cells = <2>;
0550 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
0551 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
0552 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
0553 clock-names = "pclk";
0554 status = "disabled";
0555 };
0556
0557 pit64b0: timer@e1800000 {
0558 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";
0559 reg = <0xe1800000 0x4000>;
0560 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
0561 clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>;
0562 clock-names = "pclk", "gclk";
0563 };
0564
0565 pit64b1: timer@e1804000 {
0566 compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";
0567 reg = <0xe1804000 0x4000>;
0568 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
0569 clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>;
0570 clock-names = "pclk", "gclk";
0571 };
0572
0573 aes: crypto@e1810000 {
0574 compatible = "atmel,at91sam9g46-aes";
0575 reg = <0xe1810000 0x100>;
0576 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
0577 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
0578 clock-names = "aes_clk";
0579 dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>,
0580 <&dma0 AT91_XDMAC_DT_PERID(2)>;
0581 dma-names = "tx", "rx";
0582 };
0583
0584 sha: crypto@e1814000 {
0585 compatible = "atmel,at91sam9g46-sha";
0586 reg = <0xe1814000 0x100>;
0587 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
0588 clocks = <&pmc PMC_TYPE_PERIPHERAL 83>;
0589 clock-names = "sha_clk";
0590 dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;
0591 dma-names = "tx";
0592 };
0593
0594 flx0: flexcom@e1818000 {
0595 compatible = "atmel,sama5d2-flexcom";
0596 reg = <0xe1818000 0x200>;
0597 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
0598 #address-cells = <1>;
0599 #size-cells = <1>;
0600 ranges = <0x0 0xe1818000 0x800>;
0601 status = "disabled";
0602
0603 uart0: serial@200 {
0604 compatible = "atmel,at91sam9260-usart";
0605 reg = <0x200 0x200>;
0606 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
0607 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
0608 clock-names = "usart";
0609 dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>,
0610 <&dma1 AT91_XDMAC_DT_PERID(5)>;
0611 dma-names = "tx", "rx";
0612 atmel,use-dma-rx;
0613 atmel,use-dma-tx;
0614 status = "disabled";
0615 };
0616 };
0617
0618 flx1: flexcom@e181c000 {
0619 compatible = "atmel,sama5d2-flexcom";
0620 reg = <0xe181c000 0x200>;
0621 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
0622 #address-cells = <1>;
0623 #size-cells = <1>;
0624 ranges = <0x0 0xe181c000 0x800>;
0625 status = "disabled";
0626
0627 i2c1: i2c@600 {
0628 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
0629 reg = <0x600 0x200>;
0630 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
0631 #address-cells = <1>;
0632 #size-cells = <0>;
0633 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
0634 atmel,fifo-size = <32>;
0635 dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>,
0636 <&dma0 AT91_XDMAC_DT_PERID(7)>;
0637 dma-names = "tx", "rx";
0638 status = "disabled";
0639 };
0640 };
0641
0642 flx3: flexcom@e1824000 {
0643 compatible = "atmel,sama5d2-flexcom";
0644 reg = <0xe1824000 0x200>;
0645 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
0646 #address-cells = <1>;
0647 #size-cells = <1>;
0648 ranges = <0x0 0xe1824000 0x800>;
0649 status = "disabled";
0650
0651 uart3: serial@200 {
0652 compatible = "atmel,at91sam9260-usart";
0653 reg = <0x200 0x200>;
0654 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
0655 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
0656 clock-names = "usart";
0657 dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>,
0658 <&dma1 AT91_XDMAC_DT_PERID(11)>;
0659 dma-names = "tx", "rx";
0660 atmel,use-dma-rx;
0661 atmel,use-dma-tx;
0662 status = "disabled";
0663 };
0664 };
0665
0666 trng: rng@e2010000 {
0667 compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng";
0668 reg = <0xe2010000 0x100>;
0669 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
0670 clocks = <&pmc PMC_TYPE_PERIPHERAL 97>;
0671 status = "disabled";
0672 };
0673
0674 tdes: crypto@e2014000 {
0675 compatible = "atmel,at91sam9g46-tdes";
0676 reg = <0xe2014000 0x100>;
0677 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
0678 clocks = <&pmc PMC_TYPE_PERIPHERAL 96>;
0679 clock-names = "tdes_clk";
0680 dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>,
0681 <&dma0 AT91_XDMAC_DT_PERID(53)>;
0682 dma-names = "tx", "rx";
0683 };
0684
0685 flx4: flexcom@e2018000 {
0686 compatible = "atmel,sama5d2-flexcom";
0687 reg = <0xe2018000 0x200>;
0688 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
0689 #address-cells = <1>;
0690 #size-cells = <1>;
0691 ranges = <0x0 0xe2018000 0x800>;
0692 status = "disabled";
0693
0694 uart4: serial@200 {
0695 compatible = "atmel,at91sam9260-usart";
0696 reg = <0x200 0x200>;
0697 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
0698 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
0699 clock-names = "usart";
0700 dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>,
0701 <&dma1 AT91_XDMAC_DT_PERID(13)>;
0702 dma-names = "tx", "rx";
0703 atmel,use-dma-rx;
0704 atmel,use-dma-tx;
0705 atmel,fifo-size = <16>;
0706 status = "disabled";
0707 };
0708 };
0709
0710 flx7: flexcom@e2024000 {
0711 compatible = "atmel,sama5d2-flexcom";
0712 reg = <0xe2024000 0x200>;
0713 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
0714 #address-cells = <1>;
0715 #size-cells = <1>;
0716 ranges = <0x0 0xe2024000 0x800>;
0717 status = "disabled";
0718
0719 uart7: serial@200 {
0720 compatible = "atmel,at91sam9260-usart";
0721 reg = <0x200 0x200>;
0722 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
0723 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
0724 clock-names = "usart";
0725 dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>,
0726 <&dma1 AT91_XDMAC_DT_PERID(19)>;
0727 dma-names = "tx", "rx";
0728 atmel,use-dma-rx;
0729 atmel,use-dma-tx;
0730 atmel,fifo-size = <16>;
0731 status = "disabled";
0732 };
0733 };
0734
0735 gmac0: ethernet@e2800000 {
0736 compatible = "microchip,sama7g5-gem";
0737 reg = <0xe2800000 0x1000>;
0738 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH
0739 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH
0740 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH
0741 GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH
0742 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH
0743 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
0744 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>;
0745 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
0746 assigned-clocks = <&pmc PMC_TYPE_GCK 51>;
0747 assigned-clock-rates = <125000000>;
0748 status = "disabled";
0749 };
0750
0751 gmac1: ethernet@e2804000 {
0752 compatible = "microchip,sama7g5-emac";
0753 reg = <0xe2804000 0x1000>;
0754 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH
0755 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
0756 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>;
0757 clock-names = "pclk", "hclk";
0758 status = "disabled";
0759 };
0760
0761 dma0: dma-controller@e2808000 {
0762 compatible = "microchip,sama7g5-dma";
0763 reg = <0xe2808000 0x1000>;
0764 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
0765 #dma-cells = <1>;
0766 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
0767 clock-names = "dma_clk";
0768 status = "disabled";
0769 };
0770
0771 dma1: dma-controller@e280c000 {
0772 compatible = "microchip,sama7g5-dma";
0773 reg = <0xe280c000 0x1000>;
0774 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
0775 #dma-cells = <1>;
0776 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
0777 clock-names = "dma_clk";
0778 status = "disabled";
0779 };
0780
0781 /* Place dma2 here despite it's address */
0782 dma2: dma-controller@e1200000 {
0783 compatible = "microchip,sama7g5-dma";
0784 reg = <0xe1200000 0x1000>;
0785 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
0786 #dma-cells = <1>;
0787 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
0788 clock-names = "dma_clk";
0789 dma-requests = <0>;
0790 status = "disabled";
0791 };
0792
0793 tcb0: timer@e2814000 {
0794 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
0795 #address-cells = <1>;
0796 #size-cells = <0>;
0797 reg = <0xe2814000 0x100>;
0798 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
0799 clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>;
0800 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
0801 };
0802
0803 flx8: flexcom@e2818000 {
0804 compatible = "atmel,sama5d2-flexcom";
0805 reg = <0xe2818000 0x200>;
0806 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
0807 #address-cells = <1>;
0808 #size-cells = <1>;
0809 ranges = <0x0 0xe2818000 0x800>;
0810 status = "disabled";
0811
0812 i2c8: i2c@600 {
0813 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
0814 reg = <0x600 0x200>;
0815 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0816 #address-cells = <1>;
0817 #size-cells = <0>;
0818 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
0819 atmel,fifo-size = <32>;
0820 dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>,
0821 <&dma0 AT91_XDMAC_DT_PERID(21)>;
0822 dma-names = "tx", "rx";
0823 status = "disabled";
0824 };
0825 };
0826
0827 flx9: flexcom@e281c000 {
0828 compatible = "atmel,sama5d2-flexcom";
0829 reg = <0xe281c000 0x200>;
0830 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
0831 #address-cells = <1>;
0832 #size-cells = <1>;
0833 ranges = <0x0 0xe281c000 0x800>;
0834 status = "disabled";
0835
0836 i2c9: i2c@600 {
0837 compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
0838 reg = <0x600 0x200>;
0839 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
0840 #address-cells = <1>;
0841 #size-cells = <0>;
0842 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
0843 atmel,fifo-size = <32>;
0844 dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>,
0845 <&dma0 AT91_XDMAC_DT_PERID(23)>;
0846 dma-names = "tx", "rx";
0847 status = "disabled";
0848 };
0849 };
0850
0851 flx11: flexcom@e2824000 {
0852 compatible = "atmel,sama5d2-flexcom";
0853 reg = <0xe2824000 0x200>;
0854 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
0855 #address-cells = <1>;
0856 #size-cells = <1>;
0857 ranges = <0x0 0xe2824000 0x800>;
0858 status = "disabled";
0859
0860 spi11: spi@400 {
0861 compatible = "atmel,at91rm9200-spi";
0862 reg = <0x400 0x200>;
0863 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
0864 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
0865 clock-names = "spi_clk";
0866 #address-cells = <1>;
0867 #size-cells = <0>;
0868 atmel,fifo-size = <32>;
0869 dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>,
0870 <&dma0 AT91_XDMAC_DT_PERID(28)>;
0871 dma-names = "rx", "tx";
0872 status = "disabled";
0873 };
0874 };
0875
0876 uddrc: uddrc@e3800000 {
0877 compatible = "microchip,sama7g5-uddrc";
0878 reg = <0xe3800000 0x4000>;
0879 };
0880
0881 ddr3phy: ddr3phy@e3804000 {
0882 compatible = "microchip,sama7g5-ddr3phy";
0883 reg = <0xe3804000 0x1000>;
0884 };
0885
0886 gic: interrupt-controller@e8c11000 {
0887 compatible = "arm,cortex-a7-gic";
0888 #interrupt-cells = <3>;
0889 #address-cells = <0>;
0890 interrupt-controller;
0891 reg = <0xe8c11000 0x1000>,
0892 <0xe8c12000 0x2000>;
0893 };
0894 };
0895 };
